RT9185
THERMAL CONSIDERATIONS
The RT9185 is a triple channel CMOS regulator
designed to provide two output voltage from one
package. Each output pin the RT9185 can deliver a
current of up to 1.5A, 0.8A and 0.3A respectively
over the full operating junction temperature range.
However, the maximum output current must be
derated at higher ambient temperature to ensure the
junction temperature does not exceed 125°C. With all
possible conditions, the junction temperature must be
within the range specified under operating conditions.
Each regulator contributes power dissipation to the
overall power dissipation of the package. Power
dissipation can be calculated based on the output
current and the voltage drop across each regulator.
P
D
= (V
DD
–V
OUT1
) I
OUT1
+ (V
DD
– V
OUT2
) I
OUT2
+
(V
DD
– V
OUT3
) I
OUT3
+ V
IN
I
GND
Although the device is rated for 1.5A, 0.8A and 0.3A
of output current, the application may limit the
amount of output current based on the total power
dissipation and the ambient temperature. The final
operating junction temperature for any set of
conditions can be estimated by the following thermal
equation:
P
D (MAX)
= ( T
J (MAX)
−
T
A
) /
θ
JA
Where T
J (MAX)
is the maximum junction temperature
of the die (125°C) and T
A
is the maximum ambient
temperature.
θ
J
A
is the thermal resistance from the
junction to the surrounding environment which is
combined with
θ
J
C
+
θ
CA
. Where
θ
J
C
is junction to
case thermal resistance which for fused SOP-8 is
20°C/W, TO-252-5 is 10°C/W and TO-263-5 is
5.5°C/W,
θ
CA
is case to ambient thermal resistance
which depend on PCB board area and air flow.
PCB LAYOUT
The RT9185 is a fixed output voltage regulator which
the voltage are sensed at the output pin. A long PCB
trace to load will cause a voltage drop between load
and RT9185. Be careful with PCB layout which
minimum the output trace length and maximum the
trace width.
TRACE RESISTANCE
RP
RT9185
VDD
+
VOUT1
VOUT3
VOUT2
GND
GND PLANE
I
O
DROP = I
O
* RP
+
LOAD
The GND pin of the RT9185 performs the dual
function of providing an electrical connection to
ground and channeling heat away. Connect the GND
pin to ground using a large pad or ground plane.
Good board layout practices must be used or
instability can be induced because of ground loops
and voltage drops. The input and output capacitors
MUST
be directly connected to the input, output, and
ground pins of the device using traces which have no
other currents flowing through them. The best way to
do this is to layout C
IN
and C
OUT
near the device with
short traces to the V
DD
, V
OUT
, and ground pins.
The regulator ground pin should be connected to the
external circuit ground so that the regulator and its
capacitors have a “single point ground”.
It should be noted that stability problems have been
seen in applications where “vias” to an internal
ground plane were used at the ground points of the
device and the input and output capacitors. This was
caused by varying ground potentials at these nodes
resulting from current flowing through the ground
plane. Using a single point ground technique for the
regulator and it’s capacitors fixed the problem. Since
high current flows through the traces going into V
IN
and coming from V
OUT
, Kelvin connect the capacitor
leads to these pins so there is no voltage drop in
series with the input and output capacitors.
Optimum performance can only be achieved when
the device is mounted on a PC board according to
the diagram below:
www.richtek.com
DS9185-02 July 2003
10
ETC [ ETC ]
