Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
FEATURES
•
’Trench’
technology
• Very low on-state resistance
• Fast switching
• Low thermal resistance
• Logic level compatible
PHP55N04LT, PHB55N04LT
PHD55N04LT
QUICK REFERENCE DATA
d
SYMBOL
V
DSS
= 35 V
I
D
= 55 A
R
DS(ON)
≤
14 mΩ (V
GS
= 10 V)
R
DS(ON)
≤
18 mΩ (V
GS
= 5 V)
g
s
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:-
• High frequency computer motherboard d.c. to d.c. converters
• High current switching
The PHP55N04LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB55N04LT is supplied in the SOT404 (D
2
PAK) surface mounting package.
The PHD55N04LT is supplied in the SOT428 (DPAK)surface mounting package.
PINNING
PIN
1
2
3
tab
DESCRIPTION
gate
drain
1
source
SOT78 (TO220AB)
tab
SOT404 (D
2
PAK)
tab
SOT428 (DPAK)
tab
2
1 23
2
1
3
1
3
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
DM
P
tot
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage (DC)
Gate-source voltage (pulse
peak value)
Drain current (DC)
Drain current (pulse peak
value)
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
T
j
= 25 ˚C to 175˚C
T
j
= 25 ˚C to 175˚C; R
GS
= 20 kΩ
T
j
≤
150˚C
T
mb
= 25 ˚C
T
mb
= 100 ˚C
T
mb
= 25 ˚C
T
mb
= 25 ˚C
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
35
35
±
15
±
20
55
38
220
103
175
UNIT
V
V
V
V
A
A
A
W
˚C
1
It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
January 2001
1
Rev 1.000