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产品型号2305B-1DC的Datasheet PDF文件预览

IDT2305B  
3.3V ZERO DELAY  
CLOCK BUFFER  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution  
• 10MHz to 133MHz operating frequency  
• Distributes one clock input to one bank of five outputs  
• Zero Input-Output Delay  
The IDT2305B is a high-speed phase-lock loop (PLL) clock buffer,  
designed to address high-speed clock distribution applications. The zero  
delay is achieved by aligning the phase between the incoming clock and  
the output clock, operable within the range of 10 to 133MHz.  
• Output Skew < 250ps  
The IDT2305B is an 8-pin version of the IDT2309B. IDT2305B accepts  
one reference input, and drives out five low skew clocks. The -1H version  
of this device operates, up to 133MHz frequency and has a higher drive  
thanthe-1device. Allpartshaveon-chipPLLswhichlocktoaninputclock  
on the REF pin. The PLL feedback is on-chip and is obtained from the  
CLKOUTpad.Intheabsenceofaninputclock,theIDT2305Benterspower  
down. In this mode, the device will draw less than 25µA, the outputs are  
tri-stated, and the PLL is not running, resulting in a significant reduction of  
power.  
• Low jitter <175 ps cycle-to-cycle  
• 50ps typical cycle-to-cycle jitter (15pF, 66MHz)  
• IDT2305B-1 for Standard Drive  
• IDT2305B-1H for High Drive  
• No external RC network required  
• Operates at 3.3V VDD  
• Power down mode  
• Available in SOIC and TSSOP packages  
The IDT2305B is characterized for both Industrial and Commercial  
operation.  
NOTE: EOL for non-green parts to occur on 5/13/10 per  
PDNU-09-01  
FUNCTIONALBLOCKDIAGRAM  
8
CLKOUT  
3
CLK1  
PLL  
1
Control  
Logic  
REF  
2
CLK2  
CLK3  
CLK4  
5
7
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
AUGUST 2009  
1
c
2007 Integrated Device Technology, Inc.  
DSC 6994/5  
IDT2305B  
3.3VZERODELAYCLOCKBUFFER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
PINCONFIGURATION  
ABSOLUTEMAXIMUMRATINGS(1)  
Symbol  
Rating  
Max.  
–0.5to+4.6  
–0.5to+5.5  
–0.5to  
VDD+0.5  
–50  
Unit  
V
VDD  
SupplyVoltageRange  
InputVoltageRange(REF)  
InputVoltageRange  
(except REF)  
(2)  
VI  
VI  
V
V
1
REF  
8
7
6
5
CLKOUT  
CLK4  
CLK2  
2
IIK (VI < 0)  
IO (VO = 0 to VDD)  
VDD or GND  
TA = 55°C  
(instillair)(3)  
TSTG  
InputClampCurrent  
ContinuousOutputCurrent  
ContinuousCurrent  
mA  
mA  
mA  
W
±50  
VDD  
3
4
CLK1  
GND  
±100  
MaximumPowerDissipation  
0.7  
CLK3  
StorageTemperatureRange  
CommercialTemperature  
Range  
–65to+150  
0 to +70  
°C  
°C  
SOIC/TSSOP  
TOP VIEW  
Operating  
Temperature  
Operating  
IndustrialTemperature  
Range  
-40to+85  
°C  
Temperature  
NOTES:  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
2. The input and output negative-voltage ratings may be exceeded if the input and output  
clamp-current ratings are observed.  
3. The maximum package power dissipation is calculated using a junction temperature  
of 150°C and a board trace length of 750 mils.  
APPLICATIONS:  
SDRAM  
Telecom  
Datacom  
PC Motherboards/Workstations  
Critical Path Delay Designs  
PINDESCRIPTION  
Pin Name  
REF(1)  
Pin Number  
Type  
IN  
FunctionalDescription  
1
2
3
4
5
6
7
Inputreferenceclock, 5Volttolerantinput  
Output clock  
CLK2(2)  
CLK1(2)  
GND  
Out  
Out  
Output clock  
Ground  
Out  
Ground  
CLK3(2)  
Output clock  
VDD  
CLK4(2)  
PWR  
Out  
3.3V Supply  
Output clock  
CLKOUT(2)  
8
Out  
Outputclock, internalfeedbackonthispin  
NOTES:  
1. Weak pull down.  
2. Weak pull down on all outputs.  
2
IDT2305B  
3.3VZERODELAYCLOCKBUFFER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
OPERATINGCONDITIONS-COMMERCIAL  
Symbol  
Parameter  
Min.  
3
Max.  
3.6  
70  
Unit  
V
VDD  
SupplyVoltage  
TA  
OperatingTemperature(AmbientTemperature)  
Load Capacitance < 100MHz  
0
°C  
pF  
CL  
30  
Load Capacitance 100MHz - 133MHz  
InputCapacitance  
10  
CIN  
7
pF  
DCELECTRICALCHARACTERISTICS-COMMERCIAL  
Symbol  
VIL  
Parameter  
Conditions  
Min.  
2
Max.  
0.8  
Unit  
V
InputLOWVoltageLevel  
Input HIGH Voltage Level  
InputLOWCurrent  
Input HIGH Current  
OutputLOWVoltage  
VIH  
V
IIL  
VIN = 0V  
50  
µA  
µA  
V
IIH  
VIN = VDD  
100  
0.4  
VOL  
StandardDrive  
High Drive  
IOL = 8mA  
IOL = 12mA (-1H)  
IOH = -8mA  
VOH  
Output HIGH Voltage  
StandardDrive  
High Drive  
2.4  
V
IOH = -12mA (-1H)  
IDD_PD  
IDD  
Power Down Current  
SupplyCurrent  
REF = 0MHz  
12  
32  
µA  
mA  
UnloadedOutputsat 66.66MHz  
SWITCHINGCHARACTERISTICS(2305B-1)-COMMERCIAL(1,2)  
Symbol  
Parameter  
Conditions  
Min.  
10  
10  
40  
Typ.  
Max.  
Unit  
t1  
OutputFrequency  
10pFLoad  
30pFLoad  
50  
0
133  
100  
60  
MHz  
Duty Cycle = t2 ÷ t1  
RiseTime  
Measured at 1.4V, FOUT = 66.66MHz  
Measured between 0.8V and 2V  
Measured between 0.8V and 2V  
Alloutputsequallyloaded  
%
t3  
t4  
t5  
t6  
t7  
tJ  
2.5  
2.5  
250  
350  
700  
175  
ns  
ns  
ps  
ps  
ps  
ps  
FallTime  
OutputtoOutputSkew  
Delay, REF Rising Edge to CLKOUT Rising Edge MeasuredatVDD/2  
Device-to-Device Skew  
Cycle-to-Cycle Jitter  
Measured at VDD/2 on the CLKOUT pins of devices  
0
Measuredat66.66MHz,loadedoutputs  
50  
tLOCK  
PLLLockTime  
Stable power supply, valid clock presented on REF pin  
1
ms  
NOTES:  
1. REF Input has a threshold voltage of VDD/2.  
2. All parameters specified with loaded outputs.  
3
IDT2305B  
3.3VZERODELAYCLOCKBUFFER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
SWITCHINGCHARACTERISTICS(2305B-1H)-COMMERCIAL(1,2)  
Symbol  
Parameter  
OutputFrequency  
Conditions  
Min.  
10  
Typ.  
Max.  
133  
Unit  
t1  
10pFLoad  
30pFLoad  
MHz  
10  
100  
Duty Cycle = t2 ÷ t1  
Duty Cycle = t2 ÷ t1  
RiseTime  
Measured at 1.4V, FOUT = 66.66MHz  
Measured at 1.4V, FOUT <50MHz  
Measured between 0.8V and 2V  
Measured between 0.8V and 2V  
Alloutputsequallyloaded  
40  
45  
1
50  
50  
0
60  
55  
%
%
t3  
1.5  
1.5  
250  
350  
700  
ns  
t4  
FallTime  
ns  
t5  
OutputtoOutputSkew  
ps  
t6  
t7  
Delay, REF Rising Edge to CLKOUT Rising Edge MeasuredatVDD/2  
ps  
Device-to-Device Skew  
OutputSlewRate  
Cycle-to-Cycle Jitter  
PLLLockTime  
Measured at VDD/2 on the CLKOUT pins of devices  
0
ps  
t8  
Measured between 0.8V and 2V using Test Circuit #2  
Measuredat66.66MHz,loadedoutputs  
V/ns  
ps  
tJ  
175  
1
tLOCK  
Stable power supply, valid clock presented on REF pin  
ms  
NOTES:  
1. REF Input has a threshold voltage of VDD/2.  
2. All parameters specified with loaded outputs.  
OPERATINGCONDITIONS-INDUSTRIAL  
Symbol  
Parameter  
Min.  
3
Max.  
Unit  
VDD  
SupplyVoltage  
3.6  
+85  
30  
V
TA  
OperatingTemperature(AmbientTemperature)  
Load Capacitance < 100MHz  
-40  
°C  
pF  
CL  
Load Capacitance 100MHz - 133MHz  
InputCapacitance  
10  
CIN  
7
pF  
DCELECTRICALCHARACTERISTICS-INDUSTRIAL  
Symbol  
VIL  
Parameter  
Conditions  
Min.  
2
Max.  
Unit  
V
InputLOWVoltageLevel  
Input HIGH Voltage Level  
InputLOWCurrent  
Input HIGH Current  
OutputLOWVoltage  
0.8  
VIH  
V
IIL  
VIN = 0V  
50  
µA  
µA  
V
IIH  
VIN = VDD  
100  
0.4  
VOL  
StandardDrive  
High Drive  
IOL = 8mA  
IOL = 12mA (-1H)  
IOH = -8mA  
VOH  
Output HIGH Voltage  
StandardDrive  
High Drive  
2.4  
V
IOH = -12mA (-1H)  
IDD_PD  
IDD  
Power Down Current  
SupplyCurrent  
REF = 0MHz  
25  
35  
µA  
mA  
UnloadedOutputsat 66.66MHz  
4
IDT2305B  
3.3VZERODELAYCLOCKBUFFER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
SWITCHINGCHARACTERISTICS(2305B-1)-INDUSTRIAL(1,2)  
Symbol  
Parameter  
OutputFrequency  
Conditions  
Min.  
10  
10  
40  
Typ.  
50  
0
Max.  
133  
100  
60  
Unit  
t1  
10pFLoad  
30pFLoad  
MHz  
Duty Cycle = t2 ÷ t1  
RiseTime  
Measured at 1.4V, FOUT = 66.66MHz  
Measured between 0.8V and 2V  
Measured between 0.8V and 2V  
Alloutputsequallyloaded  
%
t3  
t4  
t5  
t6  
t7  
tJ  
2.5  
ns  
ns  
ps  
ps  
ps  
ps  
FallTime  
2.5  
OutputtoOutputSkew  
250  
350  
700  
175  
Delay, REF Rising Edge to CLKOUT Rising Edge MeasuredatVDD/2  
Device-to-Device Skew  
Cycle-to-Cycle Jitter  
Measured at VDD/2 on the CLKOUT pins of devices  
0
Measuredat66.66MHz,loadedoutputs  
50  
tLOCK  
PLLLockTime  
Stable power supply, valid clock presented on REF pin  
1
ms  
NOTES:  
1. REF Input has a threshold voltage of VDD/2.  
2. All parameters specified with loaded outputs.  
SWITCHINGCHARACTERISTICS(2305B-1H)-INDUSTRIAL(1,2)  
Symbol  
Parameter  
OutputFrequency  
Conditions  
Min.  
10  
Typ.  
Max.  
133  
Unit  
t1  
10pFLoad  
30pFLoad  
MHz  
10  
100  
Duty Cycle = t2 ÷ t1  
Duty Cycle = t2 ÷ t1  
RiseTime  
Measured at 1.4V, FOUT = 66.66MHz  
Measured at 1.4V, FOUT <50MHz  
Measured between 0.8V and 2V  
Measured between 0.8V and 2V  
Alloutputsequallyloaded  
40  
45  
1
50  
50  
0
60  
55  
%
%
t3  
1.5  
1.5  
250  
350  
700  
ns  
t4  
FallTime  
ns  
t5  
OutputtoOutputSkew  
ps  
t6  
t7  
Delay, REF Rising Edge to CLKOUT Rising Edge MeasuredatVDD/2  
ps  
Device-to-Device Skew  
OutputSlewRate  
Cycle-to-Cycle Jitter  
PLLLockTime  
Measured at VDD/2 on the CLKOUT pins of devices  
0
ps  
t8  
Measured between 0.8V and 2V using Test Circuit #2  
Measuredat66.66MHz,loadedoutputs  
V/ns  
ps  
tJ  
175  
1
tLOCK  
Stable power supply, valid clock presented on REF pin  
ms  
NOTES:  
1. REF Input has a threshold voltage of VDD/2.  
2. All parameters specified with loaded outputs.  
5
IDT2305B  
3.3VZERODELAYCLOCKBUFFER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
ZERO DELAY AND SKEW CONTROL  
All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative  
loading can affect and adjust the input/output delay. The Output Load Difference diagram illustrates the PLL's relative loading with respect to the other  
outputs that can adjust the Input-Output (I/O) Delay.  
For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive  
load equaltothatontheotheroutputsinordertoobtaintruezeroI/ODelay. IfI/ODelayadjustmentsareneeded, usetheOutputLoadDifferencediagram  
to calculate loading differences between the CLKOUT pin and other outputs. For zero output-to-output skew, all outputs must be loaded equally.  
REF TO CLKA/CLKB RELAY vs. OUTPUT LOAD DIFFERENCE BETWEEN CLKOUT PIN AND CLKA/CLKB PINS  
OUTPUT LOAD DIFFERENCE BETWEEN CLKOUT PIN AND CLKA/CLKB PINS (pF)  
6
IDT2305B  
3.3VZERODELAYCLOCKBUFFER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
SWITCHINGWAVEFORMS  
1.4V  
t1  
Output  
t2  
1.4V  
1.4V  
1.4V  
1.4V  
Output  
t5  
Output to Output Skew  
Duty Cycle Timing  
3.3V  
0V  
VDD/2  
2V  
0.8V  
t4  
0.8V  
t3  
2V  
REF  
Output  
VDD/2  
Output  
t6  
Input to Output Propagation Delay  
All Outputs Rise/Fall Time  
CLKOUT  
Device 1  
VDD/2  
CLKOUT  
Device 2  
VDD/2  
t7  
Device to Device Skew  
TESTCIRCUITS  
VDD  
VDD  
1K  
CLKOUT  
CLKOUT  
10pF  
0.1 F  
0.1 F  
0.1 F  
OUTPUTS  
OUTPUTS  
CLOAD  
1K  
VDD  
VDD  
0.1 F  
GND  
GND  
GND  
GND  
Test Circuit 2 (t8, Output Slew Rate On -1H Devices)  
Test Circuit 1 (all Parameters Except t8)  
7
IDT2305B  
3.3VZERODELAYCLOCKBUFFER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
TYPICAL DUTY CYCLE(1) AND IDD TRENDS(2) FOR IDT2305B-1  
Duty Cycle vs VDD  
Duty Cycle vs VDD  
(for 30pf loads over frequency - 3.3V, 25C)  
(for 10pF loads over frequency - 3.3V, 25C)  
60  
58  
56  
60  
58  
56  
54  
52  
54  
52  
33MHz  
33MHz  
50  
48  
46  
44  
50  
48  
46  
44  
66MHz  
100MHz  
66MHz  
100MHz  
133MHz  
42  
40  
42  
40  
3
3.4  
3
3.4  
3.1  
3.3  
3.5  
3.6  
3.1  
3.3  
3.5  
3.6  
3.2  
3.2  
VDD (V)  
VDD (V)  
Duty Cycle vs Frequency  
(for 30pf loads over temperature - 3.3V)  
Duty Cycle vs Frequency  
(for 10pF loads over temperature - 3.3V)  
60  
58  
56  
60  
58  
56  
54  
52  
54  
52  
-40C  
-40C  
0C  
25C  
70C  
85C  
50  
48  
46  
44  
0C  
50  
48  
46  
44  
25C  
70C  
85C  
42  
40  
42  
40  
20  
40  
80  
100  
120  
140  
60  
20  
40  
80  
100  
120  
140  
60  
Frequency (MHz)  
Frequency (MHz)  
IDD vs Number of Loaded Outputs  
(for 30pf loads over frequency - 3.3V, 25C)  
IDD vs Number of Loaded Outputs  
(for 10pF loads over frequency - 3.3V, 25C)  
140  
120  
140  
120  
100  
80  
100  
80  
33MHz  
66MHz  
100MHz  
33MHz  
66MHz  
100MHz  
60  
60  
40  
20  
0
40  
20  
0
0
2
4
8
0
2
6
4
8
6
Number of Loaded Outputs  
Number of Loaded Outputs  
NOTES:  
1. Duty Cycle is taken from typical chip measured at 1.4V.  
2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = Number of outputs; C = Capacitance load per output (F);  
V = Supply Voltage (V); f = Frequency (Hz))  
8
IDT2305B  
3.3VZERODELAYCLOCKBUFFER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
TYPICAL DUTY CYCLE(1) AND IDD TRENDS(2) FOR IDT2305B-1H  
Duty Cycle vs VDD  
Duty Cycle vs VDD  
(for 30pf loads over frequency - 3.3V, 25C)  
(for 10pF loads over frequency - 3.3V, 25C)  
60  
58  
56  
60  
58  
56  
54  
52  
54  
52  
33MHz  
66MHz  
100MHz  
33MHz  
66MHz  
100MHz  
133MHz  
50  
48  
46  
44  
50  
48  
46  
44  
42  
40  
42  
40  
3
3.4  
3
3.4  
3.1  
3.3  
3.5  
3.6  
3.1  
3.3  
3.5  
3.6  
3.2  
3.2  
VDD (V)  
VDD (V)  
Duty Cycle vs Frequency  
(for 30pf loads over temperature - 3.3V)  
Duty Cycle vs Frequency  
(for 10pF loads over temperature - 3.3V)  
60  
58  
56  
60  
58  
56  
54  
52  
54  
52  
-40C  
0C  
25C  
70C  
85C  
-40C  
0C  
25C  
70C  
85C  
50  
48  
46  
44  
50  
48  
46  
44  
42  
40  
42  
40  
20  
40  
80  
100  
120  
140  
60  
20  
40  
80  
100  
120  
140  
60  
Frequency (MHz)  
Frequency (MHz)  
IDD vs Number of Loaded Outputs  
(for 30pf loads over frequency - 3.3V, 25C)  
IDD vs Number of Loaded Outputs  
(for 10pF loads over frequency - 3.3V, 25C)  
160  
140  
160  
140  
120  
120  
100  
80  
100  
80  
33MHz  
66MHz  
100MHz  
33MHz  
66MHz  
100MHz  
60  
60  
40  
20  
0
40  
20  
0
0
2
0
2
4
8
6
4
8
6
Number of Loaded Outputs  
Number of Loaded Outputs  
NOTES:  
1. Duty Cycle is taken from typical chip measured at 1.4V.  
2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = Number of outputs; C = Capacitance load per output (F); V = Supply Voltage (V);  
f = Frequency (Hz))  
9
IDT2305B  
3.3VZERODELAYCLOCKBUFFER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
ORDERINGINFORMATION  
XXXXX  
XX  
X
Package Process  
Device Type  
o
o
Commercial (0 C to +70 C)  
Blank  
I
o
o
Industrial (-40 C to +85 C)  
DC  
DCG  
PGG  
Small Outline  
SOIC - Green  
TSSOP - Green  
Zero Delay Clock Buffer  
High Drive Output  
2305B-1  
2305B-1H  
*NOTE: EOL for non-green parts to occur on 5/13/10 per  
PDNU-09-01  
Ordering Code  
PackageType  
OperatingRange  
2305B-1DC*  
8-Pin SOIC  
8-Pin SOIC  
8-Pin SOIC  
8-Pin SOIC  
8-Pin SOIC  
8-Pin SOIC  
8-Pin TSSOP  
8-Pin TSSOP  
Commercial  
Commercial  
Commercial  
Commercial  
Industrial  
2305B-1DCG  
2305B-1HDC*  
2305B-1HDCG  
2305B-1HDCGI  
2305B-1HDCI*  
2305B-1PGG  
2305B-1PGGI  
Industrial  
Commercial  
Industrial  
CORPORATE HEADQUARTERS  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
for SALES:  
for Tech Support:  
clockhelp@idt.com  
800-345-7015 or 408-284-8200  
fax: 408-284-2775  
www.idt.com  
10  
配单直通车
2305B-1DC产品参数
型号:2305B-1DC
是否Rohs认证: 不符合
生命周期:Obsolete
IHS 制造商:INTEGRATED DEVICE TECHNOLOGY INC
零件包装代码:SOIC
包装说明:SOIC-8
针数:8
Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01
风险等级:5.63
Is Samacsys:N
系列:2305
输入调节:STANDARD
JESD-30 代码:R-PDSO-G8
JESD-609代码:e0
长度:4.9 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1
功能数量:1
反相输出次数:
端子数量:8
实输出次数:4
最高工作温度:70 °C
最低工作温度:
输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns
座面最大高度:1.72 mm
最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V
表面贴装:YES
温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
宽度:3.9 mm
最小 fmax:133 MHz
Base Number Matches:1
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