24C02供应商报价哪里找芯片批发报价原理和应用中文资料-中国IC网-芯三七

24C01SC/02SC

2

1K/2K 5.0V I C Serial EEPROMs for Smart Cards

FEATURES

DIE LAYOUT

• ISO Standard 7816 pad locations

• Low power CMOS technology

VSS

- 1 mA active current typical

VCC

SCL

- 10 µA standby current typical at 5.5V

• Organized as a single block of 128 bytes (128 x 8)

or 256 bytes (256 x 8)

• Two-wire serial interface bus, I²C compatible

• 100 kHz and 400 kHz compatibility

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 8 bytes

• 2 ms typical write cycle time for page-write

• ESD protection > 4 kV

SDA

DC

BLOCK DIAGRAM

• 1,000,000 E/W cycles guaranteed

• Data retention > 200 years

HV GENERATOR

• Available for extended temperature ranges

- Commercial (C):

0°C to +70°C

I/O

CONTROL

LOGIC

MEMORY

CONTROL

LOGIC

EEPROM

ARRAY

XDEC

DESCRIPTION

PAGE LATCHES

The Microchip Technology Inc. 24C01SC and

24C02SC are 1K-bit and 2K-bit Electrically Erasable

PROMs with bondpad positions optimized for smart

card applications. The devices are organized as a sin-

gle block of 128 x 8-bit or 256 x 8-bit memory with a

two-wire serial interface. The 24C01SC and 24C02SC

also have page-write capability for up to 8 bytes of data.

SDA SCL

YDEC

VCC

VSS

SENSE AMP

R/W CONTROL

I²C is a trademark of Philips Corporation.

1996 Microchip Technology Inc.

Preliminary

DS21170A-page 1

This document was created with FrameMaker 4 0 4

24C01SC/02SC

TABLE 1-1:

Name

PAD FUNCTION TABLE

Function

1.0

ELECTRICAL CHARACTERISTICS

Maximum Ratings*

VCC........................................................................ 7.0V

All inputs and outputs w.r.t. VSS......-0.6V to VCC +1.0V

Storage temperature ...........................-65˚C to +150˚C

Ambient temp. with power applied.......-65˚C to +125˚C

ESD protection on all pads.....................................≥ 4 kV

VSS

SDA

SCL

VCC

DC

Ground

Serial Address/Data I/O

Serial Clock

+4.5V to 5.5V Power Supply

Don’t connect

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat-

ing only and functional operation of the device at those or any

other conditions above those indicated in the operational listings

of this speciﬁcation is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

TABLE 1-2:

DC CHARACTERISTICS

VCC = +4.5V to +5.5V

Commercial (C): Tamb = 0˚C to +70˚C

Parameter

Symbol

Min.

Max.

Units

Conditions

SCL and SDA pads:

High level input voltage

VIH

VIL

.7 VCC

—

.3 VCC

—

V

Low level input voltage

Hysteresis of Schmidt trigger inputs

Low level output voltage

VHYS

VOL

ILI

.05 VCC

—

V

(Note)

.40

10

V

IOL = 3.0 mA, VCC = 4.5V

VIN = .1V to 5.5V

Input leakage current (SCL)

Output leakage current (SDA)

Pin capacitance (all inputs/outputs)

-10

µA

pF

ILO

-10

10

VOUT = .1V to 5.5V

CIN,

—

10

VCC = 5.0V (Note 1)

COUT

Tamb = 25˚C, FCLK = 1 MHz

Operating current

ICC Write

ICC Read

ICCS

—

3

1

mA

µA

VCC = 5.5V

Vcc = 5.5V, SCL = 400 KHz

VCC = 5.5V, SDA = SCL = VCC

Standby current

100

Note:

This parameter is periodically sampled and not 100% tested.

FIGURE 1-1: BUS TIMING START/STOP

VHYS

SCL

THD:STA

TSU:STA

TSU:STO

SDA

START

STOP

DS21170A-page 2

Preliminary

1996 Microchip Technology Inc.

24C01SC/02SC

TABLE 1-3:

AC CHARACTERISTICS

Parameter

Symbol

Min.

Max.

Units

Remarks

Clock frequency

FCLK

THIGH

TLOW

TR

—

600

1300

—

400

—

kHz

ns

Clock high time

Clock low time

—

ns

SDA and SCL rise time

SDA and SCL fall time

START condition hold time

300

—

ns

(Note 1)

TF

—

ns

THD:STA

600

ns

After this period the ﬁrst clock

pulse is generated

START condition setup time

TSU:STA

600

—

ns

Only relevant for repeated

START condition

Data input hold time

Data input setup time

STOP condition setup time

Output valid from clock

Bus free time

THD:DAT

TSU:DAT

TSU:STO

TAA

0

—

ns

(Note 2)

100

600

—

900

—

(Note 2)

TBUF

1300

Time the bus must be free

before a new transmission can

start

Output fall time from VIH

minimum to VIL maximum

TOF

TSP

20 +0.1

CB

250

50

ns

(Note 1), CB ≤ 100 pF

Input ﬁlter spike suppression

(SDA and SCL pins)

—

(Note 3)

Write cycle time

Endurance

TWR

—

10

—

ms

Byte or Page mode

6

cycles 25°C, Vcc = 5V, Block Mode

10

(Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undeﬁned region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined TSP and VHYS speciﬁcations are due to new Schmitt trigger inputs which provide improved

noise spike suppression. This eliminates the need for a TI speciﬁcation for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a speciﬁc appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

FIGURE 1-2: BUS TIMING DATA

TR

TF

THIGH

TLOW

SCL

TSU:STA

THD:DAT

TSU:DAT

TSU:STO

THD:STA

SDA

IN

TSP

TAA

THD:STA

TAA

TBUF

SDA

OUT

1996 Microchip Technology Inc.

Preliminary

DS21170A-page 3

24C01SC/02SC

3.4

Data Valid (D)

2.0

FUNCTIONAL DESCRIPTION

The 24C01SC/02SC supports a bi-directional two-wire

bus and data transmission protocol. A device that

sends data onto the bus is deﬁned as transmitter, and

a device receiving data as receiver. The bus has to be

controlled by a master device which generates the

serial clock (SCL), controls the bus access, and gener-

ates the START and STOP conditions, while the

24C01SC/02SC works as slave. Both master and slave

can operate as transmitter or receiver, but the master

device determines which mode is activated.

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device

and is theoretically unlimited, although only the last 16

will be stored when doing a write operation. When an

overwrite does occur, it will replace data in a ﬁrst in ﬁrst

out fashion.

3.0

BUS CHARACTERISTICS

The following bus protocol has been deﬁned:

• Data transfer may be initiated only when the bus is

not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition.

3.5

Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this acknowledge bit.

Accordingly, the following bus conditions have been

deﬁned (Figure 3-1).

Note: The 24C01SC/02SC does not generate

any acknowledge bits if an internal pro-

gramming cycle is in progress.

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

The device that acknowledges has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by not generating an acknowledge bit on the last

byte that has been clocked out of the slave. In this case,

the slave must leave the data line HIGH to enable the

master to generate the STOP condition.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition. All

commands must be preceded by a START condition.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

(C)

(A)

SCL

SDA

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

DS21170A-page 4

Preliminary

1996 Microchip Technology Inc.

24C01SC/02SC

4.0

BUS CHARACTERISTICS

5.0

WRITE OPERATION

4.1

Slave Address

5.1

Byte Write

After generating a START condition, the bus master

transmits the slave address consisting of a 4-bit device

code (1010) for the 24C01SC/02SC, followed by three

don't care bits.

Following the start signal from the master, the device

code (4 bits), the don't care bits (3 bits), and the R/W

bit, which is a logic low, is placed onto the bus by the

master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will follow

after it has generated an acknowledge bit during the

ninth clock cycle. Therefore, the next byte transmitted

by the master is the word address and will be written

into the address pointer of the 24C01SC/02SC. After

receiving another acknowledge signal from the

24C01SC/02SC, the master device will transmit the

data word to be written into the addressed memory

location.The 24C01SC/02SC acknowledges again and

the master generates a stop condition.This initiates the

internal write cycle, and during this time the

24C01SC/02SC will not generate acknowledge signals

(Figure 5-1).

The eighth bit of slave address determines if the master

device wants to read or write to the 24C01SC/02SC

(Figure 4-1).

The 24C01SC/02SC monitors the bus for its corre-

sponding slave address all the time. It generates an

acknowledge bit if the slave address was true, and it is

not in a programming mode.

Control

Code

Chip

Select

Operation

R/W

Read

Write

1010

XXX

1

0

5.2

Page Write

FIGURE 4-1: CONTROL BYTE

ALLOCATION

The write control byte, word address, and the ﬁrst data

byte are transmitted to the 24C01SC/02SC in the same

way as in a byte write. But instead of generating a stop

condition, the master transmits up to eight data bytes to

the 24C01SC/02SC, which are temporarily stored in

the on-chip page buffer and will be written into the

memory after the master has transmitted a stop condi-

tion. After the receipt of each word, the three lower

order address pointer bits are internally incremented by

one. The higher order ﬁve bits of the word address

remains constant. If the master should transmit more

than eight words prior to generating the stop condition,

the address counter will roll over and the previously

received data will be overwritten. As with the byte write

operation, once the stop condition is received an inter-

nal write cycle will begin (Figure 5-2).

START

READ/WRITE

R/W

X

A

SLAVE ADDRESS

1

0

1

0

X

X = Don’t care

FIGURE 5-1: BYTE WRITE

S

BUS ACTIVITY

MASTER

T

A

R

T

S

T

O

P

CONTROL

BYTE

WORD

ADDRESS

DATA

SDA LINE

S

P

A

C

K

A

C

K

A

C

K

BUS ACTIVITY

FIGURE 5-2: PAGE WRITE

S

BUS ACTIVITY

MASTER

T

S

T

O

P

CONTROL

BYTE

WORD

ADDRESS (n)

A

R

T

DATA n

DATAn + 1

DATAn + 7

SDA LINE

S

P

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

BUS ACTIVITY

1996 Microchip Technology Inc.

Preliminary

DS21170A-page 5

24C01SC/02SC

6.0

ACKNOWLEDGE POLLING

7.0

READ OPERATION

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the master, the device ini-

tiates the internally timed write cycle. ACK polling can

be initiated immediately.This involves the master send-

ing a start condition followed by the control byte for a

write command (R/W = 0). If the device is still busy with

the write cycle, then NO ACK will be returned. If the

cycle is complete, then the device will return the ACK,

and the master can then proceed with the next read or

write command. See Figure 6-1 for ﬂow diagram.

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to one.There are three basic types

of read operations: current address read, random read,

and sequential read.

7.1

Current Address Read

The 24C01SC/02SC contains an address counter that

maintains the address of the last word accessed, inter-

nally incremented by one. Therefore, if the previous

access (either a read or write operation) was to address

n, the next current address read operation would

access data from address n + 1. Upon receipt of the

slave address with R/W bit set to one, the

24C01SC/02SC issues an acknowledge and transmits

the 8-bit data word. The master will not acknowledge

the transfer but does generate a stop condition and the

FIGURE 6-1: ACKNOWLEDGE POLLING

FLOW

Send

Write Command

24C01SC/02SC

(Figure 8-2).

discontinues

transmission

7.2

Random Read

Send Stop

Condition to

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, ﬁrst the word address must

be set.This is done by sending the word address to the

24C01SC/02SC as part of a write operation. After the

word address is sent, the master generates a start con-

dition following the acknowledge. This terminates the

write operation, but not before the internal address

pointer is set. Then, the master issues the control byte

again but with the R/W bit set to a one. The

24C01SC/02SC will then issue an acknowledge and

transmits the 8-bit data word. The master will not

acknowledge the transfer but does generate a stop con-

dition and the 24C01SC/02SC discontinues transmis-

sion (Figure 8-3).

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

NO

Acknowledge

(ACK = 0)?

7.3

Sequential Read

YES

Sequential reads are initiated in the same way as a ran-

dom read except that after the 24C01SC/02SC trans-

mits the ﬁrst data byte, the master issues an

acknowledge as opposed to a stop condition in a ran-

dom read. This directs the 24C01SC/02SC to transmit

the next sequentially addressed 8-bit word (Figure 9-1).

To provide sequential reads the 24C01SC/02SC con-

tains an internal address pointer which is incremented

by one at the completion of each operation. This

address pointer allows the entire memory contents to

be serially read during one operation.

DS21170A-page 6

Preliminary

1996 Microchip Technology Inc.

24C01SC/02SC

7.4

Noise Protection

The 24C01SC/02SC employs a VCC threshold detector

circuit which disables the internal erase/write logic if the

VCC is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and ﬁlter

circuits which suppress noise spikes to assure proper

device operation even on a noisy bus.

FIGURE 7-1: CURRENT ADDRESS READ

S

T

BUS ACTIVITY

CONTROL

S

T

O

P

A

R

T

MASTER

BYTE

DATA n

SDA LINE

S

P

A

C

K

N

O

BUS ACTIVITY

A

C

K

FIGURE 7-2: RANDOM READ

S

T

A

R

T

S

T

A

R

T

S

T

O

P

CONTROL

BYTE

WORD

ADDRESS (n)

CONTROL

BYTE

BUS ACTIVITY

MASTER

DATA n

S

P

S

SDA LINE

A

C

K

A

C

K

A

C

K

N

O

BUS ACTIVITY

A

C

K

FIGURE 7-3: SEQUENTIAL READ

S

T

O

P

A

C

K

A

C

K

A

C

K

CONTROL

BYTE

BUS ACTIVITY

MASTER

SDA LINE

P

A

C

K

N

O

BUS ACTIVITY

DATA n

DATA n + 1

DATA n + 2

DATA n + X

A

C

K

1996 Microchip Technology Inc.

Preliminary

DS21170A-page 7

24C01SC/02SC

8.0

PAD DESCRIPTIONS

9.0

DIE CHARACTERISTICS

Figure 9-1 shows the die layout of the 24C01SC/02SC,

including bondpad positions. Table 9-1 shows the

actual coordinates of the bondpad midpoints with

respect to the center of the die.

8.1

SDA Serial Address/Data Input/Output

This is a bi-directional pad used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pull-up

resistor to VCC (typical 10KΩ for 100 kHz, 1KΩ for 400

kHz).

FIGURE 9-1: DIE LAYOUT

DIP

VSS

For normal data transfer SDA is allowed to change only

during SCL low. Changes during SCL high are reserved

for indicating the START and STOP conditions.

VCC

8.2

SCL Serial Clock

SDA

This input is used to synchronize the data transfer from

and to the device.

DC

SCL

8.3

DC Don’t Connect

TABLE 9-1:

Pad Name

BONDPAD COORDINATES

This pad is used for test purposes and should not be

bonded out. It will be pulled to VSS through an internal

resistor.

Pad Midpoint,

X dir.

Pad Midpoint,

Y dir.

VSS

SDA

SCL

VCC

-495.000

-605.875

479.875

605.875

749.130

-271.875

-746.625

-261.375

Note 1: Dimensions are in microns.

2: Center of die is at the 0,0 point.

DS21170A-page 8

Preliminary

1996 Microchip Technology Inc.

24C01SC/02SC

NOTES:

1996 Microchip Technology Inc.

Preliminary

DS21170A-page 9

24C01SC/02SC

NOTES:

DS21170A-page 10

Preliminary

1996 Microchip Technology Inc.

24C01SC/02SC

24C01SC/02SC Product Identiﬁcation System

To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed

sales ofﬁces.

24C01SC/02SC

—

/S XX

Die Thickness

Package:

Blank = 11 mils

08 = 8 mils

Other die thicknesses available, please

consult factory.

S = Die in Wafer Pak

W = Wafer

WF = Sawed Wafer on Frame

Temperature

Range:

Blank = 0°C to +70°C

2

Device:

24C01SC

24C02SC

1K 1 C ISO Smart Card die

2

2K 1 C ISO Smart Card die

1996 Microchip Technology Inc.

Preliminary

DS21170A-page 11

WORLDWIDE SALES & SERVICE

AMERICAS

AMERICAS (continued)

EUROPE

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Corporate Ofﬁce

Microchip Technology Inc.

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Tel: 602 786-7200 Fax: 602 786-7277

Technical Support: 602 786-7627

Web: http://www.microchip.com/

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5/10/96

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Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-

sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement

of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho-

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DS21170A-page 12

Preliminary

1996 Microchip Technology Inc.

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