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产品型号24C04WP的Datasheet PDF文件预览

February 2000  
NM24C04/05 – 4K-Bit Standard 2-Wire Bus  
Interface Serial EEPROM  
General Description  
Features  
The NM24C04/05 devices are 4096 bits of CMOS non-volatile  
electrically erasable memory. These devices conform to all speci-  
fications in the Standard IIC 2-wire protocol and are designed to  
minimize device pin count, and simplify PC board layout require-  
ments.  
I Extended operating voltage 2.7V – 5.5V  
I 400 KHz clock frequency (F) at 2.7V - 5.5V  
I 200µA active current typical  
10µA standby current typical  
1µA standby current typical (L)  
0.1µA standby current typical (LZ)  
Theupperhalf(upper2Kbit)ofthememoryoftheNM24C05canbe  
write protected by connecting the WP pin to VCC. This section of  
I IIC compatible interface  
memory then becomes unalterable unless WP is switched to VSS  
.
– Provides bi-directional data transfer protocol  
This communications protocol uses CLOCK (SCL) and DATA  
I/O (SDA) lines to synchronously clock data between the master  
(forexampleamicroprocessor)andtheslaveEEPROMdevice(s).  
The Standard IIC protocol allows for a maximum of 16K of  
EEPROM memory which is supported by the Fairchild family in  
2K, 4K, 8K, and 16K devices, allowing the user to configure the  
memory as the application requires with any combination of  
EEPROMs. In order to implement higher EEPROM memory  
densities on the IIC bus, the Extended IIC protocol must be used.  
(Refer to the NM24C32 or NM24C65 datasheets for more infor-  
mation.)  
I Schmitt trigger inputs  
I Sixteen byte page write mode  
– Minimizes total write time per byte  
I Self timed write cycle  
Typical write cycle time of 6ms  
I Hardware Write Protect for upper half (NM24C05 only)  
I Endurance: 1,000,000 data changes  
I Data retention greater than 40 years  
I Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP  
I Available in three temperature ranges  
- Commercial: 0° to +70°C  
Fairchild EEPROMs are designed and tested for applications requir-  
ing high endurance, high reliability and low power consumption.  
- Extended (E): -40° to +85C  
- Automotive (V): -40° to +125°C  
Block Diagram  
V
CC  
V
SS  
WP  
H.V. GENERATION  
TIMING &CONTROL  
START  
STOP  
SDA  
LOGIC  
CONTROL  
LOGIC  
SLAVE ADDRESS  
REGISTER &  
2
E
PROM  
COMPARATOR  
XDEC  
ARRAY  
SCL  
A2  
A1  
WORD  
ADDRESS  
COUNTER  
R/W  
YDEC  
CK  
D
OUT  
DATA REGISTER  
D
IN  
DS500070-1  
1
© 1998 Fairchild Semiconductor Corporation  
NM24C04/05 Rev. G  
www.fairchildsemi.com  
Connection Diagrams  
Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)  
NC  
A1  
A2  
1
2
3
4
8
7
6
5
V
CC  
NC  
SCL  
NM24C04  
V
SDA  
SS  
DS500070-2  
See Package Number N08E, M08A and MTC08  
Pin Names  
A1,A2  
Device Address Inputs  
Ground  
VSS  
SDA  
SCL  
NC  
Serial Data I/O  
Serial Clock Input  
No Connection  
Power Supply  
VCC  
Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)  
NC  
A1  
A2  
1
2
3
4
8
7
6
5
V
CC  
WP  
NM24C05  
SCL  
SDA  
V
SS  
DS500070-3  
See Package Number N08E, M08A and MTC08  
Pin Names  
A1,A2  
Device Address Inputs  
Ground  
VSS  
SDA  
SCL  
WP  
Serial Data I/O  
Serial Clock input  
Write Protect  
VCC  
Power Supply  
No Connection  
NC  
2
www.fairchildsemi.com  
NM24C04/05 Rev. G  
Ordering Information  
NM 24  
C
XX  
F
LZ  
E
XXX  
Letter Description  
Package  
N
8-pin DIP  
M8  
MT8  
8-pin SOIC  
8-pin TSSOP  
Temp. Range  
None  
0 to 70°C  
V
E
-40 to +125°C  
-40 to +85°C  
Voltage Operating Range  
Blank  
L
4.5V to 5.5V  
2.7V to 5.5V  
LZ  
2.7V to 5.5V and  
<1µA Standby Current  
SCL Clock Frequency  
Density  
Blank  
F
100KHz  
400KHz  
04  
05  
4K  
4K with Write Protect  
C
CMOS Technology  
IIC  
Interface  
24  
NM  
Fairchild Non-Volatile  
Memory  
3
www.fairchildsemi.com  
NM24C04/05 Rev. G  
Product Specifications  
Operating Conditions  
Ambient Operating Temperature  
Absolute Maximum Ratings  
Ambient Storage Temperature  
65°C to +150°C  
6.5V to 0.3V  
NM24C04/05  
NM24C04E/05E  
NM24C04V/05V  
0°C to +70°C  
-40°C to +85°C  
-40°C to +125°C  
All Input or Output Voltages  
with Respect to Ground  
Lead Temperature  
Positive Power Supply  
NM24C04/05  
(Soldering, 10 seconds)  
+300°C  
4.5V to 5.5V  
2.7V to 5.5V  
2.7V to 5.5V  
ESD Rating  
2000V min.  
NM24C04L/05L  
NM24C04LZ/05LZ  
DC Electrical Characteristics (2.7V to 5.5V)  
Symbol  
Parameter  
Test Conditions  
Limits  
Typ  
Units  
Max  
Min  
(Note 1)  
ICCA  
Active Power Supply Current fSCL = 400 KHz  
fSCL = 100 KHz  
0.2  
1.0  
mA  
ISB  
Standby Current  
VIN = GND VCC = 2.7V - 5.5V  
10  
1
0.1  
50  
10  
1
µA  
µA  
µA  
or VCC  
VCC = 2.7V - 5.5V (L)  
VCC = 2.7V - 4.5V (LZ)  
ILI  
ILO  
Input Leakage Current  
Output Leakage Current  
Input Low Voltage  
VIN = GND to VCC  
0.1  
0.1  
1
1
µA  
µA  
V
VOUT = GND to VCC  
VIL  
VIH  
VOL  
0.3  
VCC x 0.3  
VCC + 0.5  
0.4  
Input High Voltage  
VCC x 0.7  
V
Output Low Voltage  
IOL = 3 mA  
V
Capacitance TA = +25°C, f = 100/400 KHz, VCC = 5V (Note 2)  
Symbol  
CI/O  
Test  
Conditions  
VI/O = 0V  
Max Units  
Input/Output Capacitance (SDA)  
8
pF  
CIN  
Input Capacitance (A0, A1, A2, SCL)  
VIN = 0V  
6
pF  
Note 1: Typical values are TA = 25°C and nominal supply voltage of 5V for 4.5V-5.5V operation and at 3V for 2.7V-4.5V operation.  
Note 2: This parameter is periodically sampled and not 100% tested.  
4
www.fairchildsemi.com  
NM24C04/05 Rev. G  
AC Testing Input/Output Waveforms  
AC Test Conditions  
Input Pulse Levels  
VCC x 0.1 to VCC x 0.9  
10 ns  
0.9VCC  
0.7VCC  
0.3VCC  
Input Rise and Fall Times  
0.1VCC  
Input & Output Timing Levels VCC x 0.3 to VCC x 0.7  
Output Load 1 TTL Gate and CL = 100 pF  
DS500070-4  
Read and Write Cycle Limits (Standard and Low VCC Range 2.7V - 5.5V)  
Symbol  
Parameter  
100 KHz  
400 KHz  
Units  
Min  
Max  
Min  
Max  
fSCL  
TI  
SCL Clock Frequency  
100  
100  
3.5  
400  
KHz  
ns  
Noise Suppression Time Constant at  
SCL, SDA Inputs (Minimum VIN  
Pulse width)  
50  
tAA  
SCL Low to SDA Data Out Valid  
0.3  
4.7  
0.1  
1.3  
0.9  
µs  
µs  
tBUF  
Time the Bus Must Be Free before  
a New Transmission Can Start  
tHD:STA  
tLOW  
Start Condition Hold Time  
Clock Low Period  
4.0  
4.7  
4.0  
4.7  
0.6  
1.5  
0.6  
0.6  
µs  
µs  
µs  
µs  
tHIGH  
Clock High Period  
tSU:STA  
Start Condition Setup Time  
(for a Repeated Start Condition)  
tHD:DAT  
tSU:DAT  
tR  
Data in Hold Time  
20  
20  
ns  
ns  
µs  
ns  
µs  
ns  
ms  
Data in Setup Time  
250  
100  
SDA and SCL Rise Time  
SDA and SCL Fall Time  
Stop Condition Setup Time  
Data Out Hold Time  
1
0.3  
tF  
300  
300  
tSU:STO  
tDH  
4.7  
0.6  
50  
300  
tWR  
(Note 3)  
Write Cycle Time - NM24C04/05  
- NM24C04/05L, NM24C04/05LZ  
10  
15  
10  
15  
Note 3: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the  
NM24C04/05 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Refer  
"Write Cycle Timing" diagram.  
Bus Timing  
t
t
R
F
t
HIGH  
t
t
LOW  
LOW  
SCL  
t
SU:STO  
t
t
t
SU:DAT  
SU:STA  
HD:DAT  
t
HD:STA  
SDA  
IN  
t
BUF  
t
t
AA  
DH  
SDA  
OUT  
DS500070-5  
5
www.fairchildsemi.com  
NM24C04/05 Rev. G  
Write Cycle Timing  
SCL  
SDA  
8th BIT  
WORD n  
ACK  
t
WR  
STOP  
START  
CONDITION  
CONDITION  
Note:  
The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.  
DS500070-6  
Typical System Configuration  
V
V
CC  
CC  
SDA  
SCL  
Master  
Transmitter/  
Receiver  
Slave  
Transmitter/  
Receiver  
Master  
Transmitter/  
Receiver  
Master  
Transmitter  
Slave  
Receiver  
DS500070-7  
Note:  
Due to open drain configuration of SDA and SCL, a bus-level pull-up resistor is called for, (typical value = 4.7k)  
Example of 16K of Memory on 2-Wire Bus  
Note:  
The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices.  
The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state.  
It is recommended that the total line capacitance be less than 400pF  
V
V
CC  
CC  
SDA  
SCL  
V
V
V
V
CC  
CC  
CC  
CC  
NM24C02/03  
NM24C02/03  
NM24C04/05  
NM24C08/09  
A0 A1 A2  
V
A0 A1 A2  
V
A1 A2  
V
A2  
V
SS  
SS  
SS  
SS  
To To To  
To To To  
To To  
To  
V
V
V
V
V
V
V
V
V
SS SS SS  
CC SS SS  
CC SS  
CC  
DS500070-8  
Device  
Address Pins Present  
A1  
Memory Size # of Page  
Blocks  
A0  
Yes  
No  
A2  
Yes  
Yes  
Yes  
No  
NM24C02/03  
NM24C04/05  
NM24C08/09  
NM24C16/17  
Yes  
Yes  
No  
2048 Bits  
4096 Bits  
8192 Bits  
16,384 Bits  
1
2
4
8
No  
No  
No  
6
www.fairchildsemi.com  
NM24C04/05 Rev. G  
Acknowledge  
Background Information (IIC Bus)  
Acknowledge is an active LOW pulse on the SDA line driven by an  
addressed receiver to the addressing transmitter to indicate  
receipt of 8-bits of data. The receiver provides an ACK pulse for  
every 8-bits of data received. This handshake mechanism is done  
as follows: After transmitting 8-bits of data, the transmitter re-  
leases the SDA line and waits for the ACK pulse. The addressed  
receiver, if present, drives the ACK pulse on the SDA line during  
the 9th clock and releases the SDA line back (to the transmitter).  
Refer Figure 3.  
IIC bus allows synchronous bi-directional communication be-  
tween a TRANSMITTER and a RECEIVER using a Clock signal  
(SCL) and a Data signal (SDA). Additionally there are up to three  
Address signals (A2, A1 and A0) which collectively serve as "chip  
select signal" to a device (example EEPROM) on the IIC bus.  
All communication on the IIC bus must be started with a valid  
START condition (by a MASTER), followed by transmittal (by the  
MASTER) of byte(s) of information (Address/Data). For every byte  
ofinformationreceived, theaddressedRECEIVERprovidesavalid  
ACKNOWLEDGE pulse to further continue the communication  
unless the RECEIVER intends to discontinue the communication.  
Depending on the direction of transfer (Write or Read), the RE-  
CEIVER can be a SLAVE or the MASTER. A typical IIC communi-  
cation concludes with a STOP condition (by the MASTER).  
Array Address  
Array address is an 8-bit information containing the address of a  
memory location to be selected within a page block of the device.  
16K bit Addressing Limitation:  
Addressing an EEPROM memory location involves sending a  
command string with the following information:  
Standard IIC specification limits the maximum size of EEPROM  
memory on the bus to 16K bits. This limitation is due to the  
addressingprotocolimplementedwhichconsistsofthe8-bitSlave  
Address and an additional 8-bit field called Array Address. This  
Array Address selects 1 out of 256 locations (28=256). Since the  
data format of IIC specification is 8-bit wide, a total of 256 x 8 =  
2048 = 2K bit now becomes addressable by this 8-bit Array  
Address. This 2K bit is typically referred as a Page Block.  
Combining this 8-bit Array Address with the 3-bit Device/Page  
address (part of Slave Address) allows a maximum of 8 pages  
(23=8) of memory that can be addressed. Since each page is 2K  
bit in size, 8 x 2K bit = 16K bit is the maximum size of memory that  
is addressable on the Standard IIC bus. This 16Kb of memory can  
be in the form of a single 16Kb EEPROM device or multiple  
EEPROMs of varying density (in 2Kb multiples) to a maximum  
total of 16Kb. To address the needs of systems that require more  
than 16Kb on the IIC bus, a different specification called Ex-  
tended IIC Specificationis used. Please refer to NM24C32xx  
Datasheet for more information on Extended IIC Specification.  
[DEVICE TYPE][DEVICE/PAGE BLOCK SELECTION][R/W  
BIT]{acknowledge pulse}[ARRAY ADDRESS]  
Slave Address  
Slave Address is an 8-bit information consisting of a Device type  
field (4bits), Device/Page block selection field (3bits) and Read/  
Write bit (1bit).  
Slave Address Format  
Device Type  
Identifier  
Device/Page Block  
Selection  
1
0
1
0
A2  
A1  
A0 R/W (LSB)  
DS500070-9  
DEFINITIONS  
Device Type  
WORD  
PAGE  
8 bits (byte) of data  
IIC bus is designed to support a variety of devices such as RAMs,  
EPROMs etc., along with EEPROMS. Hence to properly identify  
various devices on the IIC bus, a 4-bit Device Typeidentifier  
stringisused. ForEEPROMS, this4-bitstringis1-0-1-0. EveryIIC  
device on the bus internally compares this 4-bit string to its own  
Device Typestring to ensure proper device selection.  
16 sequential byte locations  
starting at a 16-byte address  
boundary, that may be pro-  
grammed during a "page write"  
programming cycle  
PAGE BLOCK  
2048 (2K) bits organized into 16  
pages of addressable memory. (8  
bits) x (16 bytes) x (16 pages) =  
2048 bits  
Device/Page Block Selection  
Whenmultipledevicesofthesametype(e.g.multipleEEPROMS)  
are present on the IIC bus, then the A2, A1 and A0 address  
information bits are also used as part of the Slave Address. Every  
IICdeviceonthebusinternallycomparesthis3-bitstringtoitsown  
physical configuration (A2, A1 and A0 pins) to ensure proper  
device selection. This comparison is in addition to the Device  
Typecomparison. In addition to selecting an EEPROM, these 3  
bits are also used to select a page blockwithin the selected  
EEPROM. Each page block is 2Kbit (256Bytes) in size. Depend-  
ing on the density, an EEPROM can contain from a minimum of 1  
to a maximum of 8 page blocks (in multiples of 2) and selection of  
a page block within a device is by using A2, A1 and A0 bits.  
MASTER  
Any IIC device CONTROLLING the  
transfer of data (such as a  
microprocessor)  
SLAVE  
Device being controlled  
(EEPROMs are always considered  
Slaves)  
TRANSMITTER  
RECEIVER  
Device currently SENDING data on  
the bus (may be either a Master or  
Slave).  
Read/Write Bit  
Device currently RECEIVING data  
on the bus (Master or Slave)  
Last bit of the Slave Address indicates if the intended access is  
Read or Write. If the bit is "1," then the access is Read, whereas  
if the bit is "0," then the access is Write.  
7
www.fairchildsemi.com  
NM24C04/05 Rev. G  
Pin Descriptions  
Device Operation  
The NM24C04/05 supports a bi-directional bus oriented protocol.  
The protocol defines any device that sends data onto the bus as  
a transmitter and the receiving device as the receiver. The device  
controlling the transfer is the master and the device that is  
controlled is the slave. The master will always initiate data  
transfers and provide the clock for both transmit and receive  
operations. Therefore, the NM24C04/05 will be considered a  
slave in all applications.  
Serial Clock (SCL)  
The SCL input is used to clock all data into and out of the device.  
Serial Data (SDA)  
SDA is a bi-directional pin used to transfer data into and out of the  
device. It is an open drain output and may be wireORed with any  
number of open drain or open collector outputs.  
Write Protect (WP) (NM24C05 Only)  
Clock and Data Conventions  
If tied to V , PROGRAM operations onto the upper half (upper  
CC  
Data states on the SDA line can change only during SCL LOW.  
SDA state changes during SCL HIGH are reserved for indicating  
start and stop conditions. Refer to Figure 1 and Figure 2 on next  
page.  
2Kbit) of the memory will not be executed. READ operations are  
possible. If tied to V , normal operation is enabled, READ/  
SS  
WRITE over the entire memory is possible.  
Start Condition  
Thisfeatureallowstheusertoassigntheupperhalfofthememory  
as ROM which can be protected against accidental programming.  
When write is disabled, slave address and word address will be  
acknowledged but data will not be acknowledged.  
All commands are preceded by the start condition, which is a  
HIGHtoLOWtransitionofSDAwhenSCLisHIGH.TheNM24C04/  
05 continuously monitors the SDA and SCL lines for the start  
condition and will not respond to any command until this condition  
has been met.  
This pin has an internal pull-down circuit. However, on systems  
where write protection is not required it is recommended that this  
pin is tied to VSS  
.
Stop Condition  
Device Selection Inputs A2, A1 and A0 (as  
appropriate)  
All communications are terminated by a stop condition, which is a  
LOW to HIGH transition of SDA when SCL is HIGH. The stop  
condition is also used by the NM24C04/05 to place the device in  
the standby power mode, except when a Write operation is being  
executed, in which case a second stop condition is required after  
These inputs collectively serve as chip selectsignal to an  
EEPROM when multiple EEPROMs are present on the same IIC  
bus. Hence these inputs, if present, should be connected to VCC  
orVSS inauniquemannertoallowproperselectionofanEEPROM  
amongst multiple EEPROMs. During a typical addressing se-  
quence, every EEPROM on the IIC bus compares the configura-  
tion of these inputs to the respective 3 bit Device/Page block  
selectioninformation (part of slave address) to determine a valid  
selection. For e.g. if the 3 bit Device/Page block selectionis 1-  
0-1, then the EEPROM whose Device Selection inputs(A2, A1  
and A0) are connected to VCC-VSS-VCC respectively, is selected.  
tWR period, to place the device in standby mode.  
Depending on the density, only appropriate number of Device  
Selection inputsare provided on an EEPROM. For every Device  
selection inputthat is not present on the device, the correspond-  
ing bit in the Device/Page block selectionfield is used to select  
a Page Blockwithin the device instead of the device itself.  
Following table illustrates the above:  
EEPROM  
Density  
2k bit  
Number of  
Page Blocks  
Device Selection Inputs  
Provided  
Address Bits  
Selecting Page Block  
None  
1
2
4
8
A0  
A1  
A1  
A2  
A2  
A2  
4k bit  
A0  
8k bit  
A0 and A1  
16k bit  
A0, A1 and A2  
Note that even when just one EEPROM present on the IIC bus,  
these pins should be tied to VCC or VSS to ensure proper termina-  
tion.  
8
www.fairchildsemi.com  
NM24C04/05 Rev. G  
Data Validity (Figure 1)  
SCL  
SDA  
DATA STABLE  
DATA  
CHANGE  
DS500070-10  
Start and Stop Definition (Figure 2)  
SCL  
SDA  
START  
STOP  
CONDITION  
CONDITION  
DS500070-11  
Acknowledge Response from Receiver (Figure 3)  
SCL FROM  
MASTER  
1
8
9
DATA OUTPUT  
FROM  
TRANSMITTER  
t
DH  
t
AA  
DATA OUTPUT  
FROM  
RECEIVER  
START  
CONDITION  
ACKNOWLEDGE  
PULSE  
DS500070-12  
9
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NM24C04/05 Rev. G  
Refer the following table for Slave Addresses string details:  
Acknowledge  
The NM24C04/05 device will always respond with an acknowl-  
edge after recognition of a start condition and its slave address. If  
both the device and a write operation have been selected, the  
NM24C04/05 will respond with an acknowledge after the receipt  
of each subsequent eight bit byte.  
Device A0 A1 A2 Page  
Page Block  
Blocks Addresses  
NM24C04/05  
P
A
A
2
0, 1  
A: Refers to a hardware configured Device Address pin.  
P: Refers to an internal PAGE BLOCK.  
In the read mode the NM24C04/05 slave will transmit eight bits of  
data, release the SDA line and monitor the line for an acknowl-  
edge. If an acknowledge is detected, NM24C04/05 will continue  
to transmit data. If an acknowledge is not detected,NM24C04/05  
will terminate further data transmissions and await the stop  
condition to return to the standby power mode.  
All IIC EEPROMs use an internal protocol that defines a PAGE  
BLOCK size of 2K bits (for Word addresses 0x00 through 0xFF).  
Therefore, address bits A0, A1, or A2 (if designated 'P') are used  
to access a PAGE BLOCK in conjunction with the Word address  
used to access any individual data byte.  
Device Addressing  
The last bit of the slave address defines whether a write or read  
condition is requested by the master. A '1' indicates that a read  
operation is to be executed, and a '0' initiates the write mode.  
Following a start condition the master must output the address of  
the slave it is accessing. The most significant four bits of the slave  
address are those of the device type identifier. This is fixed as  
1010 for all EEPROM devices.  
A simple review: After the NM24C04/05 recognizes the start  
condition, the devices interfaced to the IIC bus wait for a slave  
address to be transmitted over the SDA line. If the transmitted  
slave address matches an address of one of the devices, the  
designated slave pulls the line LOW with an acknowledge signal  
and awaits further transmissions.  
Device Type  
Identifier  
Device  
Address  
1
0
1
0
A2  
A1  
A0 R/W (LSB)  
Page  
NM24C04/05  
Block Address  
10  
www.fairchildsemi.com  
NM24C04/05 Rev. G  
Write Operations  
Page Write is initiated in the same manner as the Byte Write  
operation; but instead of terminating the cycle after transmitting  
the first data byte, the master can further transmit up to 15 more  
bytes. After the receipt of each byte, NM24C04/05 will respond  
withanacknowledgepulse,incrementtheinternaladdresscounter  
to the next address and is ready to accept the next data. If the  
master should transmit more than sixteen bytes prior to generat-  
ing the STOP condition, the address counter will roll overand  
previously written data will be overwritten. As with the Byte Write  
operation, all inputs are disabled until completion of the internal  
write cycle. Refer to Figure 5 for the address, acknowledge and  
data transfer sequence.  
BYTE WRITE  
For a write operation a second address field is required which is  
awordaddressthatiscomprisedofeightbitsandprovidesaccess  
to any one of the 256 bytes in the selected page of memory. Upon  
receipt of the byte address the NM24C04/05 responds with an  
acknowledge and waits for the next eight bits of data, again,  
responding with an acknowledge. The master then terminates the  
transferbygeneratingastopcondition,atwhichtimetheNM24C04/  
05beginstheinternalwritecycletothenonvolatilememory. While  
the internal write cycle is in progress the NM24C04/05 inputs are  
disabled, and the device will not respond to any requests from the  
master for the duration of tWR. Refer to Figure 4 for the address,  
acknowledge and data transfer sequence.  
Acknowledge Polling  
Once the stop condition is issued to indicate the end of the hosts  
write operation the NM24C04/05 initiates the internal write cycle.  
ACKpollingcanbeinitiatedimmediately. Thisinvolvesissuingthe  
start condition followed by the slave address for a write operation.  
If the NM24C04/05 is still busy with the write operation no ACK will  
bereturned.IftheNM24C04/05hascompletedthewriteoperation  
an ACK will be returned and the host can then proceed with the  
next read or write operation.  
PAGE WRITE  
To minimize write cycle time, NM24C04/05 offer Page Write  
feature, by which, up to a maximum of 16 contiguous bytes  
locations can be programmed all at once (instead of 16 individual  
byte writes). To facilitate this feature, the memory array is orga-  
nized in terms of Pages.A Page consists of 16 contiguous byte  
locations starting at every 16-Byte address boundary (for ex-  
ample, starting at array address 0x00, 0x10, 0x20 etc.). Page  
Write operation limits access to byte locations within a page. In  
other words a single Page Write operation will not cross over to  
locationsonanotherpagebutwillrollovertothebeginningofthe  
page whenever end of Page is reached and additional locations  
are a continued to be accessed. A Page Write operation can be  
initiated to begin at any location within a page (starting address of  
the Page Write operation need not be the starting address of a  
Page).  
Write Protection (NM24C05 Only)  
Programmingoftheupperhalf(upper2Kbit)ofthememorywillnot  
take place if the WP pin of the NM24C05 is connected to V . The  
CC  
NM24C05 will respond to slave and byte addresses; but if the  
memory accessed is write protected by the WP pin, the NM24C05  
will not generate an acknowledge after the first byte of data has  
beenreceived,andthustheprogramcyclewillnotbestartedwhen  
the stop condition is asserted.  
Byte Write (Figure 4)  
S
T
A
R
T
S
T
O
P
SLAVE  
ADDRESS  
WORD  
ADDRESS  
Bus Activity:  
Master  
DATA  
SDA Line  
A
C
K
A
C
K
A
C
K
Bus Activity:  
EEPROM  
DS500070-13  
Page Write (Figure 5)  
S
T
A
R
T
S
T
O
P
SLAVE  
ADDRESS  
Bus Activity:  
Master  
WORD ADDRESS (n)  
DATA n  
DATA n + 1  
DATA n + 15  
SDA Line  
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity:  
EEPROM  
DS500070-14  
11  
www.fairchildsemi.com  
NM24C04/05 Rev. G  
master immediately issues another start condition and the slave  
address with the R/W bit set to one. This will be followed by an  
acknowledgefromtheNM24C04/05andthenbytheeightbitbyte.  
The master will not acknowledge the transfer but does generate  
the stop condition, and therefore the NM24C04/05 discontinues  
transmission. Refer to Figure 7 for the address, acknowledge and  
data transfer sequence.  
Read Operations  
Read operations are initiated in the same manner as write  
operations, with the exception that the R/W bit of the slave  
address is set to a one. There are three basic read operations:  
current address read, random read, and sequential read.  
Current Address Read  
Sequential Read  
Internally the NM24C04/05 contains an address counter that  
maintains the address of the last byte accessed, incremented by  
one. Therefore, if the last access (either a read or write) was to  
address n, the next read operation would access data from  
address n + 1. Upon receipt of the slave address with R/W set to  
one, the NM24C04/05 issues an acknowledge and transmits the  
eight bit byte. The master will not acknowledge the transfer but  
does generate a stop condition, and therefore the NM24C04/05  
discontinues transmission. Refer to Figure 6 for the sequence of  
address, acknowledge and data transfer.  
Sequential reads can be initiated as either a current address read  
or random access read. The first word is transmitted in the same  
manner as the other read modes; however, the master now  
responds with an acknowledge, indicating it requires additional  
data. The NM24C04/05 continues to output data for each ac-  
knowledge received. The read operation is terminated by the  
master not responding with an acknowledge or by generating a  
stop condition.  
The data output is sequential, with the data from address n  
followed by the data from n + 1. The address counter for read  
operations increments all word address bits, allowing the entire  
memory contents to be serially read during one operation. After  
the entire memory has been read, the counter "rolls over" to the  
beginning of the memory. NM24C04/05 continues to output data  
for each acknowledge received. Refer to Figure 8 for the address,  
acknowledge, and data transfer sequence.  
Random Read  
Randomreadoperationsallowthemastertoaccessanymemory  
location in a random manner. Prior to issuing the slave address  
with the R/W bit set to one, the master must first perform a  
dummywrite operation. The master issues the start condition,  
slave address with the R/W bit set to zero and then the byte  
address it is to read. After the byte address acknowledge, the  
Current Address Read (Figure 6)  
S
T
S
T
O
P
SLAVE  
ADDRESS  
Bus Activity:  
Master  
A
R
T
1 0 1  
0
1
SDA Line  
A
C
K
NO  
A
C
Bus Activity:  
EEPROM  
DATA  
K
DS500070-15  
Random Read (Figure 7)  
S
T
A
R
T
S
S
T
O
P
T
A
R
T
SLAVE  
ADDRESS  
WORD  
ADDRESS  
SLAVE  
ADDRESS  
Bus Activity:  
Master  
SDA Line  
A
C
K
A
C
K
A
C
K
NO  
DATA n  
A
C
K
Bus Activity:  
EEPROM  
DS500070-16  
Sequential Read (Figure 8)  
S
T
O
P
A
C
K
A
C
K
A
C
K
Bus Activity:  
Slave  
Master  
Address  
SDA Line  
A
C
K
NO  
DATA n +1  
DATA n +1  
DATA n + 2  
DATA n + x  
A
C
K
Bus Activity:  
EEPROM  
DS500070-17  
12  
www.fairchildsemi.com  
NM24C04/05 Rev. G  
Physical Dimensions inches (millimeters) unless otherwise noted  
0.189 - 0.197  
(4.800 - 5.004)  
8
7
6
3
5
4
0.228 - 0.244  
(5.791 - 6.198)  
1
2
Lead #1  
IDENT  
0.150 - 0.157  
(3.810 - 3.988)  
0.053 - 0.069  
(1.346 - 1.753)  
0.010 - 0.020  
(0.254 - 0.508)  
0.004 - 0.010  
(0.102 - 0.254)  
x 45°  
8° Max, Typ.  
All leads  
Seating  
Plane  
0.04  
0.0075 - 0.0098  
(0.190 - 0.249)  
Typ. All Leads  
(0.102)  
All lead tips  
0.014  
(0.356)  
0.016 - 0.050  
(0.406 - 1.270)  
Typ. All Leads  
0.050  
(1.270)  
Typ  
0.014 - 0.020  
(0.356 - 0.508)  
Typ.  
8-Pin Molded Small Outline Package (M8)  
Package Number M08A  
0.114 - 0.122  
(2.90 - 3.10)  
8
5
(7.72) Typ  
(4.16) Typ  
0.169 - 0.177  
(4.30 - 4.50)  
0.246 - 0.256  
(6.25 - 6.5)  
(1.78) Typ  
(0.42) Typ  
0.123 - 0.128  
(3.13 - 3.30)  
(0.65) Typ  
Land pattern recommendation  
1
4
Pin #1 IDENT  
0.0433  
Max  
(1.1)  
0.0035 - 0.0079  
See detail A  
0.002 - 0.006  
(0.05 - 0.15)  
0.0256 (0.65)  
Typ.  
Gage  
plane  
0.0075 - 0.0098  
(0.19 - 0.30)  
0°-8°  
DETAIL A  
Typ. Scale: 40X  
0.0075 - 0.0098  
(0.19 - 0.25)  
0.020 - 0.028  
(0.50 - 0.70)  
Seating  
plane  
Notes: Unless otherwise specified  
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93  
8-Pin Molded Thin Shrink Small Outline Package (MT8)  
Package Number MTC08  
13  
www.fairchildsemi.com  
NM24C04/05 Rev. G  
Physical Dimensions inches (millimeters) unless otherwise noted  
0.373 - 0.400  
(9.474 - 10.16)  
0.090  
(2.286)  
8
7
0.032 0.005  
(0.813 0.127)  
RAD  
8
7
6
3
5
4
0.092  
(2.337)  
DIA  
0.250 - 0.005  
(6.35 0.127)  
Pin #1  
IDENT  
+
Pin #1 IDENT  
1
Option 1  
1
2
Option 2  
0.280  
MIN  
0.040  
(1.016)  
Typ.  
(7.112)  
0.030  
0.145 - 0.200  
(3.683 - 5.080)  
0.039  
(0.991)  
MAX  
(0.762)  
0.300 - 0.320  
(7.62 - 8.128)  
20° 1°  
0.130 0.005  
(3.302 0.127)  
0.125 - 0.140  
95° 5°  
(3.175 - 3.556)  
0.065  
(1.651)  
0.125  
(3.175)  
DIA  
0.020  
90° 4°  
Typ  
0.009 - 0.015  
(0.229 - 0.381)  
(0.508)  
Min  
0.018 0.003  
(0.457 0.076)  
NOM  
+0.040  
-0.015  
0.325  
0.100 0.010  
+1.016  
-0.381  
8.255  
(2.540 0.254)  
0.045 0.015  
(1.143 0.381)  
0.060  
(1.524)  
0.050  
(1.270)  
Molded Dual-In-Line Package (N)  
Package Number N08E  
Life Support Policy  
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written  
approval of the President of Fairchild Semiconductor Corporation. As used herein:  
1. Life support devices or systems are devices or systems which,  
(a)areintendedforsurgicalimplantintothebody,or(b)support  
or sustain life, and whose failure to perform, when properly  
used in accordance with instructions for use provided in the  
labeling, can be reasonably expected to result in a significant  
injury to the user.  
2. A critical component is any component of a life support device  
or system whose failure to perform can be reasonably ex-  
pected to cause the failure of the life support device or system,  
or to affect its safety or effectiveness.  
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Fairchild Semiconductor  
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Fairchild Semiconductor  
Japan Ltd.  
Customer Response Center  
Tel. 1-888-522-5372  
Fax:  
Tel:  
Tel:  
Tel:  
Tel:  
+44 (0) 1793-856858  
8/F, Room 808, Empire Centre  
68 Mody Road, Tsimshatsui East  
Kowloon. Hong Kong  
Tel; +852-2722-8338  
Fax: +852-2722-8383  
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Deutsch  
English  
Français  
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Tokyo, 113-0034 Japan  
Tel: 81-3-3818-8840  
Fax: 81-3-3818-8841  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.  
14  
www.fairchildsemi.com  
NM24C04/05 Rev. G  
配单直通车
24C08B-E/P产品参数
型号:24C08B-E/P
是否Rohs认证: 不符合
生命周期:Obsolete
IHS 制造商:MICROCHIP TECHNOLOGY INC
零件包装代码:DIP
包装说明:DIP, DIP8,.3
针数:8
Reach Compliance Code:unknown
风险等级:5.48
Is Samacsys:N
其他特性:2-WIRE SERIAL INTERFACE; DATA RETENTION > 200 YEARS; 1000000 ERASE/WRITE CYCLES GUARANTEED
最大时钟频率 (fCLK):0.1 MHz
数据保留时间-最小值:200
耐久性:1000000 Write/Erase Cycles
I2C控制字节:1010XMMR
JESD-30 代码:R-PDIP-T8
JESD-609代码:e0
长度:9.46 mm
内存密度:8192 bit
内存集成电路类型:EEPROM
内存宽度:8
功能数量:1
端子数量:8
字数:1024 words
字数代码:1000
工作模式:SYNCHRONOUS
最高工作温度:125 °C
最低工作温度:-40 °C
组织:1KX8
输出特性:OPEN-DRAIN
封装主体材料:PLASTIC/EPOXY
封装代码:DIP
封装等效代码:DIP8,.3
封装形状:RECTANGULAR
封装形式:IN-LINE
并行/串行:SERIAL
峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V
认证状态:Not Qualified
座面最大高度:4.32 mm
串行总线类型:I2C
最大待机电流:0.0001 A
子类别:EEPROMs
最大压摆率:0.003 mA
最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V
表面贴装:NO
技术:CMOS
温度等级:AUTOMOTIVE
端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE
端子节距:2.54 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mm
最长写入周期时间 (tWC):10 ms
写保护:HARDWARE
Base Number Matches:1
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