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产品型号24C08的Datasheet PDF文件预览

ST24C08, ST25C08

ST24W08, ST25W08

8 Kbit Serial I C Bus EEPROM

with User-Defined Block Write Protection

1 MILLION ERASE/WRITE CYCLES with

40 YEARS DATA RETENTION

SINGLE SUPPLY VOLTAGE:

– 3V to 5.5V for ST24x08 versions

– 2.5V to 5.5V for ST25x08 versions

HARDWARE WRITE CONTROL VERSIONS:

ST24W08 and ST25W08

PROGRAMMABLE WRITE PROTECTION

TWO WIRE SERIAL INTERFACE, FULLY I²C

BUS COMPATIBLE

SO8 (M)

150mil Width

PSDIP8 (B)

0.25mm Frame

BYTE and MULTIBYTE WRITE (up to 8

BYTES)

PAGE WRITE (up to 16 BYTES)

BYTE, RANDOM and SEQUENTIAL READ

MODES

Figure 1. Logic Diagram

SELF TIMED PROGRAMMING CYCLE

AUTOMATIC ADDRESS INCREMENTING

ENHANCED ESD/LATCH UP

PERFORMANCES

DESCRIPTION

This specification covers a range of 8 Kbits I²C bus

EEPROM products, the ST24/25C08 and the

ST24/25W08. In the text, products are referred to

as ST24/25x08, where "x" is: "C" for Standard

version and "W" for Hardware Write Control ver-

sion.

PRE

SDA

ST24x08

ST25x08

SCL

MODE/WC*

Table 1. Signal Names

PRE

Write Protect Enable

Chip Enable Input

SDA

SCL

Serial Data Address Input/Output

Serial Clock

AI00860E

Multibyte/Page Write Mode

(C version)

MODE

V_CC

V_SS

Write Control (W version)

Supply Voltage

Ground

Note: WC signal is only available for ST24/25W08 products.

February 1999

1/16

ST24/25C08, ST24/25W08

Figure 2A. DIP Pin Connections

Figure 2B. SO Pin Connections

ST24x08

ST25x08

ST24x08

ST25x08

PRE

MODE/WC

SCL

SDA

AI00861E

AI01073E

Warning: NC = Not Connected.

Table 2. Absolute Maximum Ratings ⁽¹⁾

Symbol

T_A

Parameter

Value

Unit

°C

Ambient Operating Temperature

Storage Temperature

–40 to 125

–65 to 150

T_STG

°C

T_LEAD

Lead Temperature, Soldering

(SO8 package)

(PSDIP8 package)

40 sec

10 sec

215

260

°C

V_IO

Input or Output Voltages

Supply Voltage

–0.6 to 6.5

–0.3 to 6.5

4000

V_CC

Electrostatic Discharge Voltage (Human Body model) ⁽²⁾

Electrostatic Discharge Voltage (Machine model) ⁽³⁾

V_ESD

500

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other

relevant quality documents.

2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).

3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).

DESCRIPTION (cont’d)

tional data bus and serial clock. The memories

carry a built-in 4 bit, unique device identification

code (1010) corresponding to the I²C bus defini-

tion. This is used together with 1 chip enable input

(E) so that up to 2 x 8K devices may be attached

to the I²C bus and selected individually. The memo-

ries behave as a slave device in the I²C protocol

with all memory operations synchronized by the

serial clock. Read and write operations are initiated

by a STARTcondition generated by the bus master.

The START condition is followed by a stream of 7

bits (identification code 1010), plus one read/write

bit and terminated by an acknowledge bit.

The ST24/25x08 are 8 Kbit electrically erasable

programmable memories (EEPROM), organized

as 4 blocks of 256 x8 bits. They are manufactured

in STMicroelectronics’s Hi-Endurance Advanced

CMOS technology which guarantees an endur-

ance of one million erase/write cycles with a data

retention of 40 years.

Both Plastic Dual-in-Line and Plastic Small Outline

packages are available.

The memories are compatible with the I²C stand-

ard, two wire serial interface which uses a bi-direc-

2/16

ST24/25C08, ST24/25W08

Table 3. Device Select Code

Chip

Enable

Block

Device Code

Select

Bit

Device Select

Note: The MSB b7 is sent first.

Table 4. Operating Modes ⁽¹⁾

Mode

RW bit

MODE

Bytes

Initial Sequence

START, Device Select, RW = ’1’

Current Address Read

’1’

’0’

’1’

’0’

START, Device Select, RW = ’0’, Address,

reSTART, Device Select, RW = ’1’

Similar to Current or Random Mode

START, Device Select, RW = ’0’

Random Address Read

Sequential Read

Byte Write

1 to 1024

Multibyte Write ⁽²⁾

V_IH

V_IL

Page Write

Notes: 1. X = V_IHor V_IL

2. Multibyte Write not available in ST24/25W08 versions.

When writing data to the memory it responds to the

8 bits received by asserting an acknowledge bit

during the 9th bit time. When data is read by the

bus master, it acknowledges the receipt of the data

bytes in the same way. Data transfers are termi-

nated with a STOP condition.

with other open drain or open collector signals on

the bus. Aresistor must be connected fromthe SDA

bus line to V_CCto act as pull up (see Figure 3).

Chip Enable (E). This chip enable input is used to

set one least significant bit (b3) of the device select

byte code. This input may be driven dynamically or

tied to V_CCor V_SSto establish the device select

code.

Power On Reset: V_CClock out write protect. In

order to prevent data corruption and inadvertent

write operations during power up, a Power On

Reset (POR) circuit is implemented. Until the V_CC

voltage has reached the POR threshold value, the

internal reset is active, all operations are disabled

and the device will not respond to any command.

In the same way, when V_CCdrops down from the

operating voltage to below the POR threshold

value, all operations are disabled and the device

will not respond to any command. A stable V_CC

must be applied before applying any logic signal.

Protect Enable (PRE). The PRE input pin, in ad-

dition to the status of the Block Address Pointer bit

(b2, location 3FFh as in Figure 7), sets the PRE

write protection active.

Mode (MODE). The MODE input is available on pin

7 (see also WC feature) and may be driven dynami-

cally. It must be at V_ILor V_IHfor the Byte Write

mode, V_IHfor Multibyte Write mode or V_ILfor Page

Write mode. When unconnected, the MODE input

is internally read as a V_IH(Multibyte Write mode).

Write Control (WC). An hardware Write Control

(WC) feature is offered only for ST24W08 and

ST25W08 versions on pin 7. This feature is usefull

to protect the contents of the memory from any

erroneous erase/write cycle. The Write Control sig-

nal is used to enable (WC = V_IH) or disable (WC =

V_IL) the internal write protection. When uncon-

nected, the WC input is internally read as V_ILand

the memory area is not write protected.

SIGNAL DESCRIPTIONS

Serial Clock (SCL). The SCL input pin is used to

synchronize all data in and out of the memory. A

resistor can be connected from the SCL line to V_CC

to act as a pull up (see Figure 3).

Serial Data (SDA). The SDA pin is bi-directional

and is used to transfer data in or out of the memory.

It is an open drain output that may be wire-OR’ed

3/16

ST24/25C08, ST24/25W08

SIGNAL DESCRIPTIONS (cont’d)

Stop Condition. STOPis identified by a low to high

transition of the SDA line while the clock SCL is

stable in the high state. A STOP condition termi-

nates communication between the ST24/25x08

and the bus master. A STOP condition at the end

of a Read command, after and only after a No

Acknowledge, forces the standby state. A STOP

condition at the end of a Write command triggers

the internal EEPROM write cycle.

The devices with this Write Control feature no

longer support the Multibyte Write mode of opera-

tion, however all other write modes are fully sup-

ported.

Refer to the AN404 Application Note for more de-

tailed information about Write Control feature.

Acknowledge Bit (ACK). An acknowledge signal

is used to indicate a successfull data transfer. The

bus transmitter, either master or slave, will release

the SDAbus after sending 8 bits of data. During the

9th clock pulse period the receiver pulls the SDA

bus low to acknowledge the receipt of the 8 bits of

data.

Data Input. During data input the ST24/25x08

sample the SDA bus signal on the rising edge of

the clock SCL. Note that for correct device opera-

tion the SDA signal must be stable during the clock

low to high transition and the data must change

ONLY when the SCL line is low.

DEVICE OPERATION

I²C Bus Background

The ST24/25x08 support the I²C protocol. This

protocol defines any device that sends data onto

the bus as a transmitter and any device that reads

the data as a receiver. The device that controls the

data transfer is known as the master and the other

as the slave. The master will always initiate a data

transfer and will provide the serial clock for syn-

chronisation. The ST24/25x08 are always slave

devices in all communications.

Memory Addressing. To start communication be-

tween the bus master and the slave ST24/25x08,

the master must initiate a STARTcondition. Follow-

ing this, the master sends onto the SDA bus line 8

bits (MSB first) corresponding to the device select

code (7 bits) and a READ or WRITE bit.

Start Condition. START is identified by a high to

low transition of the SDA line while the clock SCL

is stable in the high state. A START condition must

precede any command for data transfer. Except

during a programming cycle, the ST24/25x08 con-

tinuously monitor the SDA and SCL signals for a

START condition and will not respond unless one

is given.

Figure 3. Maximum R_LValue versus Bus Capacitance (C_BUS) for an I²C Bus

SDA

BUS

MASTER

SCL

BUS

= 5V

100

200

(pF)

300

400

AI01100

BUS

4/16

ST24/25C08, ST24/25W08

Table 5. Input Parameters ⁽¹⁾(T_A= 25 °C, f = 100 kHz )

Symbol

C_IN

Parameter

Input Capacitance (SDA)

Test Condition

Min

Max

Unit

C_IN

Input Capacitance (other pins)

Z_WCL

Z_WCH

WC Input Impedance (ST24/25W08)

_IN≤ 0.3 V_CC

_IN≥ 0.7 V_CC

kΩ

500

Low-pass filter input time constant

(SDA and SCL)

t_LP

100

Note: 1. Sampled only, not 100% tested.

Table 6. DC Characteristics

(T_A= 0 to 70°C, –20 to 85°C or –40 to 85°C; V_CC= 3V to 5.5V or 2.5V to 5.5V)

Symbol

Parameter

Test Condition

Min

Max

Unit

I_LI

Input Leakage Current

0V ≤ V_IN≤ V_CC

±2

µA

0V ≤ V_OUT≤ V_CC

I_LO

Output Leakage Current

±2

µA

SDA in Hi-Z

_CC= 5V, f_C= 100kHz

Supply Current (ST24 series)

Supply Current (ST25 series)

µA

(Rise/Fall time < 10ns)

I_CC

V_CC= 2.5V, f_C= 100kHz

_IN= V_SSor V_CC

_CC= 5V

100

Supply Current (Standby)

(ST24 series)

I_CC1

_IN= V_SSor V_CC

300

µA

V_CC= 5V, f_C= 100kHz

V_IN= V_SSor V_CC

V_CC= 2.5V

Supply Current (Standby)

(ST25 series)

I_CC2

_IN= V_SSor V_CC

V_CC= 2.5V, f_C= 100kHz

V_IL

V_IH

Input Low Voltage (SCL, SDA)

Input High Voltage (SCL, SDA)

–0.3

0.3 V_CC

V_CC+ 1

0.7 V_CC

Input Low Voltage

V_IL

V_IH

–0.3

0.5

(E, PRE, MODE, WC)

Input High Voltage

(E, PRE, MODE, WC)

_CC– 0.5

V_CC+ 1

Output Low Voltage (ST24 series)

Output Low Voltage (ST25 series)

I_OL= 3mA, V_CC= 5V

_OL= 2.1mA, V_CC= 2.5V

0.4

V_OL

5/16

ST24/25C08, ST24/25W08

Table 7. AC Characteristics

(T_A= 0 to 70°C, –20 to 85°C or –40 to 85°C; V_CC= 3V to 5.5V or 2.5V to 5.5V)

Symbol

t_CH1CH2

t_CL1CL2

t_DH1DH2

t_DL1DL1

Alt

t_R

Parameter

Min

Max

Unit

µs

Clock Rise Time

Clock Fall Time

Input Rise Time

Input Fall Time

t_F

300

t_R

µs

t_F

300

(1)

t_CHDX

t_SU:STA

t_HIGH

t_HD:STA

t_HD:DAT

t_LOW

t_SU:DAT

t_SU:STO

t_BUF

t_AA

Clock High to Input Transition

Clock Pulse Width High

4.7

µs

t_CHCL

t_DLCL

t_CLDX

t_CLCH

t_DXCX

t_CHDH

t_DHDL

Input Low to Clock Low (START)

Clock Low to Input Transition

Clock Pulse Width Low

4.7

250

4.7

0.3

300

Input Transition to Clock Transition

Clock High to Input High (STOP)

Input High to Input Low (Bus Free)

Clock Low to Next Data Out Valid

Data Out Hold Time

µs

(2)

t_CLQV

3.5

t_CLQX

f_C

t_DH

f_SCL

t_WR

Clock Frequency

100

kHz

(3)

t_W

Write Time

Notes: 1. For a reSTART condition, or following a write cycle.

2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP

conditions.

3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) the

maximum programming time is doubled to 20ms.

Table 8. AC Measurement Conditions

DEVICE OPERATION (cont’d)

The 4 most significant bits of the device select code

are the device type identifier, corresponding to the

I²C bus definition. For these memories the 4 bits

are fixed as 1010b. The following bit identifies the

specific memory on the bus. It is matched to the

chip enable signal E. Thus up to 2 x 8K memories

can be connected on the same bus giving a mem-

ory capacity total of 16 Kbits. After a START condi-

tion any memory on the bus will identify the device

code and compare the following bit to its chip

enable input E.

Input Rise and Fall Times

Input Pulse Voltages

≤ 50ns

0.2V_CCto 0.8V_CC

Input and Output Timing Ref.

Voltages

0.3V_CCto 0.7V_CC

Figure 4. AC Testing Input Output Waveforms

The 6th and 7th bits sent, select the block number

(one block = 256 bytes). The 8th bit sent is the read

or write bit (RW), this bit is set to ’1’ for read and ’0’

for write operations. If a match is found, the corre-

sponding memory will acknowledge the identifica-

tion on the SDA bus during the 9th bit time.

0.8V

0.7V

0.3V

0.2V

AI00825

6/16

ST24/25C08, ST24/25W08

Figure 5. AC Waveforms

tCHCL

tDLCL

tCLCH

SCL

tDXCX

tCHDH

SDA IN

tCHDX

tCLDX

SDA

tDHDL

START

CONDITION

SDA

STOP &

BUS FREE

INPUT CHANGE

SCL

tCLQV

tCLQX

DATA VALID

SDA OUT

DATA OUTPUT

SCL

SDA IN

tCHDH

tCHDX

STOP

WRITE CYCLE

START

CONDITION

AI00795B

Write Operations

receipt of the byte address the device again re-

sponds with an acknowledge.

For the ST24/25W08 versions, any write command

with WC = 1 will not modify the memory content.

Byte Write. In the Byte Write mode the master

sends one data byte, which is acknowledged by the

memory. The master then terminates the transfer

by generating a STOP condition. The Write mode

is independant of the state of the MODE pin which

could be left floating if only this mode was to be

used. However it is not a recommended operating

mode, as this pin has to be connected to either V_IH

or V_IL, to minimize the standby current.

The Multibyte Write mode (only available on the

ST24/25C08 versions) is selected when the MODE

pin is at V_IHand the Page Write mode when MODE

pin is at V_IL. The MODE pin may be driven dynami-

cally with CMOS input levels.

Following a START condition the master sends a

device select code with the RW bit reset to ’0’. The

memory acknowledges this and waits for a byte

address. The byte address of 8 bits provides ac-

cess to one block of 256 bytes of the memory. After

7/16

ST24/25C08, ST24/25W08

Figure 6. I²C Bus Protocol

SCL

SDA

START

SDA

STOP

CONDITION

INPUT CHANGE

CONDITION

SCL

SDA

ACK

MSB

START

CONDITION

SCL

SDA

MSB

ACK

STOP

CONDITION

AI00792

Multibyte Write. For the Multibyte Write mode, the

MODE pin must be at V_IH. The Multibyte Write

mode can be started from any address in the

memory. The master sends from one up to 8 bytes

of data, which are each acknowledged by the mem-

ory. The transfer is terminated by the master gen-

erating a STOP condition. The duration of the write

cycle is t_W= 10ms maximum except when bytes

are accessed on 2 rows (that is have different

values for the 5 most significant address bits A7-

A3), the programming time is then doubled to a

maximum of 20ms. Writing more than 8 bytes in the

Multibyte Write mode may modify data bytes in an

adjacent row (one row is 16 bytes long). However,

the Multibyte Write can properly write up to 16

consecutive bytes only if the first address of these

16 bytes is the first address of the row, the 15

following bytes being written in the 15 following

bytes of this same row.

Page Write. For the Page Write mode the MODE

pin must be at V_IL. The Page Write mode allows up

to 16 bytes to be written in a single write cycle,

provided that they are all located in the same ’row’

in the memory: that is the 4 most significant mem-

ory address bits (A7-A4) are the same inside one

block. The master sends from one up to 16 bytes

8/16

ST24/25C08, ST24/25W08

Figure 7. Memory Protection

of data, which are each acknowledged by the mem-

ory. After each byte is transfered, the internal byte

address counter (4 least significant bits only) is

incremented. The transfer is terminated by the

master generating a STOPcondition. Care must be

taken to avoid address counter ’roll-over’ which

could result in data being overwritten. Note that, for

any write mode, the generation by the master of the

STOP condition starts the internal memory pro-

gram cycle. All inputs are disabled until the comple-

tion of this cycle and the memory will not respond

to any request.

Minimizing System Delays by Polling On ACK.

During the internal write cycle, the memory discon-

nects itself from the bus in order to copy the data

from the internal latches to the memory cells. The

maximum value of the write time (t_W) is given in the

AC Characteristics table, since the typical time is

shorter, the time seen by the system may be re-

duced by an ACK polling sequence issued by the

master.

Page

pointer

Protect Flag

Enable = 0

Disable = 1

3FFh

300h

Block 3

Block 0

AI01121B

Figure 8. Write Cycle Polling using ACK

WRITE Cycle

in Progress

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

First byte of instruction

with RW = 0 already

decoded by ST24xxx

YES

Operation is

Addressing the

Memory

YES

Send

Byte Address

ReSTART

STOP

Proceed

WRITE Operation

Proceed

Random Address

READ Operation

AI01099B

9/16

ST24/25C08, ST24/25W08

Figure 9. Write Modes Sequence (ST24/25C08)

ACK

BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

R/W

ACK

BYTE ADDR

MULTIBYTE

AND

DEV SEL

DATA IN 1

DATA IN 2

PAGE WRITE

R/W

ACK

DATA IN N

AI00793

DEVICE OPERATION (cont’d)

boundary in steps of 16 bytes. The sequence to use

the Write Protected feature is:

The sequence is as follows:

– Initial condition: a Write is in progress (see Fig-

ure 8).

– write the data to be protected into the top of

the memory, up to, but not including, location

3FFh;

– Step 1: the Master issues a START condition

followed by a Device Select byte (1st byte of

the new instruction).

– set the protection by writing the correct bottom

boundary address in the Address pointer (4

MSBs of location 3FFh) with the bit b2 (Protect

flag) set to ’0’.

– Step 2: if the memory is busy with the internal

write cycle, no ACK will be returned and the

master goes back to Step 1. If the memory

has terminated the internal write cycle, it will

respond with an ACK, indicating that the mem-

ory is ready to receive the second part of the

next instruction (the first byte of this instruc-

tion was already sent during Step 1).

Note that for a correct fonctionality of the memory,

all the 4 LSBs of the Block Address Pointer must

also be programmed at ’0’. The area will now be

protected when the PRE input pin is taken High.

While the PRE input pin is read at ’0’ by the mem-

ory, the location 3FFh can be used as a normal

EEPROM byte.

Write Protection. Data in the upper block of 256

bytes of the memory may be write protected. The

memory is write protected between a boundary

address and the top of memory (address 3FFh)

when the PRE input pin is taken high and when the

Protect Flag (bit b2 in location 3FFh) is set to ’0’.

The boundary address is user defined by writing it

in the Block Address Pointer. The Block Address

Pointer is an 8 bit EEPROM register located at the

address 3FFh. It is composed by 4 MSBs Address

Pointer, which defines the bottom boundary ad-

dress, and 4 LSBs which must be programmed at

’0’. This Address Pointer can therefore address a

Caution: Special attention must be used when

using the protect mode together with the Multibyte

Write mode (MODE input pin High). If the Multibyte

Write starts at the location right below the first byte

of the Write Protected area, then the instruction will

write over the first 7 bytes of the Write Protected

area. The area protected is therefore smaller than

the content defined in the location 3FFh, by7 bytes.

This does not apply to the Page Write mode as the

address counter ’roll-over’ and thus cannot go

above the 16 bytes lower boundary of the protected

area.

10/16

ST24/25C08, ST24/25W08

Figure 10. Write Modes Sequence with Write Control = 1 (ST24/25W08)

ACK

NO ACK

DATA IN

BYTE WRITE

DEV SEL

BYTE ADDR

R/W

ACK

NO ACK

DATA IN 1 DATA IN 2

PAGE WRITE

DEV SEL

BYTE ADDR

R/W

WC (cont'd)

NO ACK

PAGE WRITE

(cont'd)

DATA IN N

AI01161B

Read Operations

Random Address Read. A dummy write is per-

formed to load the address intothe addresscounter

(see Figure 11). This is followed by another START

condition from the master and the byte address is

repeated with the RW bit set to ’1’. The memory

acknowledges this and outputs the byte ad-

dressed. The master have to NOT acknowledge

the byte output, but terminates the transfer with a

STOP condition.

Sequential Read. This mode can be initiated with

either a Current Address Read or a Random Ad-

dress Read. However, in this case the master

DOES acknowledge the data byte output and the

memory continues to output the next byte in se-

quence. To terminate the stream of bytes, the

Read operations are independentof the state of the

MODE pin. On delivery, the memory content is set

at all "1’s" (or FFh).

Current Address Read. The memory has an inter-

nal byte address counter. Each time a byte is read,

this counter is incremented. For the Current Ad-

dress Read mode, following a START condition,

the master sends a memory address with the RW

bit set to ’1’. The memory acknowledges this and

outputs the byte addressed by the internal byte

address counter. This counter is then incremented.

The master does NOT acknowledge the byte out-

put, but terminates the transfer with a STOP con-

dition.

11/16

ST24/25C08, ST24/25W08

DEVICE OPERATION (cont’d)

counter will ’roll-over’ and the memory will continue

to output data.

master must NOT acknowledge the last byte out-

put, but MUST generate a STOP condition. The

output data is from consecutive byte addresses,

with the internal byte address counter automat-

ically incremented after each byte output. After a

count of the last memory address, the address

Acknowledge in Read Mode. In all read modes

the ST24/25x08 wait foran acknowledgeduring the

9th bit time. If the master does not pull the SDAline

low during this time, the ST24/25x08 terminate the

data transfer and switches to a standby state.

Figure 11. Read Modes Sequence

ACK

NO ACK

CURRENT

ADDRESS

READ

DEV SEL

DATA OUT

R/W

ACK

NO ACK

DATA OUT

RANDOM

ADDRESS

READ

DEV SEL *

BYTE ADDR

DEV SEL *

R/W

ACK

NO ACK

SEQUENTIAL

CURRENT

READ

DEV SEL

DATA OUT 1

DATA OUT N

R/W

ACK

SEQUENTIAL

RANDOM

READ

DEV SEL *

BYTE ADDR

DEV SEL * DATA OUT 1

R/W

ACK

NO ACK

DATA OUT N

AI00794C

Note:

* The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.

12/16

ST24/25C08, ST24/25W08

ORDERING INFORMATION SCHEME

Example:

ST24C08

Operating Voltage

Range

ST24C08

ST24W08

ST25C08

ST25W08

3V to 5.5V

Standard

Hardware Write Control

2.5V to 5.5V Standard

2.5V to 5.5V Hardware Write Control

Package

Temperature Range

Option

PSDIP8

0.25mm Frame

0 to 70 °C

TR Tape & Reel

Packing

5 ⁽¹⁾–20 to 85 °C

SO8 150mil Width

–40 to 85 °C

–40 to 125 °C

Notes: 1. Temperature range on special request only.

Devices are shipped from the factory with the memory content set at all "1’s" (FFh).

For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect

of this device, please contact the STMicroelectronics Sales Office nearest to you. to you.

13/16

ST24/25C08, ST24/25W08

PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame

Min

3.90

0.49

3.30

0.36

1.15

0.20

9.20

–

inches

Min

Symb

Typ

Max

5.90

–

Typ

Max

0.232

–

0.154

0.019

0.130

0.014

0.045

0.008

0.362

–

5.30

0.56

1.65

0.36

9.90

–

0.209

0.022

0.065

0.014

0.390

–

7.62

2.54

0.300

0.100

6.00

–

6.70

–

0.236

–

0.264

–

7.80

–

0.307

–

10.00

3.80

0.394

0.150

3.00

0.118

PSDIP-a

Drawing is not to scale

14/16

ST24/25C08, ST24/25W08

SO8 - 8 lead Plastic Small Outline, 150 mils body width

Min

1.35

0.10

0.33

0.19

4.80

3.80

–

inches

Min

Symb

Typ

Max

1.75

0.25

0.51

0.25

5.00

4.00

–

Typ

Max

0.069

0.010

0.020

0.010

0.197

0.157

–

0.053

0.004

0.013

0.007

0.189

0.150

–

1.27

0.050

5.80

0.25

0.40

0°

6.20

0.50

0.90

8°

0.228

0.010

0.016

0°

0.244

0.020

0.035

8°

0.10

0.004

h x 45˚

SO-a

Drawing is not to scale

15/16

ST24/25C08, ST24/25W08

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to

change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

All other names are the property of their respective owners

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -

Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

http://www.st.com

16/16

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24C08B-E/P产品参数

型号:	24C08B-E/P
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	MICROCHIP TECHNOLOGY INC
零件包装代码：	DIP
包装说明：	DIP, DIP8,.3
针数：	8
Reach Compliance Code：	unknown
风险等级：	5.48
Is Samacsys：	N
其他特性：	2-WIRE SERIAL INTERFACE; DATA RETENTION > 200 YEARS; 1000000 ERASE/WRITE CYCLES GUARANTEED
最大时钟频率 (fCLK)：	0.1 MHz
数据保留时间-最小值：	200
耐久性：	1000000 Write/Erase Cycles
I2C控制字节：	1010XMMR
JESD-30 代码：	R-PDIP-T8
JESD-609代码：	e0
长度：	9.46 mm
内存密度：	8192 bit
内存集成电路类型：	EEPROM
内存宽度：	8
功能数量：	1
端子数量：	8
字数：	1024 words
字数代码：	1000
工作模式：	SYNCHRONOUS
最高工作温度：	125 °C
最低工作温度：	-40 °C
组织：	1KX8
输出特性：	OPEN-DRAIN
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装等效代码：	DIP8,.3
封装形状：	RECTANGULAR
封装形式：	IN-LINE
并行/串行：	SERIAL
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V
认证状态：	Not Qualified
座面最大高度：	4.32 mm
串行总线类型：	I2C
最大待机电流：	0.0001 A
子类别：	EEPROMs
最大压摆率：	0.003 mA
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	NO
技术：	CMOS
温度等级：	AUTOMOTIVE
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm
最长写入周期时间 (tWC)：	10 ms
写保护：	HARDWARE
Base Number Matches：	1

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