30521供应商报价哪里找芯片批发报价原理和应用中文资料-中国IC网-芯三七

PRELIMINARY

ICS83052I-01

Integrated

Circuit

Systems, Inc.

2-BIT, 2:1,

S

INGLE-ENDED

MULTIPLEXER

GENERAL DESCRIPTION

FEATURES

The ICS83052I-01 is a 2-bit, 2:1, Single-ended Mul- • 2-bit, 2:1 single-ended multiplexer

tiplexer and a member of the HiPerClockS™fam-

ICS

• Nominal output impedance: 15Ω (V_DDO= 3.3V)

• Maximum output frequency: 250MHz

• Propagation delay: 2.5ns (typical)

• Input skew: 45ps (typical)

HiPerClockS™

ily of High Performance Clock Solutions from ICS.

The ICS83052I-01 has two selectable single-ended

clock inputs and two single-ended clock outputs.

The output has a V_DDOpin which may be set at 3.3V, 2.5V, or

1.8V, making the device ideal for use in voltage translation ap-

plications. An output enable pin places the output in

a high impedance state which may be useful for testing or

debug. Possible applications include systems with up to two

transceivers which need to be independently set for different

rates. For example, a board may have two transceivers, each

of which need to be independently configured for 1 Gigabit

Ethernet or 1 Gigabit Fibre Channel rates. Another possible

application may require the ports to be independently set for

FEC (Forward Error Correction) or non-FEC rates.The device

operates up to 250MHz and is packaged in a 16 TSSOP.

• Part-to-part skew: TBD

• Additive phase jitter, RMS (12KHz - 20MHz):

0.07ps (typical)

• Operating supply modes:

V_DD/V_DDO

3.3V/3.3V

3.3V/2.5V

3.3V/1.8V

2.5V/2.5V

2.5V/1.8V

• -40°C to 85°C ambient operating temperature

BLOCK DIAGRAM

PIN ASSIGNMENT

Pulldown

SEL0

1

2

3

4

5

6

7

8

nc

V^DDO

nc

GND

Q1

SEL1

CLK1

V^DD

16

15

14

13

12

11

10

9

nc

V^DDO

nc

GND

Q0

SEL0

CLK0

OE

Pulldown

CLK0

CLK1

0

1

Q0

Pulldown

ICS83052I-01

0

1

16-LeadTSSOP

Q1

4.4mm x 3.0mm x 0.92mm package body

G Package

Top View

Pulldown

SEL1

OE

Pullup

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial

product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

83052AGI-01

www.icst.com/products/hiperclocks.html

REV. A NOVEMBER 24, 2004

1

PRELIMINARY

ICS83052I-01

Integrated

Circuit

Systems, Inc.

2-BIT, 2:1,

S

INGLE-ENDED

MULTIPLEXER

TABLE 1. PIN DESCRIPTIONS

Number

1, 3, 14, 16

2, 15

Name

nc

Type

Unused

Description

No connect.

V_DDO

Power

Output

Output supply pins.

Power supply ground.

4, 13

GND

Q1, Q0

5, 12

Single-ended clock output. LVCMOS/LVTTL interface levels.

Clock select inputs. See Control Input Function Table.

LVCMOS / LVTTL interface levels.

6, 11

SEL1, SEL0

Input

Pulldown

7, 10

8

CLK1, CLK0

V_DD

Input

Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.

Core supply pin.

Power

Output enable. When LOW, outputs are in HIGH impedance state.

Pullup

9

OE

Input

When HIGH, outputs are active. LVCMOS / LVTTL interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Units

pF

Symbol Parameter

Test Conditions

Minimum Typical Maximum

C_IN

Input Capacitance

Input Pullup Resistor

4

R_PULLUP

51

KΩ

R_PULLDOWNInput Pulldown Resistor

KΩ

Power Dissipation Capacitance

(per output)

C_PD

11

15

pF

R_OUT

Output Impedance

Ω

TABLE 3. CONTROL INPUT FUNCTION TABLE

Control Inputs

Outputs

SEL1

SEL0

Q1

Q0

0

1

0

1

0

1

CLK0

CLK1

CLK0

CLK1

CLK0

CLK1

83052AGI-01

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REV. A NOVEMBER 24, 2004

2

PRELIMINARY

ICS83052I-01

Integrated

Circuit

Systems, Inc.

2-BIT, 2:1,

S

INGLE-ENDED

MULTIPLEXER

ABSOLUTE MAXIMUM RATINGS

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device.These ratings are stress specifications only.Functional

operation of product at these conditions or any conditions be-

yond those listed in the DC Characteristics or AC Character-

istics is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

SupplyVoltage, V

4.6V

DD

Inputs, V

-0.5V to V_DD+ 0.5 V

-0.5V to V_DDO+ 0.5V

89°C/W (0 lfpm)

-65°C to 150°C

I

Outputs, V_O

PackageThermal Impedance, θ

JA

StorageTemperature, T

STG

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V_DD= 3.3V 5ꢀ, V_DDO= 3.3V 5ꢀ, OR 2.5V 5ꢀ, OR 1.8V 0.2V,

T^A= -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

V_DD

Core Supply Voltage

3.135

2.375

1.6

3.3

2.5

1.8

32

4

3.465

2.625

2.0

V

V_DDO

Output Supply Voltage

V

I_DD

Power Supply Current

Output Supply Current

mA

I_DDO

TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, V_DD= 2.5V 5ꢀ, V_DDO= 2.5V 5ꢀ, OR 1.8V 0.2V, TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

V_DD

Core Supply Voltage

2.375

1.6

2.5

1.8

30

4

2.625

2.0

V

V_DDO

Output Supply Voltage

V

I_DD

Power Supply Current

Output Supply Current

mA

I_DDO

83052AGI-01

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REV. A NOVEMBER 24, 2004

3

PRELIMINARY

ICS83052I-01

Integrated

Circuit

Systems, Inc.

2-BIT, 2:1,

S

INGLE-ENDED

MULTIPLEXER

TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C

Symbol Parameter Test Conditions

_DD= 3.3V 5ꢀ

Minimum Typical Maximum Units

V

2

V_DD+ 0.3

1.3

V

CLK0, CLK1

V_DD= 2.5V 5ꢀ

V_DD= 3.3V 5ꢀ

V_DD= 2.5V 5ꢀ

1.7

2

V_IH

Input High Voltage

OE, SEL0,

SEL1

1.7

-0.3

V

_DD= 3.3V 5ꢀ

CLK0, CLK1

V_DD= 2.5V 5ꢀ

V_DD= 3.3V 5ꢀ

V_DD= 2.5V 5ꢀ

0.7

V_IL

Input Low Voltage

1.3

OE, SEL0,

SEL1

0.7

CLK0, CLK1,

SEL0, SEL1

V

_DD= 3.3V or 2.5V 5ꢀ

150

5

µA

I_IH

Input High Current

Input Low Current

OE

V_DD= 3.3V or 2.5V 5ꢀ

CLK0, CLK1,

SEL0, SEL1

-5

I_IL

OE

V

_DD= 3.3V or 2.5V 5ꢀ

-150

2.6

µA

V

_DDO= 3.3V 5ꢀ; NOTE 1

V_OH

Output HighVoltage

Output Low Voltage

V_DDO= 2.5V 5ꢀ; NOTE 1

V_DDO= 1.8V 0.2V; NOTE 1

1.8

V

V_DD- 0.3

V

_DDO= 3.3V 5ꢀ; NOTE 1

0.5

V

V_OL

V_DDO= 2.5V 5ꢀ; NOTE 1

V_DDO= 1.8V 0.2V; NOTE 1

0.45

0.35

V

NOTE 1: Outputs terminated with 50Ω to V_DDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.

TABLE 5A. AC CHARACTERISTICS, V_DD= V_DDO= 3.3V 5ꢀ, TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

f_MAX

Output Frequency

250

MHz

Propagation Delay, Low to High;

NOTE 1

tp_LH

2.5

ns

Propagation Delay, High to Low;

NOTE 1

tp_HL

2.65

ns

tsk(i)

Input Skew; NOTE 5

45

ps

tsk(pp)

Part-to-Part Skew; NOTE 2, 5

TBD

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter section,

NOTE 4

Integration Range:

12KHz - 20MHz

tjit

0.07

ps

t_R/ t_F

odc

t_EN

Output Rise/Fall Time

20ꢀ to 80ꢀ

535

50

ps

ꢀ

Output Duty Cycle

Output Enable Time; NOTE 3

Output Disable Time; NOTE 3

5

ns

dB

t_DIS

MUX_ISOLMUX Isolation

@100MHz

45

NOTE 1A: Measured from V_DD/2 of the input to V_DDO/2 of the output.

NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and

with equal load conditions. Using the same type of input on each device, the output is measured at V_DDO/2.

NOTE 3: These parameters are guaranteed by characterization. Not tested in production.

NOTE 4: Driving only one input clock.

NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.

83052AGI-01

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REV. A NOVEMBER 24, 2004

4

PRELIMINARY

ICS83052I-01

Integrated

Circuit

Systems, Inc.

2-BIT, 2:1,

S

INGLE-ENDED

MULTIPLEXER

TABLE 5B. AC CHARACTERISTICS, V_DD= 3.3V 5ꢀ, V_DDO= 2.5V 5ꢀ, TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

f_MAX

Output Frequency

250

MHz

Propagation Delay, Low to High;

NOTE 1

Propagation Delay, High to Low;

NOTE 1

tp_LH

2.7

ns

tp_HL

ns

tsk(i)

Input Skew; NOTE 5

38

ps

tsk(pp)

Part-to-Part Skew; NOTE 2, 5

TBD

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter section,

NOTE 4

Integration Range:

12KHz - 20MHz

tjit

0.04

ps

t_R/ t_F

odc

t_EN

Output Rise/Fall Time

20ꢀ to 80ꢀ

550

50

ps

ꢀ

Output Duty Cycle

Output Enable Time; NOTE 3

Output Disable Time; NOTE 3

5

ns

dB

t_DIS

MUX_ISOLMUX Isolation

@100MHz

45

NOTE 1A: Measured from V_DD/2 of the input to V_DDO/2 of the output.

NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and

with equal load conditions. Using the same type of input on each device, the output is measured at V_DDO/2.

NOTE 3: These parameters are guaranteed by characterization. Not tested in production.

NOTE 4: Driving only one input clock.

NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.

TABLE 5C. AC CHARACTERISTICS, V_DD= 3.3V 5ꢀ, V_DDO= 1.8V 0.2V, TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

f_MAX

Output Frequency

250

MHz

Propagation Delay, Low to High;

NOTE 1

Propagation Delay, High to Low;

NOTE 1

tp_LH

3

ns

tp_HL

ns

tsk(i)

Input Skew; NOTE 5

38

ps

tsk(pp)

Part-to-Part Skew; NOTE 2, 5

TBD

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter section,

NOTE 4

Integration Range:

12KHz - 20MHz

tjit

0.05

ps

t_R/ t_F

odc

t_EN

Output Rise/Fall Time

20ꢀ to 80ꢀ

595

50

ps

ꢀ

Output Duty Cycle

Output Enable Time; NOTE 3

Output Disable Time; NOTE 3

5

ns

dB

t_DIS

MUX_ISOLMUX Isolation

@100MHz

45

NOTE 1A: Measured from V_DD/2 of the input to V_DDO/2 of the output.

NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and

with equal load conditions. Using the same type of input on each device, the output is measured at V_DDO/2.

NOTE 3: These parameters are guaranteed by characterization. Not tested in production.

NOTE 4: Driving only one input clock.

NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.

83052AGI-01

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REV. A NOVEMBER 24, 2004

5

PRELIMINARY

ICS83052I-01

Integrated

Circuit

Systems, Inc.

2-BIT, 2:1,

S

INGLE-ENDED

MULTIPLEXER

TABLE 5D. AC CHARACTERISTICS, V_DD= V_DDO= 2.5V 5ꢀ, TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

f_MAX

Output Frequency

250

MHz

Propagation Delay, Low to High;

NOTE 1

Propagation Delay, High to Low;

NOTE 1

tp_LH

2.7

2.9

ns

tp_HL

ns

tsk(i)

Input Skew; NOTE 5

45

ps

tsk(pp)

Part-to-Part Skew; NOTE 2, 5

TBD

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter section,

NOTE 4

Integration Range:

12KHz - 20MHz

tjit

0.10

ps

t_R/ t_F

odc

t_EN

Output Rise/Fall Time

20ꢀ to 80ꢀ

540

50

ps

ꢀ

Output Duty Cycle

Output Enable Time; NOTE 3

Output Disable Time; NOTE 3

5

ns

dB

t_DIS

MUX_ISOLMUX Isolation

@100MHz

45

NOTE 1A: Measured from V_DD/2 of the input to V_DDO/2 of the output.

NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and

with equal load conditions. Using the same type of input on each device, the output is measured at V_DDO/2.

NOTE 3: These parameters are guaranteed by characterization. Not tested in production.

NOTE 4: Driving only one input clock.

NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.

TABLE 5E. AC CHARACTERISTICS, V_DD= 2.5V 5ꢀ, V_DDO= 1.8V -0.2V, TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

f_MAX

Output Frequency

250

MHz

Propagation Delay, Low to High;

NOTE 1

Propagation Delay, High to Low;

NOTE 1

tp_LH

2.9

3

ns

tp_HL

ns

tsk(i)

Input Skew; NOTE 5

43

ps

tsk(pp)

Part-to-Part Skew; NOTE 2, 5

TBD

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter section,

NOTE 4

Integration Range:

12KHz - 20MHz

tjit

0.07

ps

t_R/ t_F

odc

t_EN

Output Rise/Fall Time

20ꢀ to 80ꢀ

590

50

ps

ꢀ

Output Duty Cycle

Output Enable Time; NOTE 3

Output Disable Time; NOTE 3

5

ns

dB

t_DIS

MUX_ISOLMUX Isolation

@100MHz

45

NOTE 1A: Measured from V_DD/2 of the input to V_DDO/2 of the output.

NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and

with equal load conditions. Using the same type of input on each device, the output is measured at V_DDO/2.

NOTE 3: These parameters are guaranteed by characterization. Not tested in production.

NOTE 4: Driving only one input clock.

NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.

83052AGI-01

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REV. A NOVEMBER 24, 2004

6

PRELIMINARY

ICS83052I-01

Integrated

Circuit

Systems, Inc.

2-BIT, 2:1,

S

INGLE-ENDED

MULTIPLEXER

ADDITIVE PHASE JITTER

the 1Hz band to the power in the fundamental. When the re-

quired offset is specified, the phase noise is called a dBc value,

which simply means dBm at a specified offset from the funda-

mental. By investigating jitter in the frequency domain, we get a

better understanding of its effects on the desired application over

the entire time record of the signal. It is mathematically possible

to calculate an expected bit error rate given a phase noise plot.

The spectral purity in a band at a specific offset from the funda-

mental compared to the power of the fundamental is called the

dBc Phase Noise. This value is normally expressed using a

Phase noise plot and is most often the specified plot in many

applications. Phase noise is defined as the ratio of the noise

power present in a 1Hz band at a specified offset from the fun-

damental frequency to the power value of the fundamental.This

ratio is expressed in decibels (dBm) or a ratio of the power in

0

-10

-20

-30

-40

Additive Phase Jitter (Random)

at 155.52MHz (12KHz - 20MHz)

= 0.07ps (typical)

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

1k

10k

100k

1M

10M

100M

OFFSET FROM CARRIER FREQUENCY (HZ)

As with most timing specifications, phase noise measure- above.The device meets the noise floor of what is shown, but

ments have issues. The primary issue relates to the limita- can actually be lower. The phase noise is dependant on the

tions of the equipment. Often the noise floor of the equipment input source and measurement equipment.

is higher than the noise floor of the device. This is illustrated

83052AGI-01

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REV. A NOVEMBER 24, 2004

7

PRELIMINARY

ICS83052I-01

Integrated

Circuit

Systems, Inc.

2-BIT, 2:1,

S

INGLE-ENDED

MULTIPLEXER

PARAMETER MEASUREMENT INFORMATION

1.65V 5ꢀ

1.25V 5ꢀ

SCOPE

V_DD

V_DDO

,

V_DD

V_DDO

,

Qx

LVCMOS

GND

LVCMOS

GND

-1.65V 5ꢀ

-1.25V 5ꢀ

3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT

2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT

2.4 0.065V

V_DD

2.05V 5ꢀ 1.25V 5ꢀ

0.9V 0.1V

SCOPE

V_DD

V_DDO

Qx

LVCMOS

GND

-0.9V 0.1V

-1.25V 5ꢀ

3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT

1.6V 0.025V

3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT

0.9V 0.1V

Part 1

Qx

V_DDO

2

SCOPE

V_DD

V_DDO

Qx

LVCMOS

Part 2

Qy

V_DDO

GND

2

tsk(pp)

-0.9V 0.1V

2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT

PART-TO-PART SKEW

83052AGI-01

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REV. A NOVEMBER 24, 2004

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PRELIMINARY

ICS83052I-01

Integrated

Circuit

Systems, Inc.

2-BIT, 2:1,

S

INGLE-ENDED

MULTIPLEXER

V_DD

2

80ꢀ

t_F

80ꢀ

t_R

CLK0, CLK1

Q0, Q1

20ꢀ

V_DDO

2

Clock

Outputs

tp_LH

PROPAGATION DELAY

OUTPUT RISE/FALL TIME

CLKx

V_DDO

2

Q0, Q1

Pulse Width

t_PD1

t_PERIOD

t_PW

odc =

t_PERIOD

CLKy

Q0, Q1

t_PD2

INPUT SKEW

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

83052AGI-01

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REV. A NOVEMBER 24, 2004

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PRELIMINARY

ICS83052I-01

Integrated

Circuit

Systems, Inc.

2-BIT, 2:1,

S

INGLE-ENDED

MULTIPLEXER

RELIABILITY INFORMATION

TABLE 5. θ_JA^VS. AIR FLOW TABLE FOR 16 LEAD TSSOP

θ_JAbyVelocity (Linear Feet per Minute)

0

200

118.2°C/W

81.8°C/W

500

106.8°C/W

78.1°C/W

Single-Layer PCB, JEDEC Standard Test Boards

Multi-Layer PCB, JEDEC Standard Test Boards

137.1°C/W

89.0°C/W

NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.

TRANSISTOR COUNT

The transistor count for ICS83052I-01 is: 967

83052AGI-01

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REV. A NOVEMBER 24, 2004

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PRELIMINARY

ICS83052I-01

Integrated

Circuit

Systems, Inc.

2-BIT, 2:1,

S

INGLE-ENDED

MULTIPLEXER

PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP

T^ABLE6. PACKAGE DIMENSIONS

Millimeters

Minimum Maximum

SYMBOL

N

A

16

--

1.20

0.15

1.05

0.30

0.20

5.10

A1

A2

b

0.05

0.80

0.19

0.09

4.90

c

D

E

6.40 BASIC

0.65 BASIC

E1

e

4.30

4.50

L

0.45

0°

0.75

8°

α

aaa

--

0.10

Reference Document: JEDEC Publication 95, MO-153

83052AGI-01

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REV. A NOVEMBER 24, 2004

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PRELIMINARY

ICS83052I-01

Integrated

Circuit

Systems, Inc.

2-BIT, 2:1,

S

INGLE-ENDED

MULTIPLEXER

TABLE 7. ORDERING INFORMATION

Part/Order Number

ICS83052AGI-01

Marking

3052AI01

Package

Count

Temperature

-40°C to 85°C

16 Lead TSSOP

94 per tube

16 Lead TSSOP on Tape and Reel

2500

The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use

or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not

recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product

for use in life support devices or critical medical instruments.

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REV. A NOVEMBER 24, 2004

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