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  • 北京元坤伟业科技有限公司

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产品型号39VF040-70-4C-NHE的概述

芯片39VF040-70-4C-NHE的概述 39VF040-70-4C-NHE是一款广泛应用于嵌入式系统中的闪存芯片。这款产品由曾经辉煌的记忆体制造商默克(Micron Technology)生产。芯片的设计理念旨在提供高性能的存储解决方案,使其适合于各种电子设备,包括计算机、手机及各类消费电子产品。由于其较大的存储空间和较快的读写速度,该芯片在市场中拥有良好的口碑和广泛的应用前景。 芯片39VF040-70-4C-NHE的详细参数 39VF040-70-4C-NHE的核心特点在于其存储容量、访问速度和电源特性。具体参数如下: - 存储容量: 4Mb(512KB*8) - 访问时间: 70ns - 工作电压: 2.7V-3.6V - 封装类型: TSOP (Thin Small Outline Package) - 引脚数: 32 - 数据接口: 并行接口 - 擦除周期: 100,0...

产品型号39VF6401的Datasheet PDF文件预览

16 Mbit / 32 Mbit / 64 Mbit (x16) Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
SST39VF160x / 320x / 640x2.7V 16Mb / 32Mb / 64Mb (x16) MPF+ memories  
Preliminary Specifications  
FEATURES:  
Organized as 1M x16: SST39VF1601/1602  
2M x16: SST39VF3201/3202  
Security-ID Feature  
– SST: 128 bits; User: 128 bits  
Fast Read Access Time:  
4M x16: SST39VF6401/6402  
Single Voltage Read and Write Operations  
– 2.7-3.6V  
– 70 ns  
– 90 ns  
Superior Reliability  
Latched Address and Data  
– Endurance: 100,000 Cycles (Typical)  
– Greater than 100 years Data Retention  
Fast Erase and Word-Program:  
– Sector-Erase Time: 18 ms (typical)  
– Block-Erase Time: 18 ms (typical)  
– Chip-Erase Time: 40 ms (typical)  
– Word-Program Time: 7 µs (typical)  
Low Power Consumption (typical values at 5 MHz)  
– Active Current: 9 mA (typical)  
– Standby Current: 3 µA (typical)  
– Auto Low Power Mode: 3 µA (typical)  
Automatic Write Timing  
– Internal VPP Generation  
End-of-Write Detection  
Hardware Block-Protection/WP# Input Pin  
Top Block-Protection (top 32 KWord)  
for SST39VF1602/3202/6402  
– Bottom Block-Protection (bottom 32 KWord)  
for SST39VF1601/3201/6401  
Toggle Bits  
– Data# Polling  
CMOS I/O Compatibility  
JEDEC Standard  
Sector-Erase Capability  
– Uniform 2 KWord sectors  
Block-Erase Capability  
– Flash EEPROM Pinouts and command sets  
Packages Available  
– Uniform 32 KWord blocks  
Chip-Erase Capability  
– 48-lead TSOP (12mm x 20mm)  
– 48-ball TFBGA (6mm x 8mm) for 16M and 32M  
– 48-ball TFBGA (8mm x 10mm) for 64M  
Erase-Suspend/Erase-Resume Capabilities  
Hardware Reset Pin (RST#)  
PRODUCT DESCRIPTION  
The SST39VF160x/320x/640x devices are 1M x16, 2M  
x16, and 4M x16 respectively, CMOS Multi-Purpose  
Flash Plus (MPF+) manufactured with SST’s proprietary,  
high performance CMOS SuperFlash technology. The  
split-gate cell design and thick-oxide tunneling injector  
attain better reliability and manufacturability compared  
with alternate approaches. The SST39VF160x/320x/640x  
write (Program or Erase) with a 2.7-3.6V power supply.  
These devices conform to JEDEC standard pinouts for  
x16 memories.  
The SST39VF160x/320x/640x devices are suited for appli-  
cations that require convenient and economical updating of  
program, configuration, or data memory. For all system  
applications, they significantly improve performance and  
reliability, while lowering power consumption. They inher-  
ently use less energy during Erase and Program than alter-  
native flash technologies. The total energy consumed is a  
function of the applied voltage, current, and time of applica-  
tion. Since for any given voltage range, the SuperFlash  
technology uses less current to program and has a shorter  
erase time, the total energy consumed during any Erase or  
Program operation is less than alternative flash technolo-  
gies. These devices also improve flexibility while lowering  
the cost for program, data, and configuration storage appli-  
cations.  
Featuring high performance Word-Program, the  
SST39VF160x/320x/640x devices provide a typical Word-  
Program time of 7 µsec. These devices use Toggle Bit or  
Data# Polling to indicate the completion of Program opera-  
tion. To protect against inadvertent write, they have on-chip  
hardware and Software Data Protection schemes.  
Designed, manufactured, and tested for a wide spectrum of  
applications, these devices are offered with a guaranteed  
typical endurance of 100,000 cycles. Data retention is rated  
at greater than 100 years.  
The SuperFlash technology provides fixed Erase and Pro-  
gram times, independent of the number of Erase/Program  
cycles that have occurred. Therefore the system software  
or hardware does not have to be modified or de-rated as is  
necessary with alternative flash technologies, whose  
Erase and Program times increase with accumulated  
Erase/Program cycles.  
©2003 Silicon Storage Technology, Inc.  
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.  
MPF is a trademark of Silicon Storage Technology, Inc.  
S71223-03-000  
1
11/03  
These specifications are subject to change without notice.  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
To meet high density, surface mount requirements, the  
SST39VF160x/320x/640x are offered in 48-lead TSOP  
and 48-ball TFBGA packages. See Figures 1 and 2 for  
pin assignments.  
first. The Program operation, once initiated, will be com-  
pleted within 10 µs. See Figures 4 and 5 for WE# and CE#  
controlled Program operation timing diagrams and Figure  
19 for flowcharts. During the Program operation, the only  
valid reads are Data# Polling and Toggle Bit. During the  
internal Program operation, the host is free to perform addi-  
tional tasks. Any commands issued during the internal Pro-  
gram operation are ignored. During the command  
sequence, WP# should be statically held high or low.  
Device Operation  
Commands are used to initiate the memory operation func-  
tions of the device. Commands are written to the device  
using standard microprocessor write sequences. A com-  
mand is written by asserting WE# low while keeping CE#  
low. The address bus is latched on the falling edge of WE#  
or CE#, whichever occurs last. The data bus is latched on  
the rising edge of WE# or CE#, whichever occurs first.  
Sector/Block-Erase Operation  
The Sector- (or Block-) Erase operation allows the system  
to erase the device on a sector-by-sector (or block-by-  
block) basis. The SST39VF160x/320x/640x offer both Sec-  
tor-Erase and Block-Erase mode. The sector architecture  
is based on uniform sector size of 2 KWord. The Block-  
Erase mode is based on uniform block size of 32 KWord.  
The Sector-Erase operation is initiated by executing a six-  
byte command sequence with Sector-Erase command  
(30H) and sector address (SA) in the last bus cycle. The  
Block-Erase operation is initiated by executing a six-byte  
command sequence with Block-Erase command (50H)  
and block address (BA) in the last bus cycle. The sector or  
block address is latched on the falling edge of the sixth  
WE# pulse, while the command (30H or 50H) is latched on  
the rising edge of the sixth WE# pulse. The internal Erase  
operation begins after the sixth WE# pulse. The End-of-  
Erase operation can be determined using either Data#  
Polling or Toggle Bit methods. See Figures 9 and 10 for tim-  
ing waveforms and Figure 23 for the flowchart. Any com-  
mands issued during the Sector- or Block-Erase operation  
are ignored. When WP# is low, any attempt to Sector-  
(Block-) Erase the protected block will be ignored. During  
the command sequence, WP# should be statically held  
high or low.  
The SST39VF160x/320x/640x also have the Auto Low  
Power mode which puts the device in a near standby  
mode after data has been accessed with a valid Read  
operation. This reduces the IDD active read current from  
typically 9 mA to typically 3 µA. The Auto Low Power mode  
reduces the typical IDD active read current to the range of 2  
mA/MHz of Read cycle time. The device exits the Auto Low  
Power mode with any address transition or control signal  
transition used to initiate another Read cycle, with no  
access time penalty. Note that the device does not enter  
Auto-Low Power mode after power-up with CE# held  
steadily low, until the first address transition or CE# is  
driven high.  
Read  
The Read operation of the SST39VF160x/320x/640x is  
controlled by CE# and OE#, both have to be low for the  
system to obtain data from the outputs. CE# is used for  
device selection. When CE# is high, the chip is dese-  
lected and only standby power is consumed. OE# is the  
output control and is used to gate data from the output  
pins. The data bus is in high impedance state when  
either CE# or OE# is high. Refer to the Read cycle timing  
diagram for further details (Figure 3).  
Erase-Suspend/Erase-Resume Commands  
The Erase-Suspend operation temporarily suspends a  
Sector- or Block-Erase operation thus allowing data to be  
read from any memory location, or program data into any  
sector/block that is not suspended for an Erase operation.  
The operation is executed by issuing one byte command  
sequence with Erase-Suspend command (B0H). The  
device automatically enters read mode typically within 20  
µs after the Erase-Suspend command had been issued.  
Valid data can be read from any sector or block that is not  
suspended from an Erase operation. Reading at address  
location within erase-suspended sectors/blocks will output  
DQ2 toggling and DQ6 at “1”. While in Erase-Suspend  
mode, a Word-Program operation is allowed except for the  
sector or block selected for Erase-Suspend.  
Word-Program Operation  
The SST39VF160x/320x/640x are programmed on a  
word-by-word basis. Before programming, the sector  
where the word exists must be fully erased. The Program  
operation is accomplished in three steps. The first step is  
the three-byte load sequence for Software Data Protection.  
The second step is to load word address and word data.  
During the Word-Program operation, the addresses are  
latched on the falling edge of either CE# or WE#, which-  
ever occurs last. The data is latched on the rising edge of  
either CE# or WE#, whichever occurs first. The third step is  
the internal Program operation which is initiated after the  
rising edge of the fourth WE# or CE#, whichever occurs  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
2
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
To resume Sector-Erase or Block-Erase operation which has  
been suspended the system must issue Erase Resume  
command. The operation is executed by issuing one byte  
command sequence with Erase Resume command (30H)  
at any address in the last Byte sequence.  
ing the completion of an internal Write operation, the  
remaining data outputs may still be invalid: valid data on the  
entire data bus will appear in subsequent successive Read  
cycles after an interval of 1 µs. During internal Erase oper-  
ation, any attempt to read DQ7 will produce a ‘0’. Once the  
internal Erase operation is completed, DQ7 will produce a  
‘1’. The Data# Polling is valid after the rising edge of fourth  
WE# (or CE#) pulse for Program operation. For Sector-,  
Block- or Chip-Erase, the Data# Polling is valid after the  
rising edge of sixth WE# (or CE#) pulse. See Figure 6 for  
Data# Polling timing diagram and Figure 20 for a flowchart.  
Chip-Erase Operation  
The SST39VF160x/320x/640x provide a Chip-Erase oper-  
ation, which allows the user to erase the entire memory  
array to the “1” state. This is useful when the entire device  
must be quickly erased.  
The Chip-Erase operation is initiated by executing a six-  
byte command sequence with Chip-Erase command  
(10H) at address 5555H in the last byte sequence. The  
Erase operation begins with the rising edge of the sixth  
WE# or CE#, whichever occurs first. During the Erase  
operation, the only valid read is Toggle Bit or Data# Polling.  
See Table 6 for the command sequence, Figure 9 for tim-  
ing diagram, and Figure 23 for the flowchart. Any com-  
mands issued during the Chip-Erase operation are  
ignored. When WP# is low, any attempt to Chip-Erase will  
be ignored. During the command sequence, WP# should  
be statically held high or low.  
Toggle Bits (DQ6 and DQ2)  
During the internal Program or Erase operation, any con-  
secutive attempts to read DQ6 will produce alternating “1”s  
and “0”s, i.e., toggling between 1 and 0. When the internal  
Program or Erase operation is completed, the DQ6 bit will  
stop toggling. The device is then ready for the next opera-  
tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6)  
is valid after the rising edge of sixth WE# (or CE#) pulse.  
DQ6 will be set to “1” if a Read operation is attempted on an  
Erase-Suspended Sector/Block. If Program operation is ini-  
tiated in a sector/block not selected in Erase-Suspend  
mode, DQ6 will toggle.  
An additional Toggle Bit is available on DQ2, which can be  
used in conjunction with DQ6 to check whether a particular  
sector is being actively erased or erase-suspended. Table 1  
shows detailed status bits information. The Toggle Bit  
(DQ2) is valid after the rising edge of the last WE# (or CE#)  
pulse of Write operation. See Figure 7 for Toggle Bit timing  
diagram and Figure 20 for a flowchart.  
Write Operation Status Detection  
The SST39VF160x/320x/640x provide two software  
means to detect the completion of a Write (Program or  
Erase) cycle, in order to optimize the system write cycle  
time. The software detection includes two status bits: Data#  
Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write  
detection mode is enabled after the rising edge of WE#,  
which initiates the internal Program or Erase operation.  
TABLE 1: WRITE OPERATION STATUS  
The actual completion of the nonvolatile write is asyn-  
chronous with the system; therefore, either a Data# Poll-  
ing or Toggle Bit read may be simultaneous with the  
completion of the write cycle. If this occurs, the system  
may possibly get an erroneous result, i.e., valid data may  
appear to conflict with either DQ7 or DQ6. In order to pre-  
vent spurious rejection, if an erroneous result occurs, the  
software routine should include a loop to read the  
accessed location an additional two (2) times. If both  
reads are valid, then the device has completed the Write  
cycle, otherwise the rejection is valid.  
Status  
DQ7 DQ6  
DQ2  
Normal  
Operation Program  
Standard  
DQ7# Toggle No Toggle  
Standard  
Erase  
0
1
Toggle  
1
Toggle  
Toggle  
Erase-  
Read from  
Suspend Erase-Suspended  
Mode  
Sector/Block  
Read from  
Non- Erase-Suspended  
Sector/Block  
Data  
Data  
Data  
Program  
DQ7# Toggle  
N/A  
T1.0 1223  
Note: DQ7 and DQ2 require a valid address when reading  
Data# Polling (DQ7)  
status information.  
When the SST39VF160x/320x/640x are in the internal  
Program operation, any attempt to read DQ7 will produce  
the complement of the true data. Once the Program oper-  
ation is completed, DQ7 will produce true data. Note that  
even though DQ7 may have valid data immediately follow-  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
3
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
Data Protection  
Hardware Reset (RST#)  
The SST39VF160x/320x/640x provide both hardware and  
software features to protect nonvolatile data from inadvertent  
writes.  
The RST# pin provides a hardware method of resetting the  
device to read array data. When the RST# pin is held low  
for at least TRP, any in-progress operation will terminate and  
return to Read mode. When no internal Program/Erase  
operation is in progress, a minimum period of TRHR is  
required after RST# is driven high before a valid Read can  
take place (see Figure 15).  
Hardware Data Protection  
Noise/Glitch Protection: A WE# or CE# pulse of less than 5  
ns will not initiate a write cycle.  
The Erase or Program operation that has been interrupted  
needs to be reinitiated after the device resumes normal  
operation mode to ensure data integrity.  
VDD Power Up/Down Detection: The Write operation is  
inhibited when VDD is less than 1.5V.  
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#  
high will inhibit the Write operation. This prevents inadvert-  
ent writes during power-up or power-down.  
Software Data Protection (SDP)  
The SST39VF160x/320x/640x provide the JEDEC  
approved Software Data Protection scheme for all data  
alteration operations, i.e., Program and Erase. Any Pro-  
gram operation requires the inclusion of the three-byte  
sequence. The three-byte load sequence is used to initiate  
the Program operation, providing optimal protection from  
inadvertent Write operations, e.g., during the system  
power-up or power-down. Any Erase operation requires the  
inclusion of six-byte sequence. These devices are shipped  
with the Software Data Protection permanently enabled.  
See Table 6 for the specific software command codes. Dur-  
ing SDP command sequence, invalid commands will abort  
the device to read mode within TRC. The contents of DQ15-  
DQ8 can be VIL or VIH, but no other value, during any SDP  
command sequence.  
Hardware Block Protection  
The SST39VF1602/3202/6402 support top hardware block  
protection, which protects the top 32 KWord block of the  
device. The SST39VF1601/3201/6401 support bottom  
hardware block protection, which protects the bottom 32  
KWord block of the device. The Boot Block address ranges  
are described in Table 2. Program and Erase operations  
are prevented on the 32 KWord when WP# is low. If WP# is  
left floating, it is internally held high via a pull-up resistor,  
and the Boot Block is unprotected, enabling Program and  
Erase operations on that block.  
TABLE 2: BOOT BLOCK ADDRESS RANGES  
Product  
Address Range  
Common Flash Memory Interface (CFI)  
Bottom Boot Block  
SST39VF1601/3201/6401  
Top Boot Block  
SST39VF1602  
The SST39VF160x/320x/640x also contain the CFI infor-  
mation to describe the characteristics of the device. In  
order to enter the CFI Query mode, the system must write  
three-byte sequence, same as product ID entry command  
with 98H (CFI Query command) to address 5555H in the  
last byte sequence. Once the device enters the CFI Query  
mode, the system can read CFI data at the addresses  
given in Tables 7 through 10. The system must write the  
CFI Exit command to return to Read mode from the CFI  
Query mode.  
000000H-007FFFH  
0F8000H-0FFFFFH  
1F8000H-1FFFFFH  
3F8000H-3FFFFFH  
SST39VF3202  
SST39VF6402  
T2.0 1223  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
4
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
Product Identification  
Security ID  
The Product Identification mode identifies the devices as  
the SST39VF1601, SST39VF1602, SST39VF3201,  
SST39VF3202, SST39VF6401, SST39VF6402, and  
manufacturer as SST. This mode may be accessed soft-  
ware operations. Users may use the Software Product  
Identification operation to identify the part (i.e., using the  
device ID) when using multiple manufacturers in the same  
socket. For details, see Table 6 for software operation,  
Figure 11 for the Software ID Entry and Read timing dia-  
gram and Figure 21 for the Software ID Entry command  
sequence flowchart.  
The SST39VF160x/320x/640x devices offer a 256-bit  
Security ID space. The Secure ID space is divided into two  
128-bit segments - one factory programmed segment and  
one user programmed segment. The first segment is pro-  
grammed and locked at SST with a random 128-bit num-  
ber. The user segment is left un-programmed for the  
customer to program as desired.  
To program the user segment of the Security ID, the user  
must use the Security ID Word-Program command. To  
detect end-of-write for the SEC ID, read the toggle bits. Do  
not use Data# Polling. Once this is complete, the Sec ID  
should be locked using the User Sec ID Program Lock-Out.  
This disables any future corruption of this space. Note that  
regardless of whether or not the Sec ID is locked, neither  
Sec ID segment can be erased.  
TABLE 3: PRODUCT IDENTIFICATION  
Address  
Data  
Manufacturer’s ID  
Device ID  
0000H  
BFH  
The Secure ID space can be queried by executing a three-  
byte command sequence with Enter Sec ID command  
(88H) at address 5555H in the last byte sequence. To exit  
this mode, the Exit Sec ID command should be executed.  
Refer to Table 6 for more details.  
SST39VF1601  
SST39VF1602  
SST39VF3201  
SST39VF3202  
SST39VF6401  
SST39VF6402  
0001H  
0001H  
0001H  
0001H  
0001H  
0001H  
234BH  
234AH  
235BH  
235AH  
236BH  
236AH  
T3.2 1223  
Product Identification Mode Exit/  
CFI Mode Exit  
In order to return to the standard Read mode, the Software  
Product Identification mode must be exited. Exit is accom-  
plished by issuing the Software ID Exit command  
sequence, which returns the device to the Read mode.  
This command may also be used to reset the device to the  
Read mode after any inadvertent transient condition that  
apparently causes the device to behave abnormally, e.g.,  
not read correctly. Please note that the Software ID Exit/  
CFI Exit command is ignored during an internal Program or  
Erase operation. See Table 6 for software command  
codes, Figure 13 for timing waveform, and Figures 21 and  
22 for flowcharts.  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
5
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
FUNCTIONAL BLOCK DIAGRAM  
SuperFlash  
Memory  
X-Decoder  
Memory Address  
Address Buffer & Latches  
Y-Decoder  
CE#  
OE#  
WE#  
I/O Buffers and Data Latches  
Control Logic  
WP#  
DQ - DQ  
15  
RESET#  
0
1223 B1.0  
SST39VF160x/320x/640x  
SST39VF6401/6402 SST39VF3201/3202  
SST39VF1601/1602  
A16  
NC  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
1
48  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
2
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
V
3
SS  
DQ15  
DQ7  
4
5
DQ14  
DQ6  
6
7
DQ13  
DQ5  
A8  
A8  
8
A8  
Standard Pinout  
Top View  
A19  
A20  
WE#  
RST#  
A21  
WP#  
NC  
A19  
A20  
WE#  
RST#  
NC  
9
A19  
NC  
DQ12  
DQ4  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
WE#  
RST#  
NC  
V
DD  
Die Up  
DQ11  
DQ3  
DQ10  
DQ2  
DQ9  
DQ1  
DQ8  
DQ0  
OE#  
WP#  
NC  
WP#  
NC  
A18  
A17  
A7  
A18  
A17  
A7  
A18  
A17  
A7  
A6  
A6  
A6  
A5  
A5  
A5  
A4  
A4  
A4  
V
A3  
A3  
A3  
SS  
CE#  
A0  
A2  
A2  
A2  
A1  
A1  
A1  
1223 48-tsop P01.3  
FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TSOP  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
6
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
TOP VIEW (balls facing down)  
SST39VF1601/1602  
TOP VIEW (balls facing down)  
SST39VF3201/3202  
6
5
4
3
2
1
6
5
4
3
2
1
A13 A12 A14 A15 A16 NC DQ15 V  
A13 A12 A14 A15 A16 NC DQ15 V  
SS  
SS  
A9  
A8 A10 A11 DQ7 DQ14 DQ13 DQ6  
A9  
A8 A10 A11 DQ7 DQ14 DQ13 DQ6  
WE# RST# NC A19 DQ5 DQ12  
V
DQ4  
DD  
WE# RST# NC A19 DQ5 DQ12  
V
DQ4  
DD  
NC WP# A18 NC DQ2 DQ10 DQ11 DQ3  
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1  
A3 A4 A2 A1 A0 CE# OE#  
NC WP# A18 A20 DQ2 DQ10 DQ11 DQ3  
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1  
A3 A4 A2 A1 A0 CE# OE#  
V
V
SS  
SS  
A B C D E F G H  
A B C D E F G H  
TOP VIEW (balls facing down)  
SST39VF6401/6402  
6
5
4
3
2
1
A13 A12 A14 A15 A16 NC DQ15 V  
SS  
A9  
A8 A10 A11 DQ7 DQ14 DQ13 DQ6  
WE# RST# A21 A19 DQ5 DQ12  
V
DQ4  
DD  
NC WP# A18 A20 DQ2 DQ10 DQ11 DQ3  
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1  
A3 A4 A2 A1 A0 CE# OE#  
V
SS  
A B C D E F G H  
FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
7
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
TABLE 4: PIN DESCRIPTION  
Symbol  
Pin Name  
Functions  
AMS1-A0  
Address Inputs  
To provide memory addresses.  
During Sector-Erase AMS-A11 address lines will select the sector.  
During Block-Erase AMS-A15 address lines will select the block.  
DQ15-DQ0  
Data Input/output  
To output data during Read cycles and receive input data during Write cycles.  
Data is internally latched during a Write cycle.  
The outputs are in tri-state when OE# or CE# is high.  
WP#  
RST#  
CE#  
OE#  
WE#  
VDD  
Write Protect  
Reset  
To protect the top/bottom boot block from Erase/Program operation when grounded.  
To reset and return the device to Read mode.  
To activate the device when CE# is low.  
Chip Enable  
Output Enable  
Write Enable  
Power Supply  
Ground  
To gate the data output buffers.  
To control the Write operations.  
To provide power supply voltage: 2.7-3.6V  
VSS  
NC  
No Connection  
Unconnected pins.  
T4.2 1223  
1. AMS = Most significant address  
MS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402  
A
TABLE 5: OPERATION MODES SELECTION  
Mode  
Read  
CE#  
VIL  
OE#  
VIL  
WE#  
VIH  
VIL  
DQ  
DOUT  
DIN  
X1  
Address  
AIN  
Program  
Erase  
VIL  
VIH  
VIH  
AIN  
VIL  
VIL  
Sector or block address,  
XXH for Chip-Erase  
Standby  
VIH  
X
X
VIL  
X
X
X
High Z  
X
X
X
Write Inhibit  
High Z/ DOUT  
High Z/ DOUT  
X
VIH  
Product Identification  
Software Mode  
VIL  
VIL  
VIH  
See Table 6  
T5.0 1223  
1. X can be VIL or VIH, but no other value.  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
8
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
TABLE 6: SOFTWARE COMMAND SEQUENCE  
Command  
Sequence  
1st Bus  
Write Cycle  
2nd Bus  
Write Cycle  
3rd Bus  
Write Cycle  
4th Bus  
Write Cycle  
5th Bus  
Write Cycle  
6th Bus  
Write Cycle  
Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2  
WA3  
Data  
Word-Program  
Sector-Erase  
Block-Erase  
5555H  
5555H  
5555H  
5555H  
AAH 2AAAH 55H 5555H A0H  
4
4
AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H  
AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H  
SAX  
BAX  
30H  
50H  
Chip-Erase  
AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H  
Erase-Suspend  
Erase-Resume  
Query Sec ID5  
XXXXH B0H  
XXXXH 30H  
5555H  
5555H  
AAH 2AAAH 55H 5555H 88H  
AAH 2AAAH 55H 5555H A5H  
WA6  
Data  
User Security ID  
Word-Program  
XXH6 0000H  
User Security ID  
Program Lock-Out  
5555H  
AAH 2AAAH 55H 5555H 85H  
Software ID Entry7,8  
5555H  
5555H  
5555H  
AAH 2AAAH 55H 5555H 90H  
AAH 2AAAH 55H 5555H 98H  
AAH 2AAAH 55H 5555H F0H  
CFI Query Entry  
Software ID Exit9,10  
/CFI Exit/Sec ID Exit  
Software ID Exit9,10  
/CFI Exit/Sec ID Exit  
XXH  
F0H  
T6.6 1223  
1. Address format A14-A0 (Hex).  
Addresses A15-A19 can be VIL or VIH, but no other value, for Command sequence for SST39VF1601/1602,  
Addresses A15-A20 can be VIL or VIH, but no other value, for Command sequence for SST39VF3201/3202,  
Addresses A15- A21 can be VIL or VIH, but no other value, for Command sequence for SST39VF6401/6402.  
2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence  
3. WA = Program Word address  
4. SAX for Sector-Erase; uses AMS-A11 address lines  
BAX, for Block-Erase; uses AMS-A15 address lines  
AMS = Most significant address  
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402  
5. With AMS-A4 = 0; Sec ID is read with A3-A0,  
SST ID is read with A3 = 0 (Address range = 000000H to 000007H),  
User ID is read with A3 = 1 (Address range = 000010H to 000017H).  
Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.  
6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000010H-000017H.  
7. The device does not remain in Software Product ID Mode if powered down.  
8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0,  
SST39VF1601 Device ID = 234BH, is read with A0 = 1,  
SST39VF1602 Device ID = 234AH, is read with A0 = 1,  
SST39VF3201 Device ID = 235BH, is read with A0 = 1,  
SST39VF3202 Device ID = 235AH, is read with A0 = 1,  
SST39VF6401 Device ID = 236BH, is read with A0 = 1,  
SST39VF6402 Device ID = 236AH, is read with A0 = 1.  
AMS = Most significant address  
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402  
9. Both Software ID Exit operations are equivalent  
10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID  
mode again (the programmed “0” bits cannot be reversed to “1”). Valid Word-Addresses for Sec ID are from 000000H-000007H and  
000010H-000017H.  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
9
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
1
TABLE 7: CFI QUERY IDENTIFICATION STRING FOR SST39VF160X/320X/640X  
Address  
10H  
11H  
12H  
13H  
14H  
15H  
16H  
17H  
Data  
Data  
0051H  
0052H  
0059H  
0001H  
0007H  
0000H  
0000H  
0000H  
0000H  
0000H  
0000H  
Query Unique ASCII string “QRY”  
Primary OEM command set  
Address for Primary Extended Table  
Alternate OEM command set (00H = none exists)  
Address for Alternate OEM extended Table (00H = none exits)  
18H  
19H  
1AH  
T7.1 1223  
1. Refer to CFI publication 100 for more details.  
TABLE 8: SYSTEM INTERFACE INFORMATION FOR SST39VF160X/320X/640X  
Address  
Data  
Data  
1BH  
0027H  
VDD Min (Program/Erase)  
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts  
1CH  
0036H  
VDD Max (Program/Erase)  
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts  
1DH  
1EH  
1FH  
20H  
21H  
22H  
23H  
24H  
25H  
26H  
0000H  
0000H  
0003H  
0000H  
0004H  
0005H  
0001H  
0000H  
0001H  
0001H  
VPP min. (00H = no VPP pin)  
VPP max. (00H = no VPP pin)  
Typical time out for Word-Program 2N µs (23 = 8 µs)  
Typical time out for min. size buffer program 2N µs (00H = not supported)  
Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)  
Typical time out for Chip-Erase 2N ms (25 = 32 ms)  
Maximum time out for Word-Program 2N times typical (21 x 23 = 16 µs)  
Maximum time out for buffer program 2N times typical  
Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)  
Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms)  
T8.3 1223  
TABLE 9: DEVICE GEOMETRY INFORMATION FOR SST39VF1601/1602  
Address  
27H  
28H  
Data  
Data  
0015H  
0001H  
0000H  
0000H  
0000H  
0002H  
00FFH  
0001H  
0010H  
0000H  
001FH  
0000H  
0000H  
0001H  
Device size = 2N Bytes (15H = 21; 221 = 2 MByte)  
Flash Device Interface description; 0001H = x16-only asynchronous interface  
29H  
2AH  
2BH  
2CH  
2DH  
2EH  
2FH  
30H  
31H  
32H  
33H  
34H  
Maximum number of byte in multi-byte write = 2N (00H = not supported)  
Number of Erase Sector/Block sizes supported by device  
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)  
y = 511 + 1 = 512 sectors (01FF = 511  
z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)  
Block Information (y + 1 = Number of blocks; z x 256B = block size)  
y = 31 + 1 = 32 blocks (001F = 31)  
z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)  
T9.0 1223  
S71223-03-000 11/03  
©2003 Silicon Storage Technology, Inc.  
10  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
TABLE 10: DEVICE GEOMETRY INFORMATION FOR SST39VF3201/3202  
Address  
27H  
28H  
Data  
Data  
0016H  
0001H  
0000H  
0000H  
0000H  
0002H  
00FFH  
0003H  
0010H  
0000H  
003FH  
0000H  
0000H  
0001H  
Device size = 2N Bytes (16H = 22; 222 = 4 MByte)  
Flash Device Interface description; 0001H = x16-only asynchronous interface  
29H  
2AH  
2BH  
2CH  
2DH  
2EH  
2FH  
30H  
31H  
32H  
33H  
34H  
Maximum number of byte in multi-byte write = 2N (00H = not supported)  
Number of Erase Sector/Block sizes supported by device  
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)  
y = 1023 + 1 = 1024 (03FFH = 1023)  
z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)  
Block Information (y + 1 = Number of blocks; z x 256B = block size)  
y = 63 + 1 = 64 blocks (003FH = 63)  
z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)  
T10.2 1223  
TABLE 11: DEVICE GEOMETRY INFORMATION FOR SST39VF6401/6402  
Address  
27H  
28H  
Data  
Data  
0017H  
0001H  
0000H  
0000H  
0000H  
0002H  
00FFH  
0007H  
0010H  
0000H  
007FH  
0000H  
0000H  
0001H  
Device size = 2N Bytes (17H = 23; 223 = 8 MByte)  
Flash Device Interface description; 0001H = x16-only asynchronous interface  
29H  
2AH  
2BH  
2CH  
2DH  
2EH  
2FH  
30H  
31H  
32H  
33H  
34H  
Maximum number of bytes in multi-byte write = 2N (00H = not supported)  
Number of Erase Sector/Block sizes supported by device  
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)  
y = 2047 + 1 = 2048 sectors (07FFH = 2047)  
z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)  
Block Information (y + 1 = Number of blocks; z x 256B = block size)  
y =127 + 1 = 128 blocks (007FH = 127)  
z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)  
T11.2 1223  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
11  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum  
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation  
of the device at these conditions or conditions greater than those defined in the operational sections of this data  
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)  
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C  
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C  
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V  
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V  
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V  
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W  
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C  
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
1. Outputs shorted for no more than one second. No more than one output shorted at a time.  
OPERATING RANGE  
Range  
Ambient Temp  
VDD  
Commercial  
Industrial  
0°C to +70°C  
-40°C to +85°C  
2.7-3.6V  
2.7-3.6V  
AC CONDITIONS OF TEST  
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns  
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF  
See Figures 17 and 18  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
12  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
TABLE 12: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V1  
Limits  
Symbol Parameter  
Min  
Max  
Units  
Test Conditions  
IDD  
Power Supply Current  
Address input=VILT/VIHT2, at f=5 MHz,  
VDD=VDD Max  
Read3  
18  
35  
20  
20  
mA  
mA  
µA  
CE#=VIL, OE#=WE#=VIH, all I/Os open  
CE#=WE#=VIL, OE#=VIH  
Program and Erase  
Standby VDD Current  
Auto Low Power  
ISB  
CE#=VIHC, VDD=VDD Max  
IALP  
µA  
CE#=VILC, VDD=VDD Max  
All inputs=VSS or VDD, WE#=VIHC  
ILI  
Input Leakage Current  
1
µA  
µA  
VIN=GND to VDD, VDD=VDD Max  
ILIW  
Input Leakage Current  
on WP# pin and RST#  
10  
WP#=GND to VDD or RST#=GND to VDD  
ILO  
Output Leakage Current  
Input Low Voltage  
10  
0.8  
0.3  
µA  
V
VOUT=GND to VDD, VDD=VDD Max  
VDD=VDD Min  
VIL  
VILC  
VIH  
Input Low Voltage (CMOS)  
Input High Voltage  
V
VDD=VDD Max  
0.7VDD  
V
VDD=VDD Max  
VIHC  
VOL  
VOH  
Input High Voltage (CMOS)  
Output Low Voltage  
VDD-0.3  
V
VDD=VDD Max  
0.2  
V
IOL=100 µA, VDD=VDD Min  
Output High Voltage  
VDD-0.2  
V
IOH=-100 µA, VDD=VDD Min  
T12.8 1223  
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C  
(room temperature), and VDD = 3V. Not 100% tested.  
2. See Figure 17  
3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V.  
TABLE 13: RECOMMENDED SYSTEM POWER-UP TIMINGS  
Symbol  
Parameter  
Minimum  
100  
Units  
µs  
1
TPU-READ  
Power-up to Read Operation  
Power-up to Program/Erase Operation  
1
TPU-WRITE  
100  
µs  
T13.0 1223  
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.  
TABLE 14: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)  
Parameter  
Description  
Test Condition  
VI/O = 0V  
Maximum  
1
CI/O  
I/O Pin Capacitance  
Input Capacitance  
12 pF  
6 pF  
1
CIN  
VIN = 0V  
T14.0 1223  
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.  
TABLE 15: RELIABILITY CHARACTERISTICS  
Symbol  
Parameter  
Endurance  
Data Retention  
Latch Up  
Minimum Specification  
Units  
Cycles  
Years  
mA  
Test Method  
1,2  
NEND  
10,000  
100  
JEDEC Standard A117  
JEDEC Standard A103  
JEDEC Standard 78  
1
TDR  
1
ILTH  
100 + IDD  
T15.2 1223  
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.  
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a  
higher minimum specification.  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
13  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
AC CHARACTERISTICS  
TABLE 16: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V  
SST39VFxx01/xx02-70  
SST39VFxx01/xx02-90  
Symbol  
TRC  
Parameter  
Min  
Max  
Min  
Max  
Units  
ns  
Read Cycle Time  
70  
90  
TCE  
Chip Enable Access Time  
Address Access Time  
70  
70  
35  
90  
90  
45  
ns  
TAA  
ns  
TOE  
Output Enable Access Time  
CE# Low to Active Output  
OE# Low to Active Output  
CE# High to High-Z Output  
OE# High to High-Z Output  
Output Hold from Address Change  
RST# Pulse Width  
ns  
1
TCLZ  
0
0
0
0
ns  
1
TOLZ  
ns  
1
TCHZ  
20  
20  
30  
30  
ns  
1
TOHZ  
ns  
1
TOH  
0
0
ns  
1
TRP  
500  
50  
500  
50  
ns  
1
TRHR  
RST# High before Read  
RST# Pin Low to Read Mode  
ns  
1,2  
TRY  
20  
20  
µs  
T16.3 1223  
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.  
2. This parameter applies to Sector-Erase, Block-Erase and Program operations.  
This parameter does not apply to Chip-Erase operations.  
TABLE 17: PROGRAM/ERASE CYCLE TIMING PARAMETERS  
Symbol Parameter  
Min  
Max  
Units  
µs  
TBP  
Word-Program Time  
10  
TAS  
Address Setup Time  
Address Hold Time  
WE# and CE# Setup Time  
WE# and CE# Hold Time  
OE# High Setup Time  
OE# High Hold Time  
CE# Pulse Width  
0
30  
0
ns  
TAH  
ns  
TCS  
ns  
TCH  
TOES  
TOEH  
TCP  
0
ns  
0
ns  
10  
40  
40  
30  
30  
30  
0
ns  
ns  
TWP  
WE# Pulse Width  
ns  
1
TWPH  
WE# Pulse Width High  
CE# Pulse Width High  
Data Setup Time  
ns  
1
TCPH  
TDS  
ns  
ns  
1
TDH  
Data Hold Time  
ns  
1
TIDA  
Software ID Access and Exit Time  
Sector-Erase  
150  
25  
ns  
TSE  
ms  
ms  
TBE  
Block-Erase  
25  
TSCE  
Chip-Erase  
50  
ms  
T17.1 1223  
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
14  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
T
T
AA  
RC  
ADDRESS A  
MS-0  
CE#  
OE#  
WE#  
T
CE  
T
OE  
T
T
OHZ  
V
OLZ  
IH  
T
CHZ  
T
OH  
T
HIGH-Z  
CLZ  
HIGH-Z  
DQ  
15-0  
DATA VALID  
DATA VALID  
1223 F03.2  
Note:  
A
A
= Most significant address  
MS  
= A for SST39VF1601/1602, A for SST39VF3201/3202, and A for SST39VF6401/6402  
MS  
19  
20  
21  
FIGURE 3: READ CYCLE TIMING DIAGRAM  
INTERNAL PROGRAM OPERATION STARTS  
T
BP  
5555  
2AAA  
5555  
ADDR  
ADDRESS A  
MS-0  
T
AH  
T
DH  
T
WP  
WE#  
T
T
AS  
DS  
T
WPH  
OE#  
CE#  
T
CH  
T
CS  
DQ  
15-0  
XXAA  
SW0  
XX55  
SW1  
XXA0  
SW2  
DATA  
WORD  
(ADDR/DATA)  
1223 F04.3  
Note:  
A
= Most significant address  
MS  
MS  
A
= A for SST39VF1601/1602, A for SST39VF3201/3202, and A for SST39VF6401/6402  
19  
20 21  
WP# must be held in proper logic state (V or V ) 1 µs prior to and 1 µs after the command sequence  
IL  
IH  
X can be V or V but no other value  
IH,  
IL  
FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
15  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
INTERNAL PROGRAM OPERATION STARTS  
T
BP  
5555  
2AAA  
5555  
ADDR  
ADDRESS A  
MS-0  
T
AH  
T
DH  
T
CP  
CE#  
T
T
AS  
DS  
T
CPH  
OE#  
WE#  
T
CH  
T
CS  
DQ  
15-0  
XXAA  
SW0  
XX55  
SW1  
XXA0  
SW2  
DATA  
WORD  
(ADDR/DATA)  
1223 F05.3  
Note:  
A
= Most significant address  
MS  
MS  
A
= A for SST39VF1601/1602, A for SST39VF3201/3202, and A for SST39VF6401/6402  
19 20 21  
WP# must be held in proper logic state (V or V ) 1 µs prior to and 1 µs after the command sequence  
IL  
IH  
X can be V or V but no other value  
IH,  
IL  
FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM  
ADDRESS A  
MS-0  
T
CE  
CE#  
OE#  
WE#  
T
OES  
T
OEH  
T
OE  
DQ  
7
DATA  
DATA#  
DATA#  
DATA  
1223 F06.2  
Note:  
A
A
= Most significant address  
MS  
= A for SST39VF1601/1602, A for SST39VF3201/3202, and A for SST39VF6401/6402  
MS  
19  
20  
21  
FIGURE 6: DATA# POLLING TIMING DIAGRAM  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
16  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
ADDRESS A  
MS-0  
T
CE  
CE#  
OE#  
WE#  
T
OES  
T
T
OE  
OEH  
DQ and DQ  
6
2
TWO READ CYCLES  
WITH SAME OUTPUTS  
1223 F07.3  
Note:  
A
A
= Most significant address  
MS  
= A for SST39VF1601/1602, A for SST39VF3201/3202, and A for SST39VF6401/6402  
MS  
19  
20  
21  
FIGURE 7: TOGGLE BITS TIMING DIAGRAM  
T
SCE  
SIX-BYTE CODE FOR CHIP-ERASE  
5555 5555 2AAA  
5555  
2AAA  
5555  
ADDRESS A  
MS-0  
CE#  
OE#  
T
WP  
WE#  
DQ  
15-0  
XXAA  
SW0  
XX55  
SW1  
XX80  
SW2  
XXAA  
SW3  
XX55  
SW4  
XX10  
SW5  
1223 F08.4  
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are  
interchageable as long as minimum timings are met. (See Table 17)  
A
MS  
A
MS  
= Most significant address  
= A for SST39VF1601/1602, A for SST39VF3201/3202, and A for SST39VF6401/6402  
19  
20  
21  
WP# must be held in proper logic state (V ) 1 µs prior to and 1 µs after the command sequence  
IH  
X can be V or V but no other value  
IH,  
IL  
FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
17  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
T
BE  
SIX-BYTE CODE FOR BLOCK-ERASE  
5555 5555 2AAA  
5555  
2AAA  
BA  
ADDRESS A  
MS-0  
X
CE#  
OE#  
WE#  
T
WP  
DQ  
15-0  
XXAA  
SW0  
XX55  
SW1  
XX80  
SW2  
XXAA  
SW3  
XX55  
SW4  
XX50  
SW5  
1223 F09.4  
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are  
interchageable as long as minimum timings are met. (See Table 17)  
BA = Block Address  
X
A
A
= Most significant address  
MS  
MS  
= A for SST39VF1601/1602, A for SST39VF3201/3202, and A for SST39VF6401/6402  
19 20 21  
WP# must be held in proper logic state (V or V ) 1 µs prior to and 1 µs after the command sequence  
IL IH  
X can be V or V but no other value  
IL IH,  
FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM  
T
SE  
SIX-BYTE CODE FOR SECTOR-ERASE  
5555  
2AAA  
5555  
5555  
2AAA  
SA  
ADDRESS A  
X
MS-0  
CE#  
OE#  
WE#  
T
WP  
DQ  
XXAA  
SW0  
XX55  
SW1  
XX80  
SW2  
XXAA  
SW3  
XX55  
SW4  
XX30  
SW5  
15-0  
1223 F10.4  
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are  
interchageable as long as minimum timings are met. (See Table 17)  
SA = Sector Address  
X
A
MS  
A
MS  
= Most significant address  
= A for SST39VF1601/1602, A for SST39VF3201/3202, and A for SST39VF6401/6402  
19  
20  
21  
WP# must be held in proper logic state (V or V ) 1 µs prior to and 1 µs after the command sequence  
IL  
IH  
X can be V or V , but no other value  
IL  
IH  
FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
18  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
Three-Byte Sequence for Software ID Entry  
ADDRESS A  
5555  
2AAA  
5555  
0000  
0001  
14-0  
CE#  
OE#  
WE#  
T
IDA  
T
WP  
T
WPH  
T
AA  
DQ  
15-0  
XXAA  
SW0  
XX55  
SW1  
XX90  
SW2  
00BF  
Device ID  
1223 F11.2  
Note: Device ID = 234BH for 39VF1601, 234AH for 39VF1602, 235BH for 39VF3201, 235AH for 39VF3202,  
236BH for 39VF6401, and 236AH for 39VF6402,  
WP# must be held in proper logic state (V or V ) 1 µs prior to and 1 µs after the command sequence  
IL  
IH  
X can be V or V but no other value  
IH,  
IL  
FIGURE 11: SOFTWARE ID ENTRY AND READ  
Three-Byte Sequence for CFI Query Entry  
ADDRESS A  
5555  
2AAA  
5555  
14-0  
CE#  
OE#  
WE#  
T
IDA  
T
WP  
T
WPH  
T
AA  
DQ  
15-0  
XXAA  
SW0  
XX55  
SW1  
XX98  
SW2  
1223 F12.1  
Note:  
WP# must be held in proper logic state (V or V ) 1 µs prior to and 1 µs after the command sequence  
IL IH  
X can be V or V but no other value  
IH,  
IL  
FIGURE 12: CFI QUERY ENTRY AND READ  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
19  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
THREE-BYTE SEQUENCE FOR  
SOFTWARE ID EXIT AND RESET  
5555  
2AAA  
5555  
ADDRESS A  
DQ  
14-0  
XXAA  
XX55  
XXF0  
15-0  
T
IDA  
CE#  
OE#  
T
WP  
WE#  
T
WHP  
SW0  
SW1  
SW2  
1223 F13.0  
Note:  
WP# must be held in proper logic state (V or V ) 1 µs prior to and 1 µs after the command sequence  
IL  
IH  
X can be V or V but no other value  
IH,  
IL  
FIGURE 13: SOFTWARE ID EXIT/CFI EXIT  
THREE-BYTE SEQUENCE FOR  
CFI QUERY ENTRY  
ADDRESS A  
5555  
2AAA  
5555  
MS-0  
CE#  
OE#  
WE#  
T
IDA  
T
WP  
T
WPH  
T
AA  
DQ  
15-0  
XXAA  
SW0  
XX55  
SW1  
XX88  
SW2  
1223 F20.1  
Note:  
A
A
= Most significant address  
MS  
= A for SST39VF1601/1602, A for SST39VF3201/3202, and A for SST39VF6401/6402  
MS  
19  
20  
21  
WP# must be held in proper logic state (V or V ) 1 µs prior to and 1 µs after the command sequence  
IL  
IH  
X can be V or V but no other value.  
IH,  
IL  
FIGURE 14: SEC ID ENTRY  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
20  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
T
RP  
RST#  
T
RHR  
CE#/OE#  
1223 F22.1  
FIGURE 15: RST# TIMING DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS)  
T
RP  
RST#  
T
RY  
CE#/OE#  
End-of-Write Detection  
(Toggle-Bit)  
1223 F23.0  
FIGURE 16: RST# TIMING DIAGRAM (DURING PROGRAM OR ERASE OPERATION)  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
21  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
V
IHT  
V
V
INPUT  
REFERENCE POINTS  
OUTPUT  
OT  
IT  
V
ILT  
1223 F14.0  
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points  
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns.  
Note: VIT - VINPUT Test  
VOT - VOUTPUT Test  
V
IHT - VINPUT HIGH Test  
VILT - VINPUT LOW Test  
FIGURE 17: AC INPUT/OUTPUT REFERENCE WAVEFORMS  
TO TESTER  
TO DUT  
C
L
1223 F15.0  
FIGURE 18: A TEST LOAD EXAMPLE  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
22  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
Start  
Load data: XXAAH  
Address: 5555H  
Load data: XX55H  
Address: 2AAAH  
Load data: XXA0H  
Address: 5555H  
Load Word  
Address/Word  
Data  
Wait for end of  
Program (T  
Data# Polling  
,
BP  
bit, or Toggle bit  
operation)  
Program  
Completed  
1223 F16.0  
X can be V or V , but no other value  
IL IH  
FIGURE 19: WORD-PROGRAM ALGORITHM  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
23  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
Toggle Bit  
Data# Polling  
Internal Timer  
Program/Erase  
Initiated  
Program/Erase  
Initiated  
Program/Erase  
Initiated  
Read DQ  
7
Read word  
Wait T  
BP  
,
T
T
SCE, SE  
or T  
BE  
Read same  
word  
Is DQ =  
7
No  
true data?  
Program/Erase  
Completed  
Yes  
No  
Does DQ  
match?  
Program/Erase  
Completed  
6
Yes  
Program/Erase  
Completed  
1223 F17.0  
FIGURE 20: WAIT OPTIONS  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
24  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
CFI Query Entry  
Command Sequence  
Sec ID Query Entry  
Command Sequence  
Software Product ID Entry  
Command Sequence  
Load data: XXAAH  
Address: 5555H  
Load data: XXAAH  
Address: 5555H  
Load data: XXAAH  
Address: 5555H  
Load data: XX55H  
Address: 2AAAH  
Load data: XX55H  
Address: 2AAAH  
Load data: XX55H  
Address: 2AAAH  
Load data: XX98H  
Address: 5555H  
Load data: XX88H  
Address: 5555H  
Load data: XX90H  
Address: 5555H  
Wait T  
IDA  
Wait T  
IDA  
Wait T  
IDA  
Read CFI data  
Read Sec ID  
Read Software ID  
X can be V or V , but no other value  
IL  
IH  
1223 F21.0  
FIGURE 21: SOFTWARE ID/CFI ENTRY COMMAND FLOWCHARTS  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
25  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
Software ID Exit/CFI Exit/Sec ID Exit  
Command Sequence  
Load data: XXAAH  
Address: 5555H  
Load data: XXF0H  
Address: XXH  
Load data: XX55H  
Address: 2AAAH  
Wait T  
IDA  
Load data: XXF0H  
Address: 5555H  
Return to normal  
operation  
Wait T  
IDA  
Return to normal  
operation  
X can be V or V , but no other value  
IL IH  
1223 F18.1  
FIGURE 22: SOFTWARE ID/CFI EXIT COMMAND FLOWCHARTS  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
26  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
Chip-Erase  
Sector-Erase  
Block-Erase  
Command Sequence  
Command Sequence  
Command Sequence  
Load data: XXAAH  
Address: 5555H  
Load data: XXAAH  
Address: 5555H  
Load data: XXAAH  
Address: 5555H  
Load data: XX55H  
Address: 2AAAH  
Load data: XX55H  
Address: 2AAAH  
Load data: XX55H  
Address: 2AAAH  
Load data: XX80H  
Address: 5555H  
Load data: XX80H  
Address: 5555H  
Load data: XX80H  
Address: 5555H  
Load data: XXAAH  
Address: 5555H  
Load data: XXAAH  
Address: 5555H  
Load data: XXAAH  
Address: 5555H  
Load data: XX55H  
Address: 2AAAH  
Load data: XX55H  
Address: 2AAAH  
Load data: XX55H  
Address: 2AAAH  
Load data: XX10H  
Address: 5555H  
Load data: XX30H  
Load data: XX50H  
Address: SA  
Address: BA  
X
X
Wait T  
SCE  
Wait T  
SE  
Wait T  
BE  
Chip erased  
to FFFFH  
Sector erased  
to FFFFH  
Block erased  
to FFFFH  
1223 F19.0  
X can be V or V , but no other value  
IL  
IH  
FIGURE 23: ERASE COMMAND SEQUENCE  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
27  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
PRODUCT ORDERING INFORMATION  
SST 39 VF 6402  
-
70  
-
4C  
-
EK  
E
XX XX XXXX - XXX  
-
XX - XXX  
X
Environmental Attribute  
E = non-Pb  
Package Modifier  
K = 48 balls or leads  
Package Type  
E = TSOP (type1, die up, 12mm x 20mm)  
B3 = TFBGA (6mm x 8mm, 0.8mm pitch)  
B1 = TFBGA (8mm x 10mm, 0.8mm pitch)  
Temperature Range  
C = Commercial = 0°C to +70°C  
I = Industrial = -40°C to +85°C  
Minimum Endurance  
4 = 10,000 cycles  
Read Access Speed  
70 = 70 ns  
90 = 90 ns  
Hardware Block Protection  
1 = Bottom Boot-Block  
2 = Top Boot-Block  
Device Density  
160 = 16 Mbit  
320 = 32 Mbit  
640 = 64 Mbit  
Voltage  
V = 2.7-3.6V  
Product Series  
39 = Multi-Purpose Flash  
Valid Combinations for SST39VF1601  
SST39VF1601-70-4C-EK  
SST39VF1601-70-4C-EKE  
SST39VF1601-90-4C-EK  
SST39VF1601-90-4C-EKE  
SST39VF1601-70-4C-B3K  
SST39VF1601-70-4C-B3KE  
SST39VF1601-90-4C-B3K  
SST39VF1601-90-4C-B3KE  
SST39VF1601-70-4I-EK  
SST39VF1601-70-4I-EKE  
SST39VF1601-90-4I-EK  
SST39VF1601-90-4I-EKE  
SST39VF1601-70-4I-B3K  
SST39VF1601-70-4I-B3KE  
SST39VF1601-90-4I-B3K  
SST39VF1601-90-4I-B3KE  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
28  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
Valid Combinations for SST39VF1602  
SST39VF1602-70-4C-EK  
SST39VF1602-70-4C-EKE  
SST39VF1602-90-4C-EK  
SST39VF1602-90-4C-EKE  
SST39VF1602-70-4C-B3K  
SST39VF1602-70-4C-B3KE  
SST39VF1602-90-4C-B3K  
SST39VF1602-90-4C-B3KE  
SST39VF1602-70-4I-EK  
SST39VF1602-70-4I-EKE  
SST39VF1602-90-4I-EK  
SST39VF1602-90-4I-EKE  
SST39VF1602-70-4I-B3K  
SST39VF1602-70-4I-B3KE  
SST39VF1602-90-4I-B3K  
SST39VF1602-90-4I-B3KE  
Valid Combinations for SST39VF3201  
SST39VF3201-70-4C-EK  
SST39VF3201-70-4C-EKE  
SST39VF3201-90-4C-EK  
SST39VF3201-90-4C-EKE  
SST39VF3201-70-4C-B3K  
SST39VF3201-70-4C-B3KE  
SST39VF3201-90-4C-B3K  
SST39VF3201-90-4C-B3KE  
SST39VF3201-70-4I-EK  
SST39VF3201-70-4I-EKE  
SST39VF3201-90-4I-EK  
SST39VF3201-90-4I-EKE  
SST39VF3201-70-4I-B3K  
SST39VF3201-70-4I-B3KE  
SST39VF3201-90-4I-B3K  
SST39VF3201-90-4I-B3KE  
Valid Combinations for SST39VF3202  
SST39VF3202-70-4C-EK  
SST39VF3202-70-4C-EKE  
SST39VF3202-90-4C-EK  
SST39VF3202-90-4C-EKE  
SST39VF3202-70-4C-B3K  
SST39VF3202-70-4C-B3KE  
SST39VF3202-90-4C-B3K  
SST39VF3202-90-4C-B3KE  
SST39VF3202-70-4I-EK  
SST39VF3202-70-4I-EKE  
SST39VF3202-90-4I-EK  
SST39VF3202-90-4I-EKE  
SST39VF3202-70-4I-B3K  
SST39VF3202-70-4I-B3KE  
SST39VF3202-90-4I-B3K  
SST39VF3202-90-4I-B3KE  
Valid Combinations for SST39VF6401  
SST39VF6401-70-4C-EK  
SST39VF6401-70-4C-EKE  
SST39VF6401-90-4C-EK  
SST39VF6401-90-4C-EKE  
SST39VF6401-70-4C-B1K  
SST39VF6401-70-4C-B1KE  
SST39VF6401-90-4C-B1K  
SST39VF6401-90-4C-B1KE  
SST39VF6401-70-4I-EK  
SST39VF6401-70-4I-EKE  
SST39VF6401-90-4I-EK  
SST39VF6401-90-4I-EKE  
SST39VF6401-70-4I-B1K  
SST39VF6401-70-4I-B1KE  
SST39VF6401-90-4I-B1K  
SST39VF6401-90-4I-B1KE  
Valid Combinations for SST39VF6402  
SST39VF6402-70-4C-EK  
SST39VF6402-70-4C-EKE  
SST39VF6402-90-4C-EK  
SST39VF6402-90-4C-EKE  
SST39VF6402-70-4C-B1K  
SST39VF6402-70-4C-B1KE  
SST39VF6402-90-4C-B1K  
SST39VF6402-90-4C-B1KE  
SST39VF6402-70-4I-EK  
SST39VF6402-70-4I-EKE  
SST39VF6402-90-4I-EK  
SST39VF6402-90-4I-EKE  
SST39VF6402-70-4I-B1K  
SST39VF6402-70-4I-B1KE  
SST39VF6402-90-4I-B1K  
SST39VF6402-90-4I-B1KE  
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales  
representative to confirm availability of valid combinations and to determine availability of new combinations.  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
29  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
PACKAGING DIAGRAMS  
1.05  
0.95  
Pin # 1 Identifier  
0.50  
BSC  
0.27  
0.17  
12.20  
11.80  
0.15  
0.05  
18.50  
18.30  
DETAIL  
1.20  
max.  
0.70  
0.50  
20.20  
19.80  
0˚- 5˚  
0.70  
0.50  
Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,  
although some dimensions may be more stringent.  
2. All linear dimensions are in millimeters (max/min).  
3. Coplanarity: 0.1 mm  
1mm  
48-tsop-EK-8  
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.  
48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM  
SST PACKAGE CODE: EK  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
30  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
TOP VIEW  
8.00 0.20  
BOTTOM VIEW  
5.60  
0.80  
0.45 0.05  
(48X)  
6
5
4
3
2
1
6
5
4
3
2
1
4.00  
0.80  
6.00 0.20  
A
B C D E F G H  
H
G F E D C B A  
A1 CORNER  
A1 CORNER  
1.10 0.10  
SIDE VIEW  
0.12  
SEATING PLANE  
1mm  
0.35 0.05  
Note:  
1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.  
2. All linear dimensions are in millimeters.  
3. Coplanarity: 0.12 mm  
4. Ball opening size is 0.38 mm ( 0.05 mm)  
48-tfbga-B3K-6x8-450mic-4  
48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM  
SST PACKAGE CODE: B3K  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
31  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
TOP VIEW  
BOTTOM VIEW  
10.00 0.20  
5.60  
0.80  
6
5
4
3
2
1
6
5
4.00  
4
8.00 0.20  
3
2
1
0.80  
0.45 0.05  
(48X)  
A
B
C
D
E
F
G
H
H G F E D C B A  
A1 CORNER  
A1 CORNER  
1.10 0.10  
SIDE VIEW  
0.12  
1mm  
SEATING PLANE  
0.35 0.05  
Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.  
2. All linear dimensions are in millimeters.  
3. Coplanarity: 0.12 mm  
4. Ball opening size is 0.38 mm ( 0.05 mm)  
48-tfbga-B1K-8x10-450mic-4  
48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 8MM X 10MM  
SST PACKAGE CODE: B1K  
TABLE 18: REVISION HISTORY  
Number  
00  
Description  
Date  
Mar 2003  
Apr 2003  
Jun 2003  
Nov 2003  
Initial release  
01  
Corrected Pin 15 from A20 to NC for SST39VF160x in Figure 1 on page 6  
Changed data sheet title  
02  
03  
2004 Data Book  
Updated the B3K and B1K package diagrams  
Added non-Pb MPNs and removed footnote. (See page 28)  
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036  
www.SuperFlash.com or www.sst.com  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
32  
配单直通车
39VP864D产品参数
型号:39VP864D
生命周期:Obsolete
IHS 制造商:RAYTHEON SEMICONDUCTOR
Reach Compliance Code:unknown
风险等级:5.84
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