4052IC贸易商引脚图技术参数全新原装-中国IC网-芯三七

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产品型号4052的概述

芯片4052的概述 4052是一种双路模拟多路复用器，属于CMOS（互补金属氧化物半导体）技术的系列产品。此芯片广泛应用于数据采集系统、信号调理、电路设计与开发等多个领域，因其高性能和低功耗的特性，受到电子工程师的青睐。4052能够在较宽的电源电压范围内工作，适用于多种不同的应用场景，使其成为多路复用器中一种非常重要的选择。 4052通过控制引脚来选择输入通道，从而实现对多路信号的有效管理。其设计结构使其在选择多条信号传输路径时，能够保证信号的完整性和保真度，具有良好的线性度和较低的交叉干扰。这使得在模拟信号处理中，4052显得尤为重要。芯片4052的详细参数 4052的主要技术参数如下： - 工作电压: 3V至15V（典型值为5V） - 输入电流: 最高10μA - 输出电流: 最高25mA - 通道数: 2 (双路) - 带宽: 可达数百千赫兹（具体视电路配置而定） - 传输延迟...

产品型号4052的Datasheet PDF文件预览

UTC 4052

CMOS

ANALOG MULTIPLEXERS

/DEMULTIPLEXERS

DESCRIPTION

The UTC 4052 analog multiplexers is digitally

–controlled analog switch. The device feature low ON

impedance and very low OFF leakage current. Control

of analog signals up to the complete supply voltage

range can be achieved.

SOP-16

FEATURES

*Triple Diode Protection on Control Inputs

*Switch Function is Break Before Make

*Supply Voltage Range=3.0 Vdc to 18 Vdc

*Analog Voltage Range(VDD-VEE)=3.0 to 18V

*Note:VEE must be≤Vss

*Linearized Transfer Characterisstics

*Low-noise-12nV/√Cycle ,f≥1.0kHz Typical

DIP-16

ABSOLUTE MAXIMUM RATINGS*¹

PARAMETER

SYMBOL

VDD

RATING

-0.5 ~ +18.0

-0.5 ~ V^DD+0.5

UNIT

DC Supply Voltage (Referenced to VEE,Vss≥VEE)

Input or Output Voltage (DC or Transient) (Referenced to

Vin,Vout

Vss for Control Inputs and V^EEfor switch I/O)

Input Current (DC or Transient) per Control Pin

Iin

ISW

±10

±25

Switch Through Current

Power Dissipation *²

700

500

-55 ~ +125

-65 ~ +150

260

DIP-16

SOP-16

Ambient Temperature Range

Tstg

TLEAD

°C

Storage Temperature Range

Lead Temperature (8-Second Soldering)

*1. Maximum Ratings are those values beyond which damage to the device may occur.

*2. Temperature Derating : 7.0 mW/℃ From 65℃ ~ 125℃

UTC UNISONIC TECHNOLOGIES CO., LTD.

QW-R502-013,A

UTC 4052

CMOS

Dual 4-Channel Analog

Multiplexer/Demultiplexer

PIN ASSIGMENT

INHIBIT

VDD

CONTROLS

COMMONS

OUT/IN

SWITCHES

IN/OUT

INH

VDD=PIN16, VSS=PIN8, VEE=PIN7

VEE

Vss

Note: Control Inputs referenced to Vss.

Analog Inputs and Outputs reference to VEE.

VEE must be <Vss.

ELECTRICAL CHARACTERISTICS

-55°C

25°C

125°C

PARAMETER

SYMBOL TEST CONDITIONS

UNIT

MIN MAX MIN TYP^*3MAX MIN MAX

SUPPLY REQUIREMENTS (Voltages Referenced to VEE)

Power Current Per

Range

VDD

3.0

18 3.0

3.0

VDD-3.0≥Vss≥VEE

Quiescent Current

Per Package

IDD

Control Inputs:

Vin=Vss or V^DD,Switch

I/O : VEE≤VI/O≤≤VDD,

and△Vswitch≤500mV ^*4

VDD=5.0V

µA

5.0

0.005

0.010

0.015

5.0

150

300

600

VDD=10V

VDD=15V

Total Supply Current

(Dynamic Plus

Quiescent, Per

Package

I^D(AV)

TA=25℃only (The

channel component,

(Vin-Vout) /Ron, is not

included.)

VDD=5.0V

(0.07µA/kHz)f+I^DD

VDD=10V

Typical (0.20µA/kHz)f+I^DD

(0.36µA/kHz)f+I^DD

VDD=15V

CONTROL INPUTS-INHIBIT, A, B, C (Voltages Referenced to Vss)

Low-Level Input

Voltage

VIL

Ron=per spec,

Ioff=per spec

VDD=5.0V

1.5

3.0

4.0

2.25

4.50

6.75

1.5

3.0

4.0

1.5

3.0

4.0

V^DD=10V

VDD=15V

High-Level Input

Voltage

VIH

Ron=per spec,

Ioff=per spec

VDD=5.0V

3.5

7.0

3.5

7.0

2.75

5.50

8.25

3.5

7.0

VDD=10V

VDD=15V

UTC UNISONIC TECHNOLOGIES CO., LTD.

QW-R502-013,A

UTC 4052

CMOS

-55°C

25°C

125°C

PARAMETER

SYMBOL TEST CONDITIONS

UNIT

µA

MIN MAX MIN TYP^*3MAX MIN MAX

1.0

Input Leakage

Current

Iin

VDD=15V ,Vin=0 or VDD

±0.1

±10^-5±0.1

Input Capacitance

Cin

5.0

7.5

SWITCHES IN/OUT AND COMMONS OUT/IN –X,Y,Z(Voltages Referenced to VEE)

Recommended

V^I/O

Channel On or Off

VDD

300

Vpp

Peak-to-Peak

Voltage Into or Out of

the Switch

Recommended Static

or Dynamic Voltage

Across the Switch *⁴

(Figure 3)

Channel On

600

µV

△V^switch

Output Offset

Voo

Ron

Vin=0V,No Load

Voltage

△V^switch≤500mV *⁴

Vin=VIL or VIH (Control),

and Vin=0 to V^DD(Switch)

VDD=5.0V

ON Resistance

800

400

220

250

120

1050

500

1200

520

VDD=10V

280

300

VDD=15V

135

△ON Resistance

Between Any Two

Channels in the

△Ron VDD=5.0V

VDD=10V

VDD=15V

Same Package

±1000

±100

Off-Channel Leakage

Current(Figure 8)

Ioff

VDD=15V ,Vin=VIL or VIH

(Control) Channel to

Channel or Any One

Channel

±0.05

Capacitance,

Switch I/O

Capacitance,

Common O/I

Capacitance,

Feedthrough

(Channel Off)

C^I/O

C^O/I

CI/O

Inhibit=VDD

Pins Not Adjacent

Pins Adjacent

0.15

0.47

*3. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential

*performance.

*4. For voltage drops across the switch (△Vswitch) > 600 mV ( > 300 mV at high temperature), excessive V^DD

^*current may be drawn, i.e. the current out of the switch may contain both VDD and switch input components. The

*reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data

*sheet.)

UTC UNISONIC TECHNOLOGIES CO., LTD.

QW-R502-013,A

UTC 4052

CMOS

ELECTRICAL CHARACTERISTICS^*5^(CL = 50 pF, TA = 25℃) (VEE ≤VSS unless otherwise indicated)

TYP^*6

PARAMETER

SYMBOL

t^PLH,tPHL

TEST CONDITIONS

MIN

MAX UNIT

Propagation Delay

Times(Figure 4)

Switch Input to Switch

Output

Propagation Delay

Times(Figure 4)

Inhibit to Output

RL=10kΩ

VDD-VEE= 5.0, tPLH,tPHL=(0.17 ns/pF) CL+21.5 ns

VDD-VEE=10, tPLH,tPHL=(0.08 ns/pF) CL+8.0 ns

VDD-VEE=15, tPLH,tPHL=(0.06 ns/pF) CL+7.0 ns

t^PHZ,tPLZ

t^PZH,tPZL

RL=10kΩ,VEE=Vss

Output”1” or “0” to High Impedance, or

High Impedance to”1” or “0” Level

V^DD-VEE= 5.0

300

155

125

600

310

250

VDD-VEE=10

VDD-VEE=15

Propagation Delay

Times(Figure 4)

t^PLN,tPHL

RL=10kΩ,VEE=Vss

V^DD-VEE= 5.0

325

130

650

Control Input to Output

260

VDD-VEE=10

180

VDD-VEE=15

Second Harmonic

Distortion

Bandwidth (Figure 5)

0.07

R^L=10kΩ, f=1kHz, Vin=5Vpp, VDD-VEE=10

R^L=1kΩ, Vin=1/2(VDD-VEE)p-p, CL=50pF,

20 Log (Vout/Vin)=-3dB, VDD-VEE=10

R^L=1kΩ, Vin=1/2(VDD-VEE)p-p, Fin=30MHz,

VDD-VEE=10

MHz

Off Channel

-50

Feedthrough Attenuation

(Figure 5)

Channel Separation

-50

RL=1kΩ, Vin=1/2(VDD-VEE)p-p, fin=3.0MHz,

V^DD-VEE=10

(Figure 6)

Crosstalk ,Control Input

to Common O/I (Figure

R1=1kΩ, RL=10kΩ,

Control tTLH=tTHL=20ns ,Inhibit=Vss), VDD-VEE=10

*5. The formulas given are for the typical characteristics only at 25 ℃.

*6. Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential

*performance.

UTC UNISONIC TECHNOLOGIES CO., LTD.

QW-R502-013,A

UTC 4052

CMOS

VDD

IN/OUT

OUT/IN

VEE

VDD

LEVEL

CONVERTED

CONTROL

OUT/IN

IN/OUT

CONTROL

VEE

Figure 1.Switch Circuit Schematic

VDD

INH

BINARY TO 1-OF-4

DECODER WITH

INHIBIT

LEVEL

TRUTH TABLE

Control Inputs

CONVERTER

Select

ON Switches

Vss

VEE

Inhibit

X0 12

X1 14

X2 15

None

* X=Don't Care

Figure 2. Functional Diagram

TEST CIRCUITS

UTC UNISONIC TECHNOLOGIES CO., LTD.

QW-R502-013,A

UTC 4052

CMOS

ON SWITCH

LOAD

PULSE

GENERATOR

CONTROL

SECTION

OF IC

Vout

INH

SOURCE

VDD

VEE

VDD

Figure 4. Propagation Delay Times, Control and Inhibit to Output

Figure 3.→△V Across Switch

A,B,and C inputs used to tum ON or OFF

the switch under tes.

Vout

CL=50pF

OFF

Vout

INH

Vss

CL=50pF

Vin

VDD

VEE

VDD

VEE

Figure 6. Channel Separation

Figure 5. Bandwidth and Off-Channe Feedthrough Attenuation

(Adjacent Channels Used For Setup)

UTC UNISONIC TECHNOLOGIES CO., LTD.

QW-R502-013,A

UTC 4052

CMOS

OFF CHANNEL UNDER TEST

VDD

VEE

OTHER

CONTROL

SECTION

OF IC

CHANNEL(S)

Vout

CL=50pF

VEE

INH

VDD

VEE

COMMON

VDD

Figure 7. Crosstalk,Control Input to Common O/I

VDD

Figure 8. Off Channel Leakage

KEITHLEY 160

DIGITAL

MULTIMETER

10K

1kΩ

RANGE

X-Y

PLOTTER

VDD

VEE=VSS

Figure 9. Channel Resistance(RON) Test Circuit

TYPICAL RESISTANCE CHARACTERISTIS

350

300

250

350

300

250

200

150

100

200

TA=125℃

150

100

TA=125℃

25℃

-55℃

25℃

-55℃

-6.0

6.0

-6.0

6.0

0.2 4.0 8.0 10

-10 -8.0

-4.0 -2.0

-10 -8.0

-4.0 -2.0

0.2 4.0

8.0 10

Vin,INPUT VOLTAGE (VOLTS)

Figure11.VDD=5.0V,VEE=-5.0V

Vin,INPUT VOLTAGE (VOLTS)

Figure10.VDD=7.5V,VEE=-7.5V

UTC UNISONIC TECHNOLOGIES CO., LTD.

QW-R502-013,A

UTC 4052

CMOS

700

600

350

300

TA=25℃

500

400

250

200

VDD=2.5V

300

200

150

100

5.0V

TA=125℃

7.5V

25℃

100

-55℃

-6.0

6.0

-10

-8.0

-4.0 -2.0

Vin, INPUT VOLTAGE (VOLTS)

Figure13 Comparison at 25℃,VDD=-VEE

0.2

4.0

8.0 10

-6.0

6.0

-10

-8.0

-4.0 -2.0

0.2

4.0

8.0 10

Vin,INPUT VOLTAGE (VOLTS)

Figure12.VDD=2.5V,VEE=-2.5V

Figure A illustrates use of the on–chip level converter detailed in Figures 2. The 0 ~ 5 V Digital Control

signal is used to directly control a 9 Vp–p analog signal.

The digital control logic levels are determined by VDD and VSS. The VDD voltage is the logic high voltage; the VSS

voltage is logic low. For the example, V^DD= + 5 V = logic high at the control inputs; VSS = GND = 0 V = logic low.

The maximum analog signal level is determined by VDD and VEE. The VDD voltage determines the maximum

recommended peak above VSS. The VEE voltage determines the maximum swing below VSS. For the example, VDD –

VSS = 5 V maximum swing above VSS; VSS – VEE = 5 V maximum swing below VSS. The example shows a ± 4.5 V

signal which allows a 1/2 volt margin at each peak. If voltage transients above V^DDand/or below VEE are anticipated

on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small

signal types able to absorb the maximum anticipated current surges during clipping.

The absolute maximum potential difference between VDD and VEE is 18.0 V. Most parameters are specified up to

15 V which is the recommended maximum difference between V^DDand VEE.

Balanced supplies are not required. However, VSS must be greater than or equal to VEE. For example, VDD = + 10

V, VSS = + 5 V, and VEE – 3 V is acceptable. See the Table below.

+5V

-5V

VEE

VDD

Vss

+4.5V

+5V

9 Vp-p

SWITCH

I/O

9 Vp-p

ANALOG SIGNAL

COMMON

O/I

ANALOG SIGNAL

GND

-4.5V

4052

EXTERNAL

CMOS

DIGITAL

0 ~ 5V DIGITAL

CIRCUITRY

INHIBIT,

A,B,C

CONTROL SIGNALS

Figure A. Application Example

UTC UNISONIC TECHNOLOGIES CO., LTD.

QW-R502-013,A

UTC 4052

CMOS

VDD

ANALOG

I/O

COMMON

O/I

VEE

Figure B.External Germanium or Schottky Clipping Diodes

POSSIBLE SUPPLY CONNECTIONS

CONTROL INPUTS

MAXIMUM ANALOG

SIGNAL RANGE IN

VOLTS

VDD

VSS

VEE

LOGIC HIGH/LOGIC LOW

IN VOLTS

IN VOITS

IN VOLTS

+8/0

-8

-12

+8 ~ -8=16Vp-p

+5 ~–12=17Vp-p

+5 ~ 0=5Vp-p

+5/0

-5

+5/0

+5 ~ -5=10Vp-p

+10 ~ –5=15Vp-p

+10

-5

+10/+5

UTC UNISONIC TECHNOLOGIES CO., LTD.

QW-R502-013,A

配单直通车

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4052-D16-T产品参数

型号:	4052-D16-T
生命周期：	Active
IHS 制造商：	UNISONIC TECHNOLOGIES CO LTD
零件包装代码：	DIP
包装说明：	DIP,
针数：	16
Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01
风险等级：	5.56
Is Samacsys：	N
模拟集成电路 - 其他类型：	DIFFERENTIAL MULTIPLEXER
JESD-30 代码：	R-XDIP-T16
JESD-609代码：	e0
长度：	19.3 mm
信道数量：	4
功能数量：	2
端子数量：	16
通态电阻匹配规范：	70 Ω
最大通态电阻 (Ron)：	1050 Ω
最高工作温度：	125 °C
最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED
封装代码：	DIP
封装形状：	RECTANGULAR
封装形式：	IN-LINE
认证状态：	Not Qualified
座面最大高度：	4.31 mm
最大供电电压 (Vsup)：	18 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	5 V
表面贴装：	NO
最长断开时间：	600 ns
最长接通时间：	600 ns
技术：	CMOS
温度等级：	AUTOMOTIVE
端子面层：	TIN LEAD
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
宽度：	7.62 mm
Base Number Matches：	1

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