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SSM40N03P

N-CHANNEL ENHANCEMENT-MODE POWER MOSFET

Low gate charge

BV_DSS

R _DS(ON)

I_D

30V

17mΩ

40A

Simple drive requirement

Fast switching

G

D

S

TO-220

Description

D

S

Power MOSFETs from Silicon Standard provide the

designer with the best combination of fast switching,

ruggedized device design, low on-resistance and cost-effectiveness.

G

The TO-220 package is widely preferred for commercial and

industrial applications and suited for low voltage applications such as

DC/DC converters and high efficiency switching circuits.

Absolute Maximum Ratings

Symbol

Parameter

Rating

30

Units

V

V_DS

V_GS

Drain-Source Voltage

Gate-Source Voltage

V

± 20

40

Continuous Drain Current, V_GS@ 10V

I_D@ T_C=25°C

I_D@ T_C=100°C

I_DM

A

Continuous Drain Current, V_GS@ 10V

Pulsed Drain Current¹

30

A

169

50

A

P_D@ T_C=25°C

Total Power Dissipation

W

Linear Derating Factor

0.4

W/°C

°C

T_STG

T_J

Storage Temperature Range

Operating Junction Temperature Range

-55 to 150

Thermal Data

Symbol

Parameter

Value

Unit

Rthj-c

Thermal Resistance Junction-case

Thermal Resistance Junction-ambient

Max.

2.5

62

°C/W

Rthj-a

Rev.2.01 7/01/2004

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SSM40N03P

Electrical Characteristics @ T=25^oC (unless otherwise specified)

j

Symbol

BV_DSS

Parameter

Drain-Source Breakdown Voltage

Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=1mA

Test Conditions

Min. Typ. Max. Units

V_GS=0V, I_D=250uA

30

-

0.037

14

-

V

∆BV_DSS/∆Tj

-

V/°C

mΩ

R_DS(ON)

Static Drain-Source On-Resistance

V_GS=10V, I_D=20A

-

17

V_GS=4.5V, I_D=16A

V_DS=V_GS, I_D=250uA

V_DS=10V, I_D=20A

V_DS=30V, V_GS=0V

V_DS=24V,V_GS=0V

-

1

-

20

-

23

3

mΩ

V

V_GS(th)

g_fs

Gate Threshold Voltage

Forward Transconductance

Drain-Source Leakage Current (T=25^oC)

26

-

S

I_DSS

uA

nA

nC

ns

pF

j

1

Drain-Source Leakage Current (T=150^oC)

-

25

j

I_GSS

Q_g

Gate-Source Leakage

Total Gate Charge²

Gate-Source Charge

Gate-Drain ("Miller") Charge

Turn-on Delay Time²

Rise Time

V =

GS

-

± 20V

±100

I_D=20A

17

3

-

Q_gs

Q_gd

t_d(on)

t_r

V_DS=24V

V_GS=5V

10

7.2

60

22.5

10

800

380

133

V_DS=15V

I_D=20A

t_d(off)

t_f

Turn-off Delay Time

Fall Time

R_G=3.3Ω ,V_GS=10V

R_D=0.75Ω

V_GS=0V

-

C_iss

C_oss

C_rss

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

V_DS=25V

f=1.0MHz

Source-Drain Diode

Symbol

Parameter

Test Conditions

Min. Typ. Max. Units

A

V

I_S

Continuous Source Current ( Body Diode )

Pulsed Source Current ( Body Diode )¹

Forward On Voltage²

V_D=V_G=0V , V_S=1.3V

-

40

169

1.3

I_SM

V_SD

T_j=25°C, I_S=40A, V_GS=0V

-

Notes:

1.Pulse width limited by safe operating area.

2.Pulse width <300us , duty cycle <2%.

Rev.2.01 7/01/2004

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2 of 6

SSM40N03P

150

100

50

T _C=25 ^oC

V _G=10V

V _G=8.0V

V _G=10V

T _C=150 ^oC

150

100

50

V

_G=8.0V

V

_G=6.0V

V

_G=6.0V

V

_G=4.0V

_G=3.0V

V _G=4.0V

V _G=3.0V

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

V _DS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

Fig 2. Typical Output Characteristics

1.80

1.60

1.40

1.20

1.00

0.80

0.60

28

26

24

22

20

18

16

14

12

I _D= 2 0A

I _D=20A

V _G=10V

T _C=25 ^oC

Ω

-50

0

50

100

150

3

4

5

6

7

8

9

10

11

T _j, Junction Temperature ( ^oC)

V _GS(V)

Fig 3. On-Resistance v.s. Gate Voltage

Fig 4. Normalized On-Resistance

vs. Junction Temperature

Rev.2.01 7/01/2004

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3 of 6

SSM40N03P

50

45

40

35

30

25

20

15

10

5

60

50

40

30

20

10

0

50

100

150

25

50

75

100

125

150

T _c,Case Temperature ( ^oC)

T _c, Case Temperature ( ^oC)

Fig 5. Maximum Drain Current vs.

Case Temperature

Fig 6. Typical Power Dissipation

1

1000

DUTY=0.5

0.2

100

10

1

10us

0.1

0.05

100us

1ms

P_DM

0.02

SINGLE PULSE

t

0.01

T

Duty factor = t/T

10ms

Peak T_j= P_DMx R_thjc+ T_C

T _c=25 ^oC

100ms

Single Pulse

0.01

0.00001

0.0001

0.001

0.01

0.1

1

10

100

V _DS(V)

t , Pulse Width (s)

Fig 7. Maximum Safe Operating Area

Fig 8. Effective Transient Thermal Impedance

Rev.2.01 7/01/2004

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4 of 6

SSM40N03P

f=1.0MHz

16

14

12

10

8

10000

1000

100

Id=20A

V

_D=16V

V _D=20V

V _D=24V

Ciss

6

Coss

4

2

Crss

0

5

10

15

20

25

30

35

40

1

5

9

13

17

21

25

29

Q _G, Total Gate Charge (nC)

V _DS(V)

Fig 9. Gate Charge Characteristics

Fig 10. Typical Capacitance Characteristics

3

100

T _j= 150 ^oC

10

2

1

0

T _j= 25 ^oC

1

0.1

0.01

0.1

0.3

0.5

0.7

0.9

1.1

1.3

1.5

-50

0

50

100

150

T _j, Junction Temperature ( ^oC )

V _SD(V)

Fig 11. Forward Characteristic of

Reverse Diode

Fig 12. Gate Threshold Voltage vs.

Junction Temperature

Rev.2.01 7/01/2004

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5 of 6

SSM40N03P

V_DS

R_D

90%

V_DS

TO THE

OSCILLOSCOPE

D

S

0.5x RATED V_DS

R_G

G

10%

V_GS

+

-

10V

V_GS

t_d(off)

t_d(on)t_r

t_f

Fig 13. Switching Time Circuit

Fig 14. Switching Time Waveform

V_G

5V

V_DS

Q_G

TO THE

OSCILLOSCOPE

D

S

0.8 x RATED V_DS

Q_GD

Q_GS

G

V_GS

+

1~ 3 mA

I_G

-

I_D

Q

Charge

Fig 15. Gate Charge Circuit

Fig 16. Gate Charge Waveform

Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no

guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no

responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its

use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including

without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to

the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of

Silicon Standard Corporation or any third parties.

Rev.2.01 7/01/2004

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