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IS41C16257
IS41LV16257
ISSI
FUNCTIONAL DESCRIPTION
TheIS41C16257andtheIS41LV16257areCMOSDRAMs
optimizedforhigh-speedbandwidth,low-powerapplications.
During READ or WRITE cycles, each bit is uniquely
addressed through the 18 address bits. These are entered
nine bits (A0-A8) at a time. The row address is latched by
the Row Address Strobe (RAS). The column address is
latched by the Column Address Strobe (CAS). RASis used
to latch the first nine bits and CASis used to latch the latter
nine bits.
on the timing relationships between these parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
beforethefallingedgeof CASorWE, whicheveroccurslast.
Refresh Cycle
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory:
The IS41C16257 and the IS41LV16257 has two CAS
controls, LCAS and UCAS. The LCAS and UCAS inputs
internally generate a CAS signal functioning in an identical
manner to the single CAS input on the other 256K x 16
DRAMs. The key difference is that each CAS controls its
corresponding I/O tristate logic (in conjunction with OEand
1. By clocking each of the 512 row addresses (A0 through
A8) with RAS at least once every 8 ms. Any read, write,
read-modify-write or RAS-only cycle refreshes the ad-
dressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RASrefresh is activated by the falling edge of RAS, while
holding CASLOW. In CAS-before-RASrefresh cycle, an
internal9-bitcounterprovidestherowaddressesandthe
external address inputs are ignored.
WE and RAS). LCAS controls
controls I/O8 - I/O15.
I/O0 - I/O7 and UCAS
The IS41C16257 and the IS41LV16257 CAS function is
determined by the first CAS (LCAS or UCAS) transitioning
LOW and the last transitioning back HIGH. The two CAS
controls give the IS41C16257 both BYTE READ and BYTE
WRITE cycle capabilities.
CAS-before-RASisarefresh-onlymodeandnodataaccess
or device selection is allowed. Thus, the output remains in
the High-Z state during the cycle.
Power-On
Memory Cycle
After application of the VCC supply, an initial pause of
200µsisrequiredfollowedbyaminimumofeightinitialization
cycles (any combination of cycles containing a RASsignal).
A memory cycle is initiated by bringing RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensure proper device operation and data integrity any
memory cycle, once initiated, must not be ended or aborted
before the minimum tRAS time has expired. A new cycle
must not be initiated until the minimum precharge time tRP,
tCP has elapsed.
Duringpower-on,itisrecommendedthatRAStrackwithVCC
or be held at a valid VIH to avoid current surges.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WEHIGH. The column
address must be held for a minimum time specified by tAR.
Data Out becomes valid only when tRAC, tAA, tCAC and tOEA
are all satisfied. As a result, the access time is dependent
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Integrated Silicon Solution, Inc. — 1-800-379-4774
DR004-1B
05/24/99