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产品型号41C16257的Datasheet PDF文件预览

IS41C16257  
IS41LV16257  
256K x 16 (4-MBIT) DYNAMIC RAM  
WITH FAST PAGE MODE  
®
ISSI  
MAY 1999  
DESCRIPTION  
FEATURES  
The ISSI IS41C16257 and the IS41LV16257 are 262,144  
x16-bithigh-performanceCMOSDynamicRandomAccess  
Memories. Fast Page Mode allows 512 random accesses  
within a single row with access cycle time as short as 12 ns  
per 16-bit word. The Byte Write control, of upper and lower  
byte, makes these devices ideal for use in 16- and 32-bit  
wide data bus systems.  
• Fast access and cycle time  
• TTL compatible inputs and outputs  
• Refresh Interval: 512 cycles/8 ms  
Refresh Mode: RAS-Only, CAS-before-RAS (CBR),  
and Hidden  
• JEDEC standard pinout  
ThesefeaturesmaketheIS41C16257andtheIS41LV16257  
ideally suited for high band-width graphics, digital signal  
processing, high-performance computing systems, and  
peripheral applications.  
• Single power supply:  
-- 5V ± 10% (IS41C16257)  
-- 3.3V ± 10% (IS41LV16257)  
• Byte Write and Byte Read operation via two CAS  
• Industrial temperature available  
The IS41C16257 and the IS41LV16257 are packaged in a  
40-pin, 400-mil SOJ and TSOP (Type II).  
KEY TIMING PARAMETERS  
Parameter  
-35  
35  
10  
18  
12  
60  
-60  
60  
Unit  
ns  
Max. RAS Access Time (tRAC)  
Max. CAS Access Time (tCAC)  
Max. Column Address Access Time (tAA)  
Min. Fast Page Mode Cycle Time (tPC)  
Min. Read/Write Cycle Time (tRC)  
15  
ns  
30  
ns  
25  
ns  
110  
ns  
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which  
may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
DR004-1B  
05/24/99  
1
®
IS41C16257  
IS41LV16257  
ISSI  
FUNCTIONAL BLOCK DIAGRAM  
OE  
WE  
WE  
CONTROL  
LOGICS  
OE  
CONTROL  
LOGIC  
CAS  
CLOCK  
GENERATOR  
LCAS  
UCAS  
CAS  
WE  
DATA I/O BUS  
RAS  
CLOCK  
RAS  
GENERATOR  
COLUMN DECODERS  
SENSE AMPLIFIERS  
REFRESH  
COUNTER  
I/O0-I/O15  
MEMORY ARRAY  
262,144 x 16  
ADDRESS  
BUFFERS  
A0-A8  
PIN CONFIGURATIONS  
40-Pin TSOP (Type II)  
PIN DESCRIPTIONS  
40-Pin SOJ  
A0-A8  
I/O0-I/O15  
WE  
Address Inputs  
Data Inputs/Outputs  
VCC  
I/O0  
I/O1  
I/O2  
I/O3  
VCC  
I/O4  
I/O5  
I/O6  
I/O7  
1
2
3
4
5
6
7
8
9
10  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
GND  
I/O15  
I/O14  
I/O13  
I/O12  
GND  
I/O11  
I/O10  
I/O9  
VCC  
I/O0  
I/O1  
I/O2  
I/O3  
VCC  
I/O4  
I/O5  
I/O6  
I/O7  
NC  
1
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
GND  
I/O15  
I/O14  
I/O13  
I/O12  
GND  
I/O11  
I/O10  
I/O9  
I/O8  
NC  
Write Enable  
2
3
OE  
Output Enable  
4
RAS  
Row Address Strobe  
5
6
UCAS  
Upper Column Address  
Strobe  
7
8
LCAS  
Lower Column Address  
Strobe  
I/O8  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
Vcc  
GND  
NC  
Power  
NC  
NC  
WE  
RAS  
NC  
A0  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
NC  
NC  
LCAS  
UCAS  
OE  
LCAS  
UCAS  
OE  
Ground  
WE  
RAS  
NC  
No Connection  
A8  
A8  
A0  
A7  
A7  
A1  
A6  
A1  
A6  
A2  
A5  
A2  
A5  
A3  
A4  
A3  
A4  
VCC  
GND  
VCC  
GND  
2
Integrated Silicon Solution, Inc. — 1-800-379-4774  
DR004-1B  
05/24/99  
®
IS41C16257  
IS41LV16257  
ISSI  
TRUTH TABLE  
Function  
RAS  
H
LCAS UCAS  
WE  
X
OE  
X
Address tR/tC I/O  
Standby  
H
L
L
H
L
X
High-Z  
Read: Word  
Read: Lower Byte  
L
H
L
ROW/COL  
ROW/COL  
DOUT  
L
H
H
L
Lower Byte, DOUT  
Upper Byte, High-Z  
Read: Upper Byte  
L
H
L
H
L
ROW/COL  
Lower Byte, High-Z  
Upper Byte, DOUT  
Write: Word (Early Write)  
L
L
L
L
L
L
L
X
X
ROW/COL  
ROW/COL  
DIN  
Write: Lower Byte (Early Write)  
H
Lower Byte, DIN  
Upper Byte, High-Z  
Write: Upper Byte (Early Write)  
L
L
H
L
L
L
L
X
ROW/COL  
ROW/COL  
Lower Byte, High-Z  
Upper Byte, DIN  
Read-Write(1,2)  
HL  
LH  
DOUT, DIN  
Hidden Refresh2)  
Read LHL  
Write LHL  
L
L
L
L
H
L
L
X
ROW/COL  
ROW/COL  
DOUT  
DOUT  
RAS-Only Refresh  
CBR Refresh(3)  
L
H
L
H
L
X
X
X
X
ROW/NA  
X
High-Z  
High-Z  
HL  
Notes:  
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).  
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).  
3. At least one of the two CAS signals must be active (LCAS or UCAS).  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
DR004-1B  
05/24/99  
3
®
IS41C16257  
IS41LV16257  
ISSI  
FUNCTIONAL DESCRIPTION  
TheIS41C16257andtheIS41LV16257areCMOSDRAMs  
optimizedforhigh-speedbandwidth,low-powerapplications.  
During READ or WRITE cycles, each bit is uniquely  
addressed through the 18 address bits. These are entered  
nine bits (A0-A8) at a time. The row address is latched by  
the Row Address Strobe (RAS). The column address is  
latched by the Column Address Strobe (CAS). RASis used  
to latch the first nine bits and CASis used to latch the latter  
nine bits.  
on the timing relationships between these parameters.  
Write Cycle  
A write cycle is initiated by the falling edge of CAS and WE,  
whichever occurs last. The input data must be valid at or  
beforethefallingedgeof CASorWE, whicheveroccurslast.  
Refresh Cycle  
To retain data, 512 refresh cycles are required in each  
8 ms period. There are two ways to refresh the memory:  
The IS41C16257 and the IS41LV16257 has two CAS  
controls, LCAS and UCAS. The LCAS and UCAS inputs  
internally generate a CAS signal functioning in an identical  
manner to the single CAS input on the other 256K x 16  
DRAMs. The key difference is that each CAS controls its  
corresponding I/O tristate logic (in conjunction with OEand  
1. By clocking each of the 512 row addresses (A0 through  
A8) with RAS at least once every 8 ms. Any read, write,  
read-modify-write or RAS-only cycle refreshes the ad-  
dressed row.  
2. Using a CAS-before-RAS refresh cycle. CAS-before-  
RASrefresh is activated by the falling edge of RAS, while  
holding CASLOW. In CAS-before-RASrefresh cycle, an  
internal9-bitcounterprovidestherowaddressesandthe  
external address inputs are ignored.  
WE and RAS). LCAS controls  
controls I/O8 - I/O15.  
I/O0 - I/O7 and UCAS  
The IS41C16257 and the IS41LV16257 CAS function is  
determined by the first CAS (LCAS or UCAS) transitioning  
LOW and the last transitioning back HIGH. The two CAS  
controls give the IS41C16257 both BYTE READ and BYTE  
WRITE cycle capabilities.  
CAS-before-RASisarefresh-onlymodeandnodataaccess  
or device selection is allowed. Thus, the output remains in  
the High-Z state during the cycle.  
Power-On  
Memory Cycle  
After application of the VCC supply, an initial pause of  
200µsisrequiredfollowedbyaminimumofeightinitialization  
cycles (any combination of cycles containing a RASsignal).  
A memory cycle is initiated by bringing RAS LOW and it is  
terminated by returning both RAS and CAS HIGH. To  
ensure proper device operation and data integrity any  
memory cycle, once initiated, must not be ended or aborted  
before the minimum tRAS time has expired. A new cycle  
must not be initiated until the minimum precharge time tRP,  
tCP has elapsed.  
Duringpower-on,itisrecommendedthatRAStrackwithVCC  
or be held at a valid VIH to avoid current surges.  
Read Cycle  
A read cycle is initiated by the falling edge of CAS or OE,  
whichever occurs last, while holding WEHIGH. The column  
address must be held for a minimum time specified by tAR.  
Data Out becomes valid only when tRAC, tAA, tCAC and tOEA  
are all satisfied. As a result, the access time is dependent  
4
Integrated Silicon Solution, Inc. — 1-800-379-4774  
DR004-1B  
05/24/99  
®
IS41C16257  
IS41LV16257  
ISSI  
ABSOLUTE MAXIMUM RATINGS(1)  
Symbol Parameters  
Rating  
Unit  
VT  
Voltage on Any Pin Relative to GND  
5V  
3.3V  
–1.0 to +7.0  
–0.5 t0 +4.6  
V
VCC  
Supply Voltage  
5V  
3.3V  
–1.0 to +7.0  
–0.5 t0 +4.6  
V
IOUT  
PD  
Output Current  
50  
1
mA  
W
Power Dissipation  
Operation Temperature  
TA  
Com.  
Ind.  
0 to 70  
–40 to +85  
°C  
TSTG  
Storage Temperature  
–55 to +125  
°C  
Note:  
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation of the  
device at these or any other conditions above those indicated in the operational sections of  
this specification is not implied. Exposure to absolute maximum rating conditions for  
extended periods may affect reliability.  
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND)  
Symbol  
Parameter  
Voltage  
Min.  
Typ.  
Max.  
Unit  
VCC  
VCC  
VIH  
VIH  
VIL  
Supply Voltage  
5V  
3.3V  
5V  
4.5  
3.0  
5.0  
3.3  
5.5  
3.6  
V
V
Supply Voltage  
Input High Voltage  
Input High Voltage  
Input Low Voltage  
Input Low Voltage  
Ambient Temperature  
2.4  
VCC + 1.0  
VCC + 0.3  
0.8  
V
3.3V  
5V  
2.0  
V
–1.0  
–0.3  
V
VIL  
3.3  
0.8  
V
TA  
Com.  
Ind.  
0
–40  
70  
85  
°C  
CAPACITANCE(1,2)  
Symbol  
Parameter  
Input Capacitance: A0-A8  
Max.  
Unit  
CIN1  
CIN2  
CIO  
5
7
7
pF  
pF  
pF  
Input Capacitance: RAS, UCAS, LCAS, WE, OE  
Data Input/Output Capacitance: I/O0-I/O15  
Notes:  
1. Tested initially and after any design or process changes that may affect these parameters.  
2. Test conditions: TA = 25°C, f = 1 MHz, VCC = 5.0V + 10% or Vcc=3.3V ± 10%.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
DR004-1B  
05/24/99  
5
®
IS41C16257  
IS41LV16257  
ISSI  
ELECTRICAL CHARACTERISTICS(1) (Recommended Operation Conditions unless otherwise noted.)  
Symbol Parameter  
Test Condition  
Speed Min. Max.  
Unit  
IIL  
Input Leakage Current  
Any input 0V < VIN < Vcc  
Other inputs not under test = 0V  
–10  
10  
10  
µA  
IIO  
Output Leakage Current  
Output is disabled (Hi-Z)  
0V < VOUT < Vcc  
–10  
µA  
VOH  
VOL  
Output High Voltage Level  
Output Low Voltage Level  
IOH = –2.5 mA  
IOL = 2.1 mA  
2.4  
V
V
0.4  
ICC1  
Stand-by Current: TTL  
RAS, LCAS, UCAS VIH  
Com. 5V  
Ind. 5V  
2
3
mA  
ICC1  
Stand-by Current: TTL  
RAS, LCAS, UCAS VIH  
Com. 3.3V  
Ind. 3.3V  
1
2
mA  
ICC2  
ICC2  
ICC3  
Stand-by Current: CMOS  
Stand-by Current: CMOS  
RAS, LCAS, UCAS VCC – 0.2V  
RAS, LCAS, UCAS VCC – 0.2V  
5V  
2
1
mA  
mA  
mA  
3.3V  
Operating Current:  
RAS, LCAS, UCAS,  
Address Cycling, tRC = tRC (min.)  
-35  
-60  
230  
170  
Random Read/Write(2,3,4)  
Average Power Supply Current  
ICC4  
Operating Current:  
RAS = VIL, LCAS, UCAS,  
Cycling tPC = tPC (min.)  
-35  
-60  
220  
160  
mA  
mA  
mA  
Fast Page Mode(2,3,4)  
Average Power Supply Current  
ICC5  
Refresh Current:  
RAS Cycling, LCAS, UCAS VIH  
tRC = tRC (min.)  
-35  
-60  
230  
170  
RAS-Only(2,3)  
Average Power Supply Current  
ICC6  
Refresh Current:  
RAS, LCAS, UCAS Cycling  
tRC = tRC (min.)  
-35  
-60  
230  
170  
CBR(2,3,5)  
Average Power Supply Current  
Notes:  
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device  
operation is assured.The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.  
2. Dependent on cycle rates.  
3. Specified values are obtained with minimum cycle time and the output open.  
4. Column-address is changed once each fast page cycle.  
5. Enables on-chip refresh and address counters.  
6
Integrated Silicon Solution, Inc. — 1-800-379-4774  
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05/24/99  
®
IS41C16257  
IS41LV16257  
ISSI  
AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless  
otherwise noted.)  
-35  
-60  
Symbol Parameter  
Min. Max.  
Min. Max.  
Units  
tRC  
Random READ or WRITE Cycle Time  
60  
35  
20  
6
35  
10  
18  
10K  
110  
60  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(6, 7)  
tRAC  
tCAC  
tAA  
Access Time from RAS  
Access Time from CAS(6, 8, 15)  
Access Time from Column-Address(6)  
RAS Pulse Width  
15  
30  
tRAS  
tRP  
60  
40  
10  
10  
60  
20  
— 0  
10  
0
10K  
RAS Precharge Time  
CAS Pulse Width(26)  
tCAS  
tCP  
10K  
10K  
CAS Precharge Time(9, 25)  
CAS Hold Time (21)  
RAS to CAS Delay Time(10, 20)  
Row-Address Setup Time  
Row-Address Hold Time  
Column-Address Setup Time(20)  
Column-Address Hold Time(20)  
5
tCSH  
tRCD  
tASR  
tRAH  
tASC  
tCAH  
tAR  
35  
11  
0
28  
45  
— ns  
6
ns  
ns  
ns  
ns  
0
6
10  
40  
Column-Address Hold Time  
(referenced to RAS)  
30  
tRAD  
tRAL  
tRPC  
tRSH  
tCLZ  
tCRP  
tOD  
RAS to Column-Address Delay Time(11)  
Column-Address to RAS Lead Time  
RAS to CAS Precharge Time  
RAS Hold Time(27)  
CAS to Output in Low-Z(15, 29)  
CAS to RAS Precharge Time(21)  
Output Disable Time(19, 28, 29)  
Output Enable Time(15, 16)  
12  
18  
0
20  
15  
10  
15  
30  
0
30  
15  
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
8
15  
3
3
5
5
3
3
tOE  
10  
10  
5
10  
10  
5
tOEHC  
tOEP  
tOES  
tRCS  
tRRH  
OE HIGH Hold Time from CAS HIGH  
OE HIGH Pulse Width  
OE LOW to CAS HIGH Setup Time  
Read Command Setup Time(17, 20)  
0
0
Read Command Hold Time  
(referenced to RAS)(12)  
0
0
tRCH  
Read Command Hold Time  
(referenced to CAS)(12, 17, 21)  
0
0
ns  
tWCH  
Write Command Hold Time(17, 27)  
5
10  
50  
ns  
ns  
tWCR  
Write Command Hold Time  
(referenced to RAS)(17)  
30  
tWP  
Write Command Pulse Width(17)  
5
10  
8
10  
10  
15  
15  
0
ns  
ns  
ns  
ns  
ns  
ns  
tWPZ  
tRWL  
tCWL  
tWCS  
tDHR  
WE Pulse Widths to Disable Outputs  
Write Command to RAS Lead Time(17)  
Write Command to CAS Lead Time(17, 21)  
Write Command Setup Time(14, 17, 20)  
Data-in Hold Time (referenced to RAS)  
8
0
30  
40  
(Continued)  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
DR004-1B  
05/24/99  
7
®
IS41C16257  
IS41LV16257  
ISSI  
AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless  
otherwise noted.)  
-35  
-60  
Symbol Parameter  
Min. Max.  
Min. Max.  
Units  
tACH  
Column-Address Setup Time to CAS  
15  
15  
ns  
Precharge during WRITE Cycle  
tOEH  
OE Hold Time from WE during  
READ-MODIFY-WRITE cycle(18)  
8
15  
ns  
tDS  
Data-In Setup Time(15, 22)  
Data-In Hold Time(15, 22)  
0
6
0
ns  
ns  
ns  
ns  
tDH  
10  
tRWC  
tRWD  
READ-MODIFY-WRITE Cycle Time  
80  
45  
140  
80  
RAS to WE Delay Time during  
READ-MODIFY-WRITE Cycle(14)  
tCWD  
tAWD  
tPC  
CAS to WE Delay Time(14, 20)  
Column-Address to WE Delay Time(14)  
25  
30  
12  
36  
49  
25  
ns  
ns  
ns  
Fast Page Mode READ or WRITE  
Cycle Time(24)  
tRASP  
tCPA  
RAS Pulse Width  
35 100K  
60 100K  
ns  
ns  
ns  
ns  
Access Time from CAS Precharge(15)  
READ-WRITE Cycle Time(24)  
Output Buffer Turn-Off Delay from  
40  
3
21  
15  
56  
3
34  
15  
tPRWC  
tOFF  
(13,15,19, 29)  
CAS or RAS  
tWHZ  
Output Disable Delay from WE  
3
15  
3
15  
ns  
ns  
tCLCH  
Last CAS going LOW to First CAS  
returning HIGH(23)  
10  
10  
tCSR  
tCHR  
tORD  
CAS Setup Time (CBR REFRESH)(30, 20)  
CAS Hold Time (CBR REFRESH)(30, 21)  
8
8
0
10  
10  
0
ns  
ns  
ns  
OE Setup Time prior to RAS during  
HIDDEN REFRESH Cycle  
tREF  
tT  
Refresh Period (512 Cycles)  
Transition Time (Rise or Fall)(2, 3)  
1
8
1
8
ms  
ns  
50  
50  
8
Integrated Silicon Solution, Inc. — 1-800-379-4774  
DR004-1B  
05/24/99  
®
IS41C16257  
IS41LV16257  
ISSI  
Notes:  
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device  
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.  
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and  
VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.  
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH)  
in a monotonic manner.  
4. If CAS and RAS = VIH, data output is High-Z.  
5. If CAS = VIL, data output may contain data from the last valid READ cycle.  
6. Measured with a load equivalent to one TTL gate and 50 pF.  
7. Assumes that tRCD tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by  
the amount that tRCD exceeds the value shown.  
8. Assumes that tRCD tRCD (MAX).  
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the  
data output buffer, CAS and RAS must be pulsed for tCP.  
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD  
is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.  
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD  
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.  
12. Either tRCH or tRRH must be satisfied for a READ cycle.  
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.  
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS tWCS  
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD tRWD  
(MIN), tAWD tAWD (MIN) and tCWD tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from  
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back  
to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.  
15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.  
16. During a READ cycle, if OEis LOW then taken HIGH before CASgoes HIGH, I/O goes open. If OEis tied permanently LOW, a LATE  
WRITE or READ-MODIFY-WRITE is not possible.  
17. Write command is defined as WE going low.  
18. LATEWRITEandREAD-MODIFY-WRITEcyclesmusthavebothtOD andtOEH met(OEHIGHduringWRITEcycle)inordertoensure  
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW  
and OE is taken back to LOW after tOEH is met.  
19. The I/Os are in open during READ cycles once tOD or tOFF occur.  
20. The first χCAS edge to transition LOW.  
21. The last χCAS edge to transition HIGH.  
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-  
MODIFY-WRITE cycles.  
23. Last falling χCAS edge to first rising χCAS edge.  
24. Last rising χCAS edge to next cycle’s last rising χCAS edge.  
25. Last rising χCAS edge to first falling χCAS edge.  
26. Each χCAS must meet minimum pulse width.  
27. Last χCAS to go LOW.  
28. I/Os controlled, regardless UCAS and LCAS.  
29. The 3 ns minimum is a parameter guaranteed by design.  
30. Enables on-chip refresh and address counters.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
DR004-1B  
05/24/99  
9
®
IS41C16257  
IS41LV16257  
ISSI  
FAST-PAGE-MODE READ CYCLE  
t
RC  
t
RAS  
t
RP  
RAS  
t
CSH  
t
RSH  
t
RRH  
t
CRP  
ASR  
t
CAS CLCH  
t
t
RCD  
UCAS/LCAS  
t
AR  
t
RAD  
tRAL  
t
t
RAH  
t
CAH  
t
ASC  
ADDRESS  
WE  
Row  
Column  
Row  
t
RCS  
t
RCH  
t
AA  
t
RAC  
(1)  
OFF  
t
t
CAC  
CLC  
t
Open  
Open  
Valid Data  
I/O  
OE  
t
OE  
tOD  
t
OES  
Don't Care  
Note:  
1. tOFF is referenced from rising edge of CAS.  
10  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
DR004-1B  
05/24/99  
®
IS41C16257  
IS41LV16257  
ISSI  
FAST PAGE MODE READ-MODIFY-WRITE CYCLE  
tRASP  
tRP  
RAS  
tCSH  
tCAS  
tPRWC  
tCAS  
tRSH  
tCAS  
tCRP  
tRCD  
tAR  
tCRP  
tCP  
tCP  
UCAS/LCAS  
ADDRESS  
tCPWD  
tRAL  
tCPWD  
tRAD  
tCAH  
tCAH  
tCAH  
tRAH  
tASR  
tASC  
tASC  
tASC  
Row  
Column  
Column  
Column  
tCWL  
tRWD  
tCWL  
tRWL  
tCWL  
tAWD  
tCWD  
tAWD  
tCWD  
tAWD  
tCWD  
tRCS  
tWP  
tWP  
tWP  
WE  
OE  
tAA  
tAA  
tCAC  
tAA  
tCAC  
tCAC  
tOEA  
tOEA  
tOEA  
tOEZ  
tOEZ  
tOED  
tOEZ  
tOED  
tRAC  
tCLZ  
tOED  
tDH  
tDH  
tDH  
tDS tCLZ  
tDS  
tCLZ  
OUT  
tDS  
I/O0-I/O15  
OUT  
IN  
IN  
IN  
OUT  
Don't Care  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
DR004-1B  
05/24/99  
11  
®
IS41C16257  
IS41LV16257  
ISSI  
FAST-PAGE-MODE EARLY WRITE CYCLE (OE = DON'T CARE)  
t
RC  
t
RAS  
tRP  
RAS  
t
CSH  
t
RSH  
t
CRP  
ASR  
t
CAS CLCH  
t
t
RCD  
UCAS/LCAS  
t
AR  
t
RAD  
t
t
t
RAL  
CAH  
ACH  
t
t
RAH  
t
ASC  
ADDRESS  
Row  
Column  
Row  
t
t
CWL  
RWL  
t
WCR  
t
WCS  
tWCH  
t
WP  
WE  
I/O  
t
DHR  
t
DH  
t
DS  
Valid Data  
Don't Care  
12  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
DR004-1B  
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®
IS41C16257  
IS41LV16257  
ISSI  
FAST-PAGE-MODE READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)  
tRWC  
tRAS  
tRP  
RAS  
tCSH  
tRSH  
tCRP  
tASR  
tCAS tCLCH  
tRCD  
UCAS/LCAS  
tAR  
tRAD  
tRAH  
tRAL  
tACH  
tCAH  
tASC  
ADDRESS  
WE  
Row  
Column  
Row  
tRWD  
tCWL  
tRWL  
tWP  
tRCS  
tCWD  
tAWD  
tAA  
tRAC  
tCAC  
tCLZ  
tDS  
tDH  
Open  
Open  
Valid DOUT  
Valid DIN  
I/O  
OE  
tOD  
tOEH  
tOE  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
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®
IS41C16257  
IS41LV16257  
ISSI  
FAST PAGE MODE EARLY WRITE CYCLE  
tRASP  
tRP  
RAS  
tRHCP  
tRSH  
tCAS  
tCSH  
tCAS  
tPC  
tCAS  
tCRP  
tRCD  
tAR  
tCRP  
tCP  
tCP  
UCAS/LCAS  
ADDRESS  
tRAL  
tRAD  
tCAH  
tCAH  
tCAH  
tRAH  
tASR  
tASC  
tASC  
tASC  
Row  
Column  
Column  
Column  
tCWL  
tWCH  
tCWL  
tWCH  
tCWL  
tWCH  
tWCS  
tWCS  
tWCS  
tWP  
tWP  
tWP  
WE  
OE  
tWCR  
tDHR  
tDS  
tDS  
tDS  
tDH  
tDH  
tDH  
Valid DIN  
Valid DIN  
Valid DIN  
I/O0-I/O15  
Don't Care  
14  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
DR004-1B  
05/24/99  
®
IS41C16257  
IS41LV16257  
ISSI  
AC WAVEFORMS  
READ CYCLE (With WE-Controlled Disable)  
RAS  
tCSH  
tCRP  
tASR  
tRCD  
tCP  
tCAS  
UCAS/LCAS  
tAR  
tRAD  
tRAH  
tCAH  
tRCH  
tASC  
tRCS  
tASC  
ADDRESS  
WE  
Row  
Column  
Column  
tRCS  
tAA  
tRAC  
tCAC  
tCLZ  
tWHZ  
tCLZ  
Open  
Open  
Valid Data  
I/O  
OE  
tOE  
tOD  
Don't Care  
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)  
t
RC  
t
RAS  
tRP  
RAS  
t
CRP  
t
RPC  
UCAS/LCAS  
t
ASR  
tRAH  
ADDRESS  
I/O  
Row  
Row  
Open  
Don't Care  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
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®
IS41C16257  
IS41LV16257  
ISSI  
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)  
t
RP  
t
RAS  
t
RP  
t
RAS  
RAS  
t
CHR  
t
CHR  
t
RPC  
CP  
tRPC  
t
t
CSR  
tCSR  
UCAS/LCAS  
I/O  
Open  
HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)  
t
RAS  
t
RAS  
t
RP  
RAS  
t
CRP  
t
RCD  
t
RSH  
tCHR  
UCAS/LCAS  
t
AR  
t
RAD  
t
RAL  
t
ASR  
t
RAH  
tCAH  
t
ASC  
ADDRESS  
Row  
Column  
t
AA  
t
RAC  
(2)  
t
OFF  
t
CAC  
t
CLZ  
Open  
Open  
Valid Data  
I/O  
OE  
t
OE  
tOD  
t
ORD  
Don't Care  
Notes:  
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.  
2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.  
16  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
DR004-1B  
05/24/99  
®
IS41C16257  
IS41LV16257  
ISSI  
ORDERING INFORMATION  
IS41C16257  
ORDERING INFORMATION  
IS41LV16257  
Commercial Range: 0°C to 70°C  
Commercial Range: 0°C to 70°C  
Speed (ns) Order Part No.  
Package  
Speed (ns) Order Part No.  
Package  
35  
IS41C16257-35K  
IS41C16257-35T  
400-mil SOJ  
400-mil TSOP (Type II)  
35  
IS41LV16257-35K  
IS41LV16257-35T  
400-mil SOJ  
400-mil TSOP (Type II)  
60  
IS41C16257-60K  
IS41C16257-60T  
400-mil SOJ  
400-mil TSOP (Type II)  
60  
IS41LV16257-60K  
IS41LV16257-60T  
400-mil SOJ  
400-mil TSOP (Type II)  
Industrial Range: –40°C to 85°C  
Industrial Range: –40°C to 85°C  
Speed (ns) Order Part No.  
Package  
Speed (ns) Order Part No.  
Package  
35  
IS41C16257-35KI  
IS41C16257-35TI  
400-mil SOJ  
400-mil TSOP (Type II)  
35  
IS41LV16257-35KI  
IS41LV16257-35TI  
400-mil SOJ  
400-mil TSOP (Type II)  
60  
IS41C16257-60KI  
IS41C16257-60TI  
400-mil SOJ  
400-mil TSOP (Type II)  
60  
IS41LV16257-60KI  
IS41LV16257-60TI  
400-mil SOJ  
400-mil TSOP (Type II)  
®
ISSI  
Integrated Silicon Solution, Inc.  
2231 Lawson Lane  
Santa Clara, CA 95054  
Tel: 1-800-379-4774  
Fax: (408) 588-0806  
E-mail: sales@issi.com  
www.issi.com  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
DR004-1B  
05/24/99  
17  
配单直通车
41CTQ030-1产品参数
型号:41CTQ030-1
生命周期:Active
零件包装代码:TO-262AA
包装说明:PLASTIC, TO-262, 3 PIN
针数:3
Reach Compliance Code:unknown
ECCN代码:EAR99
HTS代码:8541.10.00.80
风险等级:5.69
其他特性:FREE WHEELING DIODE, HIGH RELIABILITY
应用:GENERAL PURPOSE
外壳连接:CATHODE
配置:SINGLE
二极管元件材料:SILICON
二极管类型:RECTIFIER DIODE
JEDEC-95代码:TO-262AA
JESD-30 代码:R-PSIP-T3
最大非重复峰值正向电流:360 A
元件数量:1
相数:1
端子数量:3
最高工作温度:150 °C
最低工作温度:-55 °C
最大输出电流:20 A
封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR
封装形式:IN-LINE
认证状态:Not Qualified
最大重复峰值反向电压:30 V
表面贴装:NO
技术:SCHOTTKY
端子形式:THROUGH-HOLE
端子位置:SINGLE
Base Number Matches:1
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