583274-1各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

5833

BiMOS II 32-BIT SERIAL-INPUT,

LATCHED DRIVER

Designed to reduce logic supply current, chip size, and system

cost, the UCN5833A/EP integrated circuits offer high-speed operation

for thermal printers. These devices can also be used to drive multi-

plexed LED displays or incandescent lamps within their 125 mA peak

output current rating. The combination of bipolar and MOS technolo-

gies gives BiMOS II smart power ICs an interface flexibility beyond the

reach of standard buffers and power driver circuits.

UCN5833EP

These 32-bit drivers have bipolar open-collector npn Darlington

outputs, a CMOS data latch for each of the drivers, a 32-bit CMOS

shift register, and CMOS control circuitry. The high-speed CMOS shift

registers and latches allow operation with most microprocessor-based

systems at data input rates above 3.3 MHz. Use of these drivers with

TTL may require input pull-up resistors to ensure an input logic high.

OUT ₂

OUT ₃

OUT ₄

OUT ₅

OUT ₆

OUT ₇

OUT ₈

OUT ₉

OUT₁₀

OUT₁₁

39

38

37

OUT

7

8

31

OUT

30

OUT

29

9

36 OUT

28

10

35

34 OUT

OUT

27

11

12

26

OUT

25

33

32

13

14

OUT

24

The UCN5833A is supplied in a 40-pin dual in-line plastic package

with 0.600" (15.24 mm) row spacing. At an ambient temperature of

+75°C, all outputs of the DlP-packaged device will sustain 50 mA

continuously. For high-density applications, the UCN5833EP is

available. This 44-lead plastic chip carrier (quad pack) is intended

for surface-mounting on solder lands with 0.050" (1.27 mm) centers.

CMOS serial data outputs permit cascading for applications requiring

additional drive lines.

31 OUT

23

15

16

30 OUT

22

OUT

21

29

OUT ₁₂17

SUB

Dwg. No. A-13,049

FEATURES

ABSOLUTE MAXIMUM RATINGS

ꢀ To 3.3 MHz Data Input Rate

at +25°C Free-Air Temperature

ꢀ 30 V Minimum Output Breakdown

ꢀ Darlington Current-Sink Outputs

ꢀ Low-Power CMOS Logic and Latches

Output Voltage, V

. . . . . . . . . . . 30 V

OUT

Logic Supply Voltage, V_DD. . . . . . . 7.0 V

Input Voltage Range,

V

. . . . . . . . . -0.3 V to V + 0.3 V

IN

DD

Continuous Output Current,

(each output) . . . . . . . . . . 125 mA

l

OUT

Package Power Dissipation, P

D

(UCN5833A) . . . . . . . . . . . . . . . 3.5 W*

(UCN5833EP) . . . . . . . . . . . . . . 2.5 W*

Operating Temperature Range,

T . . . . . . . . . . . . . . -20°C to +85°C

A

Storage Temperature Range,

T . . . . . . . . . . . . . -55°C to +150°C

S

Always order by complete part number:

* Derate linearly to 0 W at +150°C.

Part Number

UCN5833A

UCN5833EP

Package

Caution: CMOS devices have input static protection

but are susceptible to damage when exposed to

extremely high static electrical charges.

40-Pin DIP

44-Lead PLCC

5833

BiMOS II 32-BIT

SERIAL-INPUT,

LATCHED DRIVER

UCN5833A

FUNCTIONAL BLOCK DIAGRAM

LOGIC

SUPPLY

LOGIC

CLOCK

1

CLK 40

V_DD

SUPPLY

SERIAL

DATA IN

SERIAL

39

2

3

V_DD

DATA OUT

CLOCK

POWER

GROUND

OUTPUT

ENABLE

38

OE

32-BIT SHIFT REGISTER

LATCHES

SERIAL

DATA IN

SERIAL DATA

OUT

32

37

36

4

5

STROBE

ST

OUT

31

OUT

1

STROBE

LOGIC

GROUND

OUT

30

OUT

2

35

34

6

7

SUB

OUTPUT

ENABLE

OUT

29

OUT

3

MOS

OUT

4

8

33 OUT

28

BIPOLAR

9

32

31

OUT

5

OUT

27

26

10

OUT

6

OUT OUT₂OUT

POWER OUT₃₀OUT OUT

31

32

GROUND

1

3

OUT

7

11

12

30 OUT

25

24

Dwg. No. A-13,057

OUT

8

OUT

29

28

OUT

9

OUT

23

22

21

20

OUT

10

14

15

16

27

26

25

TYPICAL INPUT CIRCUIT

OUT

11

V

DD

OUT

12

OUT

13

OUT

17

18

19

20

24

23

22

21

19

OUT

14

OUT

18

OUT

15

17

IN

OUT

16

LOGIC

GROUND

SUB

Dwg. No. A-13,048

Dwg. No. A-13,050

SUB

TYPICAL OUTPUT DRIVER

OUT

Dwg. No. A-13,051

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

5833

BiMOS II 32-BIT

SERIAL-INPUT,

LATCHED DRIVER

ELECTRICAL CHARACTERISTICS at T_A= +25°C, V_DD= 5 V (unless otherwise noted).

Limits

Max.

Characteristic

Symbol

I_CEX

Test Conditions

V_OUT= 30 V, T_A= 70°C

l_OUT= 50 mA

Min.

—

Units

µA

V

Output Leakage Current

10

1.2

1.7

5.3

+0.8

1.0

-1.0

—

Collector-Emitter

Saturation Voltage

V_CE(SAT)

—

l

_OUT= 100 mA

—

V

Input Voltage

V_IN(1)

V_IN(0)

l_IN(1)

3.5

-0.3

—

V

Input Current

V_IN= 5.0 V

µA

V

l_IN(0)

V_IN= 0 V

—

Serial Output Voltage

Supply Current

V_OUT(1)

V_OUT(0)

l_DD

I_OUT= -200 µA

4.5

—

I_OUT= 200 µA

0.3

1.0

50

V

One output ON, l_OUT= 100 mA

All outputs OFF

—

mA

µA

ns

—

Output Rise Time

Output Fall Time

t_r

t_f

l_OUT= 100 mA, 10% to 90%

l_OUT= 100 mA, 90% to 10%

—

500

—

NOTE: Positive (negative) current is defined as going into (coming out of) the specified device pin.

TRUTH TABLE

Serial

Data Clock

Input Input I

Shift Register Contents

Serial

Data Strobe

Output Input

Latch Contents

Output

Enable

Input

Output Contents

... I

I

...

I

...

I

N-1 N

1

2

3

N-1

N

1

2

3

N-1

N

1

2

3

H

L

H

L

R₁R₂... R_N-2R_N-1

R_N-1

R_N

X

R₁R₂R₃... R_N-1R_N

...

P₁P₂P₃... P_N-1P_N

X

L

R₁R₂R₃... R_N-1R_N

P₁P₂P₃... P_N-1P_N

P_N

H

L

P₁P₂P₃... P_N-1P_N

... H

X

...

X

H

L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State

5833

BiMOS II 32-BIT

SERIAL-INPUT,

LATCHED DRIVER

CLOCK

DATA IN

STROBE

A

D

B

E

F

C

OUTPUT

ENABLE

G

OUT_N

Dwg. No. A-12,276A

TIMING CONDITIONS

(V_DD= 5.0 V, Logic Levels are V_DDand Ground)

A. Minimum Data Active Time Before Clock Pulse

(Data Set-Up Time).......................................................................... 75 ns

B. Minimum Data Active Time After Clock Pulse

(Data Hold Time) ............................................................................. 75 ns

C. Minimum Data Pulse Width ................................................................ 150 ns

D. Minimum Clock Pulse Width............................................................... 150 ns

E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns

F. Minimum Strobe Pulse Width ............................................................. 100 ns

G. Typical Time Between Strobe Activation and

Output Transition ........................................................................... 500 ns

Serial Data present at the input is transferred to the shift register

on the logic “0” to logic “1” transition of the CLOCK input pulse. On

succeeding CLOCK pulses, the registers shift data information towards

the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the

input prior to the rising edge of the CLOCK input waveform.

Information present at any register is transferred to its respective

latch when the STROBE is high (serial-to-parallel conversion). The

latches will continue to accept new data as long as the STROBE is

held high. Applications where the latches are bypassed (STROBE tied

high) will require that the OUTPUT ENABLE input be low during serial

data entry.

When the OUTPUT ENABLE input is low, all of the output buffers

are disabled (OFF) without affecting the information stored in the

latches or shift register. With the OUTPUT ENABLE input high, the

outputs are controlled by the state of the latches.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

5833

BiMOS II 32-BIT

SERIAL-INPUT,

LATCHED DRIVER

UCN5833A

Dimensions in Inches

(controlling dimensions)

0.015

0.008

40

21

0.700

MAX

0.580

0.485

0.600

BSC

1

2

20

0.100

BSC

3

4

0.070

0.005

MIN

2.095

1.980

0.030

0.250

MAX

0.015

MIN

0.200

0.115

0.022

0.014

Dwg. MA-003-40 in

Dimensions in Millimeters

(for reference only)

0.381

0.204

40

21

17.78

MAX

14.73

12.32

15.24

BSC

1

2

20

3

4

0.13

MIN

1.77

2.54

BSC

0.77

53.2

50.3

6.35

MAX

0.39

MIN

5.08

2.93

0.558

0.356

Dwg. MA-003-40 mm

NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.

2. Lead spacing tolerance is non-cumulative.

3. Lead thickness is measured at seating plane or below.

5833

BiMOS II 32-BIT

SERIAL-INPUT,

LATCHED DRIVER

UCN5833EP

Dimensions in Inches

(controlling dimensions)

18

28

29

17

0.032

0.026

0.319

0.291

0.695

0.685

0.021

0.013

0.656

0.650

0.319

INDEX AREA

0.291

0.050

BSC

39

7

44

1

2

40

6

0.020

MIN

0.656

0.650

0.695

0.685

0.180

0.165

Dwg. MA-005-44A in

Dimensions in Millimeters

(for reference only)

28

18

29

17

0.812

0.661

8.10

7.39

17.65

17.40

0.533

0.331

16.662

16.510

8.10

7.39

INDEX AREA

1.27

BSC

39

7

44

1

2

40

6

16.662

16.510

0.51

MIN

4.57

4.20

17.65

17.40

Dwg. MA-005-44A mm

NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.

2. Lead spacing tolerance is non-cumulative.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

5833

BiMOS II 32-BIT

SERIAL-INPUT,

LATCHED DRIVER

The products described here are manufactured under one or more

U.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to

time, such departures from the detail specifications as may be required

to permit improvements in the performance, reliability, or

manufacturability of its products. Before placing an order, the user is

cautioned to verify that the information being relied upon is current.

Allegro products are not authorized for use as critical components

in life-support devices or systems without express written approval.

The information included herein is believed to be accurate and

reliable. However, Allegro MicroSystems, Inc. assumes no responsi-

bility for its use; nor for any infringement of patents or other rights of

third parties which may result from its use.

5833

BiMOS II 32-BIT

SERIAL-INPUT,

LATCHED DRIVER

POWER

INTERFACE DRIVERS

†

Function

Output Ratings*

SERIAL-INPUT LATCHED DRIVERS

Part Number

8-Bit (saturated drivers)

8-Bit

-120 mA

350 mA

75 mA

250 mA

350 mA

100 mA

50 V‡

50 V

80 V

50 V‡

80 V‡

17 V

50 V

50 V‡

50 V

5895

5821

5822

5841

5842

6275

6595

6A595

6B595

8-Bit

8-Bit (constant-current LED driver)

8-Bit (DMOS drivers)

10-Bit (active pull-downs)

-25 mA

75 mA

-25 mA

60 V

17 V

60 V

5810-F and 6809/10

5811 and 6811

6276

12-Bit (active pull-downs)

16-Bit (constant-current LED driver)

20-Bit (active pull-downs)

5812-F and 6812

32-Bit (active pull-downs)

32-Bit

32-Bit (saturated drivers)

-25 mA

100 mA

60 V

30 V

40 V

5818-F and 6818

5833

5832

PARALLEL-INPUT LATCHED DRIVERS

4-Bit

350 mA

50 V‡

5800

8-Bit

-25 mA

350 mA

100 mA

250 mA

60 V

50 V‡

50 V

5815

5801

6B273

6273

8-Bit (DMOS drivers)

SPECIAL-PURPOSE DEVICES

Unipolar Stepper Motor Translator/Driver

Addressable 8-Bit Decoder/DMOS Driver

Addressable 28-Line Decoder/Driver

1.25 A

250 mA

350 mA

100 mA

450 mA

50 V‡

5804

6259

6A259

6B259

6817

50 V

50 V‡

50 V

30 V

*

Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.

Negative current is defined as coming out of (sourcing) the output.

†

‡

Complete part number includes additional characters to indicate operating temperature range and package style.

Internal transient-suppression diodes included for inductive-load protection.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

型号:	583274-1
Brand Name：	AMP
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TE CONNECTIVITY LTD
Reach Compliance Code：	compliant
Factory Lead Time：	12 weeks
风险等级：	1.65
组装件名称：	KEYING ITEM
连接器支架类型：	CONNECTOR ACCESSORY
DIN 符合性：	NO
IEC 符合性：	NO
MIL 符合性：	NO
材料：	NYLON
Base Number Matches：	1

电子百科

产品导航

产品型号5833的Datasheet PDF文件预览

583274-1相关产品

583274-1相关文章

IC37:专业IC行业平台