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产品型号5962-9678301QSA的概述

芯片5962-9678301QSA的概述 5962-9678301QSA是一款专为军事和航空航天应用设计的集成电路芯片,属于美国国防部认证的“MIL-PRF-38534”系列。该芯片的高可靠性和耐环境特性使其广泛应用于空间、航空和国防领域,尤其是对温度、辐射和振动具有严格要求的应用场景。5962-9678301QSA芯片通常用于信号处理、数据转换和时序控制等任务,具有较高的精确度和稳定性。 该芯片的设计符合军事标准,能够在极端的电气和环境条件下可靠工作。此外,其封装和设计方式也考虑到了电磁干扰(EMI)和电磁兼容性(EMC),因此在实际应用中展示出良好的抗干扰能力。这使得5962-9678301QSA不仅适合于军事应用,也成为一些高端民用设备的选择。 芯片5962-9678301QSA的详细参数 5962-9678301QSA的主要技术参数包括: - 工作电压:该芯片通常在3V-5V的...

产品型号5962-9678301QSA的Datasheet PDF文件预览

SN54AHCT244, SN74AHCT244  
OCTAL BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCLS228L – OCTOBER 1995 – REVISED JULY 2003  
SN54AHCT244 . . . J OR W PACKAGE  
SN74AHCT244 . . . DB, DGV, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
2OE  
1
2
3
4
5
6
7
8
9
10  
20  
19  
description/ordering information  
18 1Y1  
These octal buffers/drivers are designed  
specifically to improve both the performance and  
density of 3-state memory-address drivers, clock  
drivers, and bus-oriented receivers and  
transmitters.  
17  
16  
15  
14  
13  
12  
11  
2A4  
1Y2  
2A3  
1Y3  
2A2  
1Y4  
2A1  
The ’AHCT244 devices are organized as two 4-bit  
buffers/line drivers with separate output-enable  
(OE) inputs. When OE is low, the device passes  
data from the A inputs to the Y outputs. When OE  
is high, the outputs are in the high-impedance  
state.  
SN54AHCT244 . . . FK PACKAGE  
(TOP VIEW)  
To ensure the high-impedance state during power  
up or power down, OE should be tied to V  
CC  
3
2
1 20 19  
18  
through a pullup resistor; the minimum value of  
the resistor is determined by the current-sinking  
capability of the driver.  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
1A2  
2Y3  
1A3  
2Y2  
1A4  
4
5
6
7
8
17  
16  
15  
14  
9 10 11 12 13  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – N  
Tube  
SN74AHCT244N  
SN74AHCT244N  
Tube  
SN74AHCT244DW  
SN74AHCT244DWR  
SN74AHCT244NSR  
SN74AHCT244DBR  
SN74AHCT244PW  
SN74AHCT244PWR  
SOIC – DW  
AHCT244  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP – NS  
AHCT244  
HB244  
–40°C to 85°C  
SSOP – DB  
TSSOP – PW  
HB244  
Tape and reel  
Tape and reel  
Tube  
TVSOP – DGV  
CDIP – J  
SN74AHCT244DGVR HB244  
SNJ54AHCT244J  
SNJ54AHCT244W  
SNJ54AHCT244FK  
SNJ54AHCT244J  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54AHCT244W  
SNJ54AHCT244FK  
LCCC – FK  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54AHCT244, SN74AHCT244  
OCTAL BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCLS228L OCTOBER 1995 REVISED JULY 2003  
FUNCTION TABLE  
(each 4-bit buffer/driver)  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
H
L
H
X
Z
logic diagram (positive logic)  
1
19  
1OE  
2OE  
2A1  
2
18  
16  
14  
12  
11  
13  
15  
17  
9
7
5
3
1A1  
1Y1  
1Y2  
1Y3  
1Y4  
2Y1  
2Y2  
2Y3  
2Y4  
4
1A2  
2A2  
2A3  
2A4  
6
1A3  
8
1A4  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V  
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V  
+ 0.5 V  
O
CC  
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA  
IK  
I
Output clamp current, I  
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA  
OK  
O O CC  
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA  
Continuous current through V  
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W  
O
O
CC  
CC  
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA  
JA  
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W  
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W  
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W  
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W  
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W  
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C  
stg  
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
2. The package thermal impedance is calculated in accordance with JESD 51-7.  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54AHCT244, SN74AHCT244  
OCTAL BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCLS228L OCTOBER 1995 REVISED JULY 2003  
recommended operating conditions (see Note 3)  
SN54AHCT244 SN74AHCT244  
UNIT  
MIN  
4.5  
2
MAX  
MIN  
4.5  
2
MAX  
V
V
V
V
V
Supply voltage  
5.5  
5.5  
V
V
CC  
IH  
IL  
High-level input voltage  
Low-level input voltage  
Input voltage  
0.8  
5.5  
0.8  
5.5  
V
0
0
0
0
V
I
Output voltage  
V
CC  
V
CC  
V
O
I
High-level output current  
Low-level output current  
Operating free-air temperature  
8  
8  
mA  
mA  
°C  
OH  
OL  
I
8
8
T
55  
125  
40  
85  
A
NOTE 3: All unused inputs of the device must be held at V  
or GND to ensure proper device operation. Refer to the TI application report,  
CC  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
T
A
= 25°C  
TYP  
SN54AHCT244 SN74AHCT244  
PARAMETER  
TEST CONDITIONS  
V
UNIT  
V
CC  
MIN  
4.4  
MAX  
MIN  
4.4  
MAX  
MIN  
4.4  
MAX  
I
I
I
I
= 50  
A
4.5  
OH  
OH  
OL  
OL  
V
V
4.5 V  
4.5 V  
OH  
= 8 mA  
= 50  
= 8 mA  
= V  
3.94  
3.8  
3.8  
A
0.1  
0.36  
±0.25  
±0.1  
4
0.1  
0.44  
±2.5  
±1*  
0.1  
0.44  
±2.5  
±1  
V
OL  
I
I
I
V
or GND  
5.5 V  
0 V to 5.5 V  
5.5 V  
A
A
A
OZ  
O
CC  
V = 5.5 V or GND  
I
I
V = V  
or GND,  
I = 0  
O
40  
40  
CC  
I
CC  
One input at 3.4 V,  
Other inputs at V  
5.5 V  
1.35  
10  
1.5  
1.5  
10  
mA  
I  
CC  
or GND  
CC  
or GND  
C
C
V = V  
5 V  
5 V  
2.5  
3
pF  
pF  
i
I
CC  
= V or GND  
CC  
V
o
O
* On products compliant to MIL-PRF-38535, this parameter is not production tested at V  
This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or V  
= 0 V.  
CC  
.
CC  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54AHCT244, SN74AHCT244  
OCTAL BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCLS228L OCTOBER 1995 REVISED JULY 2003  
switching characteristics over recommended operating free-air temperature range,  
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)  
CC  
T
A
= 25°C  
TYP  
SN54AHCT244 SN74AHCT244  
FROM  
(INPUT)  
TO  
(OUTPUT)  
LOAD  
CAPACITANCE  
PARAMETER  
UNIT  
ns  
MIN  
MAX  
7.4*  
7.4*  
MIN  
1*  
1*  
1*  
1*  
1*  
1*  
1
MAX  
8.5*  
8.5*  
12*  
12*  
10*  
10*  
9.5  
9.5  
13  
MIN  
1
MAX  
8.5  
8.5  
12  
t
t
t
t
t
t
5.4*  
PLH  
PHL  
PZH  
PZL  
PHZ  
PLZ  
A
Y
Y
Y
Y
Y
Y
C
C
C
C
C
= 15 pF  
= 15 pF  
= 15 pF  
= 50 pF  
= 50 pF  
L
L
L
L
L
5.4*  
1
7.7* 10.4*  
7.7* 10.4*  
1
ns  
OE  
OE  
1
12  
5*  
5*  
9.4*  
9.4*  
8.4  
1
10  
ns  
1
10  
t
t
t
t
t
t
t
5.9  
5.9  
8.2  
8.2  
8.8  
8.8  
1
9.5  
9.5  
13  
PLH  
PHL  
PZH  
PZL  
PHZ  
PLZ  
sk(o)  
A
ns  
8.4  
1
1
11.4  
11.4  
11.4  
11.4  
1**  
1
1
ns  
OE  
OE  
1
13  
1
13  
1
13  
1
13  
C
C
= 50 pF  
= 50 pF  
ns  
ns  
L
L
1
13  
1
13  
1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.  
** On products compliant to MIL-PRF-38535, this parameter does not apply.  
noise characteristics, V  
= 5 V, C = 50 pF, T = 25°C (see Note 4)  
CC  
L
A
SN74AHCT244  
PARAMETER  
UNIT  
MIN  
TYP  
MAX  
V
V
V
Quiet output, minimum dynamic V  
High-level dynamic input voltage  
Low-level dynamic input voltage  
4.1  
V
V
V
OH(V)  
IH(D)  
IL(D)  
OH  
2
0.8  
NOTE 4: Characteristics are for surface-mount packages only.  
operating characteristics, V  
= 5 V, T = 25°C  
A
CC  
PARAMETER  
TEST CONDITIONS  
No load, f = 1 MHz  
TYP  
UNIT  
C
Power dissipation capacitance  
8.2  
pF  
pd  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54AHCT244, SN74AHCT244  
OCTAL BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCLS228L OCTOBER 1995 REVISED JULY 2003  
PARAMETER MEASUREMENT INFORMATION  
V
CC  
Open  
GND  
S1  
R
= 1 kΩ  
L
TEST  
S1  
From Output  
Under Test  
Test  
Point  
From Output  
Under Test  
t
t
/t  
Open  
PLH PHL  
/t  
C
C
L
t
V
CC  
L
PLZ PZL  
/t  
(see Note A)  
(see Note A)  
GND  
PHZ PZH  
Open Drain  
V
CC  
LOAD CIRCUIT FOR  
LOAD CIRCUIT FOR  
TOTEM-POLE OUTPUTS  
3-STATE AND OPEN-DRAIN OUTPUTS  
3 V  
0 V  
1.5 V  
Timing Input  
t
w
t
h
3 V  
t
su  
3 V  
0 V  
1.5 V  
1.5 V  
Input  
Input  
1.5 V  
1.5 V  
Data Input  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
3 V  
0 V  
3 V  
Output  
Control  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
0 V  
t
t
t
t
t
PZL  
PLZ  
PLH  
PHL  
Output  
Waveform 1  
V
V  
OH  
CC  
In-Phase  
Output  
50% V  
50% V  
50% V  
CC  
50% V  
CC  
CC  
V
S1 at V  
(see Note B)  
CC  
V
V
+ 0.3 V  
OL  
V
OL  
OL  
t
t
t
PHL  
PLH  
PZH  
PHZ  
Output  
Waveform 2  
S1 at GND  
V
OH  
V
OH  
Out-of-Phase  
Output  
0.3 V  
OH  
50% V  
50% V  
CC  
CC  
CC  
V
0 V  
(see Note B)  
OL  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. includes probe and jig capacitance.  
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, Z = 50 , t 3 ns, t 3 ns.  
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.  
E. All parameters and waveforms are not applicable to all devices.  
Figure 1. Load Circuit and Voltage Waveforms  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
26-Sep-2005  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
LCCC  
CDIP  
CFP  
Drawing  
5962-9678301Q2A  
5962-9678301QRA  
5962-9678301QSA  
SN74AHCT244DBLE  
SN74AHCT244DBR  
ACTIVE  
ACTIVE  
FK  
J
20  
20  
20  
20  
20  
1
1
1
TBD  
TBD  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
Level-NC-NC-NC  
Level-NC-NC-NC  
Level-NC-NC-NC  
Call TI  
ACTIVE  
W
OBSOLETE  
ACTIVE  
SSOP  
SSOP  
DB  
DB  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74AHCT244DBRE4  
SN74AHCT244DGVR  
SN74AHCT244DGVRE4  
SN74AHCT244DW  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SSOP  
TVSOP  
TVSOP  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
DB  
DGV  
DGV  
DW  
DW  
DW  
DW  
N
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74AHCT244DWE4  
SN74AHCT244DWR  
SN74AHCT244DWRE4  
SN74AHCT244N  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
20  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
SN74AHCT244NE4  
SN74AHCT244NSR  
SN74AHCT244NSRG4  
SN74AHCT244PW  
PDIP  
N
20  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
SO  
NS  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
NS  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TSSOP  
TSSOP  
PW  
PW  
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74AHCT244PWE4  
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74AHCT244PWLE  
SN74AHCT244PWR  
OBSOLETE TSSOP  
PW  
PW  
20  
20  
TBD  
Call TI  
Call TI  
ACTIVE  
ACTIVE  
ACTIVE  
TSSOP  
TSSOP  
TSSOP  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74AHCT244PWRE4  
SN74AHCT244PWRG4  
PW  
PW  
20  
20  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SNJ54AHCT244FK  
SNJ54AHCT244J  
SNJ54AHCT244W  
ACTIVE  
ACTIVE  
ACTIVE  
LCCC  
CDIP  
CFP  
FK  
J
20  
20  
20  
1
1
1
TBD  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Level-NC-NC-NC  
Level-NC-NC-NC  
Level-NC-NC-NC  
W
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
26-Sep-2005  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
MECHANICAL DATA  
MLCC006B – OCTOBER 1996  
FK (S-CQCC-N**)  
LEADLESS CERAMIC CHIP CARRIER  
28 TERMINAL SHOWN  
A
B
NO. OF  
TERMINALS  
**  
18 17 16 15 14 13 12  
MIN  
MAX  
MIN  
MAX  
0.342  
(8,69)  
0.358  
(9,09)  
0.307  
(7,80)  
0.358  
(9,09)  
19  
20  
11  
10  
9
20  
28  
44  
52  
68  
84  
0.442  
(11,23)  
0.458  
(11,63)  
0.406  
(10,31)  
0.458  
(11,63)  
21  
B SQ  
22  
0.640  
(16,26)  
0.660  
(16,76)  
0.495  
(12,58)  
0.560  
(14,22)  
8
A SQ  
23  
0.739  
(18,78)  
0.761  
(19,32)  
0.495  
(12,58)  
0.560  
(14,22)  
7
24  
25  
6
0.938  
(23,83)  
0.962  
(24,43)  
0.850  
(21,6)  
0.858  
(21,8)  
5
1.141  
(28,99)  
1.165  
(29,59)  
1.047  
(26,6)  
1.063  
(27,0)  
26 27 28  
1
2
3
4
0.080 (2,03)  
0.064 (1,63)  
0.020 (0,51)  
0.010 (0,25)  
0.020 (0,51)  
0.010 (0,25)  
0.055 (1,40)  
0.045 (1,14)  
0.045 (1,14)  
0.035 (0,89)  
0.045 (1,14)  
0.035 (0,89)  
0.028 (0,71)  
0.022 (0,54)  
0.050 (1,27)  
4040140/D 10/96  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. This package can be hermetically sealed with a metal lid.  
D. The terminals are gold plated.  
E. Falls within JEDEC MS-004  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000  
DGV (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
24 PINS SHOWN  
0,23  
0,13  
M
0,07  
0,40  
24  
13  
0,16 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
0°ā8°  
0,75  
1
12  
0,50  
A
Seating Plane  
0,08  
0,15  
0,05  
1,20 MAX  
PINS **  
14  
16  
20  
24  
38  
48  
56  
DIM  
A MAX  
A MIN  
3,70  
3,50  
3,70  
3,50  
5,10  
4,90  
5,10  
4,90  
7,90  
7,70  
9,80  
9,60  
11,40  
11,20  
4073251/E 08/00  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.  
D. Falls within JEDEC: 24/48 Pins – MO-153  
14/16/20/56 Pins – MO-194  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001  
DB (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
28 PINS SHOWN  
0,38  
0,22  
0,65  
28  
M
0,15  
15  
0,25  
0,09  
5,60  
5,00  
8,20  
7,40  
Gage Plane  
1
14  
0,25  
A
0°ā8°  
0,95  
0,55  
Seating Plane  
0,10  
2,00 MAX  
0,05 MIN  
PINS **  
14  
16  
20  
24  
28  
30  
38  
DIM  
6,50  
5,90  
6,50  
5,90  
7,50  
8,50  
7,90  
10,50  
9,90  
10,50 12,90  
A MAX  
A MIN  
6,90  
9,90  
12,30  
4040065 /E 12/01  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-150  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
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Use of such information may require a license from a third party under the patents or other intellectual property  
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Following are URLs where you can obtain information on other Texas Instruments products and application  
solutions:  
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Amplifiers  
amplifier.ti.com  
www.ti.com/audio  
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dataconverter.ti.com  
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www.ti.com/automotive  
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dsp.ti.com  
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www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
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interface.ti.com  
logic.ti.com  
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power.ti.com  
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www.ti.com/opticalnetwork  
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Copyright 2005, Texas Instruments Incorporated  

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