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IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

IDT5V9885T

3.3V EEPROM

PROGRAMMABLE CLOCK

GENERATOR

FEATURES:

DESCRIPTION:

• Three internal PLLs

TheIDT5V9885Tisaprogrammableclockgeneratorintendedforhigh

performancedata-communications,telecommunications,consumer,and

networking applications. There are three internal PLLs, each individually

programmable,allowingforthreeuniquenon-integer-relatedfrequencies.

The frequencies are generated from a single reference clock. The

reference clock can come from one of the two redundant clock inputs. A

glitchless automatic or manual switchover function allows any one of the

redundant clocks to be selected during normal operation.

• Internal non-volatile EEPROM

• JTAG and FAST mode I²C serial interfaces

• Input Frequency Ranges: 1MHz to 400MHz

• Output Frequency Ranges: 4.9kHz to 500MHz

• Reference Crystal Input with programmable oscillator gain and

programmable linear load capacitance

− Crystal Frequency Range: 8MHz to 50MHz

• Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider

• 10-bit post-divider blocks

The IDT5V9885T can be programmed through the use of the I²C or

JTAG interfaces. The programming interface enables the device to be

programmedwhenitisinnormaloperationorwhatiscommonlyknownas

in-system programmable. An internal EEPROM allows the user to save

and restore the configuration of the device without having to reprogram it

on power-up. JTAG boundary scan is also implemented.

• Fractional Dividers

• Two of the PLLs support Spread Spectrum Generation

capability

• I/O Standards:

− Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS

− Inputs - 3.3V LVTTL/ LVCMOS

Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback

divider. Thisallowstheusertogeneratethreeuniquenon-integer-related

frequencies. The PLL loop bandwidth is programmable to allow the user

totailorthePLLresponsetotheapplication. Forinstance,theusercantune

the PLL parameters to minimize jitter generation or to maximize jitter

attenuation. Spread spectrum generation and fractional divides are

allowed on two of the PLLs.

• Programmable Slew Rate Control

• Programmable Loop Bandwidth Settings

• Programmable output inversion to reduce bimodal jitter

• Redundant clock inputs with glitchless auto and manual

switchover options

• JTAG Boundary Scan

• Individual output enable/disable

• Power-down mode

Thereare10-bitpostdividersonfiveofthesixoutputbanks. Twoofthe

six output banks are configurable to be LVTTL, LVPECL, or LVDS. The

otherfouroutputbanksareLVTTL. TheoutputsareconnectedtothePLLs

via the switch matrix. The switch matrix allows the user to route the PLL

outputstoanyoutputbank. Thisfeaturecanbeusedtosimplifyandoptimize

the board layout. In addition, each output's slew rate and enable/disable

function can be programmed.

• 3.3VVDD

• Available in TQFP and VFQFPN packages

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

SEPT. 2011

1

c

2011 Integrated Device Technology, Inc.

DSC 7117/4

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

FUNCTIONALBLOCKDIAGRAM

XTALOUT

OSC.

XTALIN/REFIN

OUT1

P2 Divider

10-Bit

/2

OUT2

P3 Divider

10-Bit

PLL 0

OUT3

CLKIN

OUT4⁽¹⁾

P4 Divider

10-Bit

PLL 1

PLL 2

/2

(1)

OUT4

OUT5⁽¹⁾

OUT5 ⁽¹⁾

P5 Divider

10-Bit

SHUTDOWN/OE

/2

P6 Divider

10-Bit

EEPROM

OUT6

GOUT0/TDO/

LOSS_LOCK

GIN5/CLK_SEL

I ²C/JTAG

Control Block for

Multi-Purpose I/O, Programming, Features

GOUT1/

LOSS_CLKIN

NOTE:

1. OUT4 and OUT5 pairs can be configured to be LVDS, LVPECL, or two single-ended LVTTL outputs. As LVTTL, OUT4 and OUT5 can be configured to be non-inverting.

2

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

PINCONFIGURATION

32 31 30 29 28 27 26 25

28 27 26 25 24 23 22

CLKIN

GND

GIN2/TMS

VDD

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

21

20

19

18

17

16

15

CLKIN

GND

GIN2/TMS

VDD

1

2

3

4

5

6

7

GOUT1/LOSS_CLKIN

XTALIN/REFIN

I ²C/JTAG

GOUT1/LOSS_CLKIN

XTALIN/REFIN

I²C/JTAG

GIN5/CLK_SEL

GND

GIN5/CLK_SEL

XTALOUT

OUT1

VDD

GIN1/SCLK/TCLK

GIN0/SDA/TDI

GND

XTALOUT

OUT1

GIN1/SCLK/TCLK

GIN0/SDA/TDI

VDD

OUT3

VDD

OUT3

8

9

10 11 12 13 14

9

10 11 12 13 14 15 16

VFQFPN

TQFP

TOP VIEW

3

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

PINDESCRIPTION

PF32

Pin#

NL28

Pin#

Pin Name

CLKIN

I/O

Type

LVTTL

Description

1

4

1

4

I

InputClock

XTALIN/REFIN

XTALOUT

LVTTL

CRYSTAL_IN-Referencecrystalinputorexternalreferenceclockinput

5

O

I

LVTTL

CRYSTAL_OUT-Referencecrystalfeedback

GIN0/SDAT/TDI

GIN1/SCLK/TCK

GIN2/TMS

19

20

24

27

16

17

21

23

LVTTL^(1,2)

Multi-purposeinputs. CanbeusedforFrequencyControl,SDAT(I²C),orTDI(JTAG).

Multi-Purposeinputs. CanbeusedforFrequencyControl,SCLK(I²C),orTCK(JTAG).

Multi-Purpose inputs. Can be used for Frequency Control or TMS (JTAG)

I

GIN3/SUSPEND

I

Multi-Purposeinputs. CanbeusedforFrequencyControlorasasuspendmodecontrol

input (active HIGH).

GIN4/TRST

GIN5/CLK_SEL

SHUTDOWN/OE

25

21

28

22

18

24

I

LVTTL^(1,2)

Multi-Purpose inputs. Can be used for Frequency Control or TRST (JTAG)

Multi-Purposeinputs. CanbeusedforFrequencyControlorinputclockselector.

Enables/disablestheoutputsorpowersdownthechip.TheSPbit(0x1C)controlsthe

polarity of the signal to be either active HIGH or LOW. (Default is active HIGH.)

I²C/JTAG

OUT1

22

6

19

6

I

3-level⁽³⁾

LVTTL

I²C (HIGH) or MFC Mode (MID) or JTAG Programming (LOW)

Configurableclockoutput1.Canalsobeusedtobufferthereferenceclock.

Configurableclockoutput2

O

OUT2

29

8

25

7

LVTTL

OUT3

LVTTL

Configurableclockoutput3

OUT4

10

11

8

Adjustable⁽⁴⁾

Configurableclockoutput4,Single-EndedorDifferentialwhencombinedwithOUT4

OUT4

9

Configurable complementary clock output 4, Single-Ended or Differential when

combinedwithOUT4

OUT5

15

16

13

14

O

Adjustable⁽⁴⁾

Configurableclockoutput5,Single-EndedorDifferentialwhencombinedwithOUT5

Configurable complementary clock output 5, Single-Ended or Differential when

combinedwithOUT5

OUT6

13

31

11

27

O

LVTTL

LVTTL⁽¹⁾

Configurableclockoutput6

GOUT0/TDO/LOSS_LOCK

Multi-PurposeOutput.CanbeprogrammedtouseasPLLLOCKsignal,LOSS_LOCK

or TDO in JTAG mode

GOUT1/LOSS_CLKIN

3

O

LVTTL

Multi-Purpose Output. Can be programmed to use as LOSS_CLKIN

3.3V Power Supply

VDD

7,12,17, 10,15,20

23,26,32

28

GND

2,9,14,

18,30

2,12,26

Ground

NOTES:

1. The JTAG (TDO, TMS, TCLK, TRST, and TDI) and I²C (SCLK and SDAT) signals share the same pins with GIN signals.

2. Weak internal 100KΩ pull-down resistor.

3. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are internally biased to VDD/2. They are not hot-insertable or over voltage tolerant.

4. Outputs are user programmable to drive single-ended 3.3V LVTTL, differential LVDS, or differential LVPECL interface levels.

4

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

PLLFEATURESANDDESCRIPTIONS

D0 Divider

VCO

M0 Multiplier

Spread

Spectrum

Modulation

PLL0 Block Diagram

D1 Divider

VCO

M1 Multiplier

Spread

Spectrum

Modulation

PLL1 Block Diagram

D2 Divider

VCO

M2 Multiplier

PLL2 Block Diagram

5

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

Spread Spectrum

Pre-Divider (D) Values

Multiplier (M) Values

Programmable Loop Bandwidth

GenerationCapability

PLL0

PLL1

PLL2

1 - 255

2 - 8190

1 - 4095

yes

no

REFERENCE CLOCK INPUT PINS AND

SELECTION

XTAL load cap = 3.5pF + XTALCAP[7:0] * 0.125pF (Eq. 1)

Parameter

Bits

Step

Min

Max

Units

The 5V9885T supports up to two clock inputs. One of the clock inputs

(XTALIN/ REFIN) can be driven by either an external crystal or a reference

clock. The second clock input (CLKIN) can only be driven from an external

referenceclock.Eitherclockinputcanbesetasatheprimaryclock. Theprimary

clockdesignation istoestablishwhichisthemainreferenceclocktothePLLs.

Thenon-primaryclockisdesignatedasthesecondaryclockincasetheprimary

clock goes absent and a backup is needed. The PRIMCLK bit (0x34)

determineswhichclockinputwillbetheprimaryclock. WhenPRIMCLKbitis

"0",itwillselectXTALIN/REFINastheprimary,andwhen"1",itwillselectCLKIN

astheprimary. Thetwoexternalreferenceclockscanbemanuallyselected

using the GIN5/CLK_SEL pin, except in Manual Frequency Control (MFC)

mode2,orviaprogrammingbyhardwiringtheCLK_SELpinandtogglingthe

PRIMCLKbit. FormoredetailsontheMFCmodes,refertotheCONFIGURING

MULTI-PURPOSEI/Ossection. WhenCLK_SELisLOW,theprimaryclock

isselectedandwhenHIGH,thesecondaryclockisselected. TheSMbits(0x34)

mustbesetto"0x"formanualswitchoverwhichisdetailedinSWITCHOVER

MODESsection.

XTALCAP

8

0.125

0

32

pF

When using an external reference clock instead of a crystal on the XTAL/

REFINpin,theinputloadcapacitorsmaybecompletelybypassed.Thisallows

fortheinputfrequencytobeupto200MHz. Whenusinganexternalreference

clock,theXTALOUTpinmustbeleftfloating,XTALCAPmustbeprogrammed

to the default value of "0", and crystal drive strength bit, XDRV (0x06), must

be set to the default value of "11".

CLKIN Pin

CLKIN pin is a regular clock input pin, and can be driven up to 400MHz.

PRE-SCALER,FEEDBACK-DIVIDER,AND

POST-DIVIDER

Each PLL incorporates an 8-bit pre-scaler and a 12-bit feedback divider

whichallowstheusertogeneratethreeuniquenon-integer-relatedfrequencies.

For output banks OUT2-OUT6, each bank has a 10-bit post-divider. The

following equation governs how the frequency on output banks OUT2-6 is

calculated.

GIN5/CLK_SEL

Selected Clock Input

L

Primary

H

Secondary

(^M)

Crystal Input (XTALIN/REFIN)

FOUT = FIN * D

(Eq. 2)

Thecrystaloscillatorsshouldbefundamentalmodequartzcrystals:overtone

crystals are not suitable. Crystal frequency should be specified for parallel

resonancewith50Ωmaximumequivalentseriesresonance.

P * 2

WhereFIN isthereferencefrequency,Misthetotalfeedback-dividervalue,

Disthepre-scalervalue,Pisthetotalpost-dividervalue,andFOUT istheresulting

output bank frequency. The value 2 in the denominator is due to the divide-

by-2oneachoftheoutputbanksOUT2-6. NotethatOUT1doesnothaveany

typeofpost-divider. Also,programminganyofthedividersmaycauseglitches

ontheoutputs.

WhentheXTALIN/REFINpinisdrivenbyacrystal,itisimportanttosetthe

internal oscillator inverter drive strength and internal tuning/load capacitor

values correctly to achieve the best clock performance. These values are

programmable through either I²C or JTAG interface to allow for maximum

compatibilitywithcrystalsfromvariousmanufacturers,processes,performances,

andqualities.Theinternalloadcapacitorsaretrueparallel-platecapacitorsfor

ultra-linearperformance. Parallel-platecapacitorswerechosentoreducethe

frequencyshiftthatoccurswhennon-linearloadcapacitanceinteractswithload,

bias, supply, and temperature changes. External non-linear crystal load

capacitors should not be used for applications that are sensitive to absolute

frequencyrequirements.Thevalueoftheinternalloadcapacitorsaredetermined

byXTALCAP[7:0]bits,(0x07).Theloadcapacitancecanbesetwitharesolution

of0.125pFforatotalcrystalloadrangeof3.5pFto35.5pF. Thisvalueshould

be set to two times the crystal load capacitance value stated by the vendor,

subtractingoutboardcapacitancevalue.Checkwiththevendor'scrystalload

capacitancespecificationfortheexactsettingtotunetheinternalloadcapacitor.

Thefollowingequationgovernshowthetotalinternalloadcapacitanceisset.

Ex.: For crystal capacitance = 12pF

Pre-Scaler

D[7:0] are the bits used to program the pre-scaler for each PLL, D0 for

PLL0, D1 for PLL1, and D2 for PLL2. The pre-scalers divide down the

referenceclockwithintegervaluesrangingfrom1to255. Tomaintainlowjitter,

thedivideddownclockmustbehigherthan400KHz;itisbesttousethesmallest

Ddividervaluepossible. IfDissetto'0x00',thenthiswillpowerdownthePLL

andalltheoutputsassociatedwiththatPLL.

For board capacitance = 3pF each leg

XTALCAP = 2x [12-3] = 18pF

6

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

Feedback-Divider

N[11:0]andA[3:0]arethebitsusedtoprogramthefeedback-dividerforPLL0(N0andA0)andPLL1(N1andA1). Ifspreadspectrumgenerationisenabled

foreitherPLL0orPLL1,thenthe SS_OFFSET[5:0]bits(0x61,0x69)wouldbefactoredintotheoverallfeedbackdividervalue. SeetheSPREADSPECTRUM

GENERATIONsectionformoredetailsonhowtoconfigurePLL0andPLL1whenspreadspectrumisenabled. ThetwoPLLscanalsobeconfiguredforfractional

divideratios. SeeFRACTIONALDIVIDERformoredetails. ForPLL2,onlytheN[11:0]bits(N2)areusedtoprogramitsfeedbackdividerandthereisnospread

spectrumgenerationandfractionaldividescapability. The12-bitfeedback-dividerintegervaluesrangefrom1to4095.

The following equations govern how the feedback divider value is set. Note that the equations are different for PLL0/PLL1 and PLL2

PLL0 and PLL1:

M = 2*N[11:0] + A[3:0] + 1 + SS_OFFSET[5:0] * 1/64

M = 2*N[11:0] + A[3:0] + 1 (spread spectrum disabled)

(Eq. 3)

(Eq. 4)

A[3:0] = 0000 = -1

= 0001 = 1

= 0010 = 2

= 0011 = 3

.

= 1111 = 15

Note: A[3:0] < (N[11:0] - 5), must be met when using A. N cannot be programmed with a value of 4, 8, or 16 when using A.

PLL2:

M = N[11:0]

(Eq. 5)

TheusercanachieveanevenoroddintegerdivideratioforbothPLL0andPLL1bysettingtheA[3:0]bitsaccordinglyanddisablingthespreadspectrum.

AfractionaldividecanalsobesetforPLL0andPLL1byusingtheA[3:0]bitsinconjunctionwiththeSS_OFFSET[5:0]bits,whichisdetailedintheFRACTIONAL

DIVIDERsection. NotethattheVCOhasafrequencyrangeof10MHzto1200MHz. To maintainlowjitter,itisbesttomaximizetheVCOfrequency. Forexample,

if thereferenceclockis100MHzanda200MHzclockisrequired,toachievethebestjitterperformance,multiplythe100MHzby12togettheVCOrunningat

thehighestpossiblefrequencyof1200MHzandthendivideitdowntoget200MHz. Orifthereferenceclockis25MHzand20MHzistherequiredclock,multiply

the25MHzby40togettheVCOrunningat1000MHzandthendivideitdowntoget20MHz. IfNissetto'0x00', theVCOwillslewtotheminimumfrequency.

Post-Divider

Q[9:0] are the bits used to program the 10-bit post-dividers on output banks OUT2-6. OUT1 bank does not have a 10-bit post-divider or any other post-

divide along its path. The 10-bit post-dividers will divide down the output banks' frequency with integer values ranging from 1 to 1023.

There is the option to choose between disabling the post-divider, utilizing a div/1, a div/2, or the 10-bit post-divider by using the PM[1:0] bits. Each bank,

exceptforOUT1,hasasetofPMbits. Whendisablingthepost-divider,noclockwillappearattheoutputs,butwillremainpoweredon. Thevaluesarelisted

inthetablebelow.

P

00

01

PM[1:0]

P Post-Divider

disabled

To Outputs

VCO

00

01

10

11

/2

10

11

/2

div/1

/ (Q+2)

div/2

Q[9:0] + 2 (Eq. 6)

PM[1:0]

Post-Divider Diagram

7

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

Notethattheactual10-bitpost-dividervaluehasa2addedtotheintegervalueQandtheoutputsareroutedthroughanotherdiv/2block. Thepost-divider

shouldneverbedisabledunlesstheoutputbankwillneverbeusedduringnormaloperation. TheoutputfrequencyrangeforLVTTLoutputsarefrom4.9KHz

to 200MHz. The output frequency range for LVPECL/LVDS outputs are from 4.9KHz to 500MHz.

SPREADSPECTRUMGENERATION

PLL0andPLL1supportspreadspectrumgenerationcapability,whichusershavetheoptionofturningonandoff. Spreadspectrumprofile,frequency,and

spreadarefullyprogrammable(withinlimits). TheprogrammablespreadspectrumgenerationparametersareTSSC[3:0], NSSC[3:0], SS_OFFSET[5:0],

SD[3:0],DITH,andX2bits. Thesebitsareinthememoryaddressrangeof0x60to0x67forPLL0and0x68to0x6FforPLL1. Thespreadspectrumgeneration

on PLL0 & PLL1 can be enabled/disabled using the TSSC[3:0] bits. To enable spread spectrum, set TSSC > '0' and set NSSC, SD[3:0], SD[5:0], and the

A[3:0] in the total M value accordingly. And to disable, set TSSC = '0'.

TSSC[3:0]

Thesebitsareusedtodeterminethenumberofphase/frequencydetectorcyclesperspreadspectrumcycle(ssc)steps. Themodulationfrequencycanbe

calculatedwiththeTSSCbitsinconjunctionwiththeNSSCbits. ValidTSSCintegervaluesforthemodulationfrequencyrangefrom5to14.

NSSC[3:0]

Thesebitsareusedtodeterminethenumberofdelta-encodedsamplesusedforasinglequadrantof thespreadspectrumwaveform. Allfourquadrants

ofthespreadspectrumwaveformaremirrorimagesofeachother. ThemodulationfrequencyisalsocalculatedbasedofftheNSSCbitsinconjunctionwiththe

TSSC bits. Valid NSSC integer values range from 1 to 6.

SS_OFFSET[5:0]

ThesebitsareusedtoprogramthefractionaloffsetwithrespecttothenominalMintegervalue. Forcenterspread,theSS_OFFSETshouldbesetto'0'so

thespreadspectrumwaveformisaboutthenominalM(Mnom)value. Fordownspread,theSS_OFFSET>'0'sothespreadspectrumwavformisaboutthe

(Mideal-1=Mnom)value. Thedownspreadpercentagecanbethoughtofintermsofcenterspread. Forexample,adownspreadof-1%canalsobeconsidered

as a center spread of ±0.5% but with Mnom shifted down by one and offset. The SS_OFFSET has integer values ranging from 0 to 63.

SD[3:0]

Thesebitsareusedtoshapetheprofileofthespreadspectrumwaveform. Thesearedelta-encodedsamplesofthewaveform. Therearetwelvesetsof

SDsamplesforeachPLL. TheNSSCbitsdeterminehowmanyofthesesamplesareusedforthewaveform. Thesumofthesedelta-encodedsamples(sigma-

delta-encodedsamples)determinetheamountofspreadandshouldnotexceed(63-SS_OFFSET). Themaximumspreadisinverselyproportionaltothe

nominalMintegervalue.

DITH

Thisbitisforditheringthesigma-delta-encodedsamples. Thiswillrandomizetheleast-significantbitoftheinputtothespreadspectrummodulator. Setthe

bitto'1'toenabledithering.

X2

Thisbitwilldoublethetotalvalueofthesigma-delta-encoded-sampleswhichwillincreasetheamplitudeofthespreadspectrumwaveformbyafactoroftwo.

WhenX2is'0', theamplituderemainsnominalbutifsetto'1', theamplitudeisincreasedbyx2.

Thefollowingequationsgovernhowthespreadspectrumisset:

TSSC = TSSC[3:0] + 2 (Eq. 7)

NSSC = NSSC[3:0] * 2 (Eq. 8)

SD[3:0]K = SJ+1(unencoded) - SJ(unencoded) (Eq. 9)

where SJ is the unencoded sample out of a possible 12 and SDK is the delta-encoded sample out of a possible 12.

Amplitude = (2*N[11:0] + A[3:0] + 1) * Spread% / 100

(Eq. 10)

2

if 1 < Amp < 2, then set X2 bit to '1'.

8

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

Modulation frequency:

FPFD = FIN / D (Eq. 11)

FVCO = FPFD * MNOM (Eq. 12)

FSSC = FPFD / (4 * Nssc * Tssc)

(Eq. 13)

Spread:

Σ∆ = SD0 + SD1 + SD2 + … + SD11

the number of samples used depends on the NSSC value

Σ∆ ≤ 63 - SS_OFFSET

±Spread% =

Σ∆ * 100

(Eq. 14)

64 * (2*N[11:0] + A{3:0} + 1)

±Max Spread% / 100 = 1 / MNOM or 2 / MNOM (X2=1)

Profile:

WaveformstartswithSS_OFFSET, SS_OFFSET+SDJ, SS_OFFSET+SDJ+1, etc.

Σ∆ = 63

(SS_OFFSET = 0)

Spread Spectrum Using Sinusoidal Profile

9

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

Example

FIN = 25MHz, FOUT = 100MHz, Fssc = 33KHz with center spread of ±2%. Find the necessary spread spectrum register settings.

Sincethespreadiscenter,theSS_OFFSETcanbesetto'0'. SolveforthenominalMvalue;keepinmindthatthenominalMshouldbechosentomaximize

the VCO. Start with D = 1, using Eq.10 and Eq.11.

MNOM = 1200MHz / 25MHz = 48

Using Eq.4, we arbitrarily choose N = 22, A = 3. Now that we have the nominal M value, we can determine TSSC and NSSC by using Eq.12.

Nssc * Tssc = 25MHz / (33KHz * 4) = 190

However, using Eq. 7 and Eq.8, we find that the closest value is when TSSC = 14 and NSSC = 6. Keep in mind to maximize the number of samples used

toenhancetheprofileofthespreadspectrumwaveform.

Tssc = 14 + 2 = 16

Nssc = 6 * 2 = 12

Nssc * Tssc = 192

UseEq.14todeterminethevalueofthesigma-delta-encodedsamples.

±2% = Σ∆ * 100

64 * 48

Σ∆ = 61.44

Eitherroundupordowntothenearestintegervalue. Therefore,weendupwith61or62forsigma-delta-encodedsamples. Sincethesigma-delta-encoded

samplesmustnotexceed63with SS_OFFSETsetto'0', 61or62iswellwithinthelimits. Itisthediscretionoftheusertodefinetheshapeof theprofilethat

isbettersuitedfortheintendedapplication.

Using Eq.14 again, the actual spread for the sigma-delta-encoded samples of 61 and 62 are ±1.99% and ±2.02%, respectively.

UseEq.10todetermineiftheX2bitneedstobeset;

Amplitude = 48 * (1.99 or 2.02) / 100 = 0.48 < 1

2

Therefore, the X2 = '0 '. The dither bit is left to the discretion of the user.

The example above was of a center spread using spread spectrum. For down spread, the nominal M value can be set one integer value lower to 43.

Note that the 5V9885T should not be programmed with TSSC > '0', SS_OFFSET = '0', and SD = '0' in order to prevent an unstable state in the modulator.

ThePLLloopbandwidthmustbeatleast10xthemodulationfrequencyalongwithhigherdamping(largerωuz)topreventthespreadspectrumfrombeingfiltered

andreduceextraneousnoise. RefertotheLOOPFILTERsectionformoredetailonωuz.TheA[3:0]mustbeusedforspreadspectrum,evenifthetotalmultiplier

value is an even integer.

FRACTIONALDIVIDER

There is the option for the feedback-divider to be programmed as a fractional divider for only PLL0 and PLL. By setting TSSC > '0' and SD bits to '0', the

SS_OFFSETbitswoulddeterminethefractionaldividevalue.SeetheSPREADSPECTRUMGENERATIONsectionformoredetailsontheTSSC,SD,and

SS_OFFSET bits. The following equation governs how the fractional divide value is set.

M = 2*N[11:0] + A[3:0] + 1 + SS_OFFSET[5:0] *1/64

10

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

ThespreadspectrumparameterssuchasthemodulationfrequencyandprofilewillnotbeenablednorwillithaveanyimpactonthePLLoutputwhenthe

PLLisprogrammedforfractionaldivide.

Thefollowingisanexampleofhowtosetthefractionaldivider.

Example

FIN = 20MHz, FOUT1 = 168.75MHz, FOUT2 = 350MHz

Solving for 350MHz using Eq.2 and Eq.3 with PLL0 and spread spectrum off,

350MHz = 20MHz * (M / D)/ (P * 2)

Forbetterjitterperformance,keepDassmallaspossible

(350MHz * 2/20MHz)= (M/P) = 35

Therefore, we have D = 1, M = 35 (N = 16, A = 2) for PLL0 with P = 1 on output bank4 resulting in 350MHz.

Solving for 168.75MHz with PLL1 and fractional divide enabled:

168.75MHz = 20MHz * (M / D)/(P * 2)

168.75MHz * 2/20MHz = M/P = 16.875/1 or 33.75/2

The 33.75 value is chosen to achieve the highest VCO frequency possible. Next step is to figure out the setting for the fractional divide using Eq.3.

33.75 = 2*N + A + 1 + SS_OFFSET * 1/64

Integer value 33 can be determined by N and A, thus leaving 0.75 left to be solved.

2*N + A + 1 = 33

SS_OFFSET = 64 * 0.75 = 48

Therefore, we have D=1, M=33.75 (N=15, A=2, SS_OFFSET=48) for PLL1 with P=2 on an output bank resulting in 168.75MHz.

Thefractionaldividercanbedeterminedifitisneededbyfollowingthestepsinthepreviousexample. Notethatthe5V9885Tshouldnotbeprogrammed

with TSSC > '0', SS_OFFSET = '0', and SD = '0' in order to prevent an unstable state in the modulator. The A[3:0] must be used and set to be greater than

'2'foramoreaccuratefractionaldivide.

11

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

LOOPFILTER

TheloopfilterforeachPLLcanbeprogrammedtooptimizethejitterperformance. Thelow-passfrequencyresponseofthePLListhemechanismthatdictates

thejittertransfercharacteristics. Theloopbandwidthcanbeextractedfromthejittertransfer. Anarrowloopbandwidthisgoodforjitterattenuationwhileawide

loopbandwidthisbestforlowjittergeneration. ThespecificloopfiltercomponentsthatcanbeprogrammedaretheresistorviatheRZ[3:0]bits,polecapacitor

via the CZ[3:0] bits, zero capacitor via the CP[3:0] bits, and the charge pump current via the IP[2:0] bits.

Thefollowingequationsgovernhowtheloopfilterisset.

VDD

Ip

UP

To VCO

From PFD

DOWN

Rz

Ip

Cp

Cz

Charge Pump and Loop Filter Configuration

Resistor (Rz) = 0.3KΩ+ RZ[3:0] * 1KΩ

(Eq. 15)

Zero capacitor (Cz) = 6pF + CZ[3:0] * 27.2pF (Eq. 16)

Pole capacitor (Cp) = 1.3pF + CP[3:0] * 0.75pF (Eq. 17)

Charge pump current (Ip) = 5 * 2^IP[2:0]µA

(Eq. 18)

Parameter

Bits

4

Step

Min

0.3

6

Max

15.3

414

Units

K Ω

pF

RZ

CZ

CP

IP

1

4

27.2

0.75

2ⁿ

4

1.3

5

12.55

640

pF

3

µA

PLLloopfilterdesignisbeyondthescopeofthisdatasheet. Refertodesignproceduresfor3-ordercharge-pumpbasedPLLs. Forthesakeofsimplicity,

thefastestandeasiestwaytocalculatethePLLloopbandwidth(Fc)giventheprogrammableloopfilterparametersisasfollows.

PLL Loop Bandwidth:

Charge pump gain (Kφ) = Ip / 2π

(Eq. 19)

VCO gain (KVCO) = 950MHz/V * 2π (Eq. 20)

M=Totalmultipliervalue(SeethePRE-SCALERS, FEEDBACK-DIVIDERS, POST-DIVIDERSsectionformoredetail)

ωc = Rz * Kφ * KVCO * Cz (Eq. 21)

M * (Cz + Cp)

Fc = ωc / 2π

(Eq. 22)

Note, the phase/frequency detector frequency (FPFD) is typically seven times the PLL closed-loop bandwidth (Fc) but too high of a ratio will reduce your

phasemarginthuscompromisingloopstability.

12

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

To determine if the loop is stable, the phase margin (ωm) would need to be calculated as follows.

Phase Margin:

ωz = 1 / (Rz * Cz)

ωp = Cz + Cp

Rz * Cz * Cp

(Eq. 23)

(Eq. 24)

φm = (360 / 2π ) * [tan^-1(ωc/ ωz) - tan^-1(ωc/ ωp)]

(Eq. 25)

Toensurestabilityintheloop,thephasemarginisrecommendedtobe>60°buttoohighwillresultinthelocktimebeingexcessivelylong. Certainloopfilter

parameterswouldneedtobecompromisedtonotonlymeetarequiredloopbandwidthbuttoalsomaintainloopstability.

Example

Fc = 150KHz is the desired loop bandwidth. The total M value is 850. The ratio of ωp/ωc should be at least 4. A rule of thumb that will help to aid the way,

theωp/ωcratioshouldbeatleast4. GivenFcandM,anoptimalloopfiltersettingneedstobesolvedforthatwillmeetboththePLLloopbandwidthandmaintain

loopstability.

The charge pump gain should be relatively small as possible to achieve a low loop bandwidth.

Ip = 40uA .

Kφ* KVCO = 950MHz/V * 40uA = 38000A/Vs

LoopBandwidths

ωc = 2π * Fc = 9.42x10⁵s^-1

ωuz = ωp / ωc = 4

ωc²= ωp * ωz

(Eq. 26)

(Eq. 27)

ωp = Cz + Cp = ωz (1 + Cz / Cp)

Rz * Cz * Cp

Solving for Cz, Cp, and Rz

Knowing ωc = Rz * Kφ* KVCO * Cz and substituting in the equations from above,

M * (Cz + Cp)

Cz >>> Cp, therefore, we can easily derive Cp to be

Cp = Kφ* KVCO

= 12.60pF

M * ωc²* ωuz

Similarly for Cz and Rz

Cz = Kφ* KVCO * (ωuz²- 1) = Cp * (ωuz²- 1) = 189pF

M * ωc²* ωuz

Rz =

M * ωc * ωuz²

= 22.48KΩ

Kφ* KVCO * (ωuz²- 1)

Basedontheloopfilterparameterequationsfromabove,sincetherearenopossiblevaluesof12.60pFforCp,189pFforCz,and22.48KΩforRz,thenext

possiblevalueswithintheloopfiltersettingsare12.55pF(CP[3:0]=1111),196.4pF(CZ[3:0]=0111),and15.3KΩ(RZ[3:0]=1111),respectively. Thisloopfilter

settingwillyieldaloopbandwidthofabout102KHz. Thephasemarginmustbecheckedforloopstability.

φm = (360 / 2π ) * [tan^-1(6.41x10⁵s^-1/ 3.33x10⁵s^-1) - tan^-1(6.41x10⁵s^-1/ 5.54x10⁶s^-1)] = 56°

Althoughslightlybelow60°, thephasemarginwouldbeacceptablewithafairlystableloop.

13

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

CONFIGURINGTHEMULTI-PURPOSEI/Os

The5V9885Tcanoperateinfourdistinctmodes. ThesemodesarecontrolledbytheMFCbit(0x04)andtheI²C/JTAGpin. ThegeneralpurposeI/Opins

(GIN0, GIN1, GIN2, GIN3, GIN4, GIN5) have different uses depending on the mode of operation. The four available modes of operation are:

1)

2)

3)

4)

Manual Frequency Control (MFC) Mode for PLL0 Only

Manual Frequency Control (MFC) Mode for all three PLLs

I²CProgrammingMode

JTAGProgrammingMode

AlongwiththeGINxpinsarealsoGOUTxoutputpinsthatcantakeupadifferentfunctiondependingonthemodeofoperation. Seetablebelowfordescription.

Multi-Purpose Pins

GIN0

Other Signal Functions

SDAT / TDI

Signal Description

I²C serial data input / JTAG serial data input

I²C clock input / JTAG clock input

GIN1

SCLK / TCK

TMS

GIN2

JTAGcontrolsignaltotheTAPcontrollerstatemachine

Suspends all outputs of PLL (Active High)

GIN3

SUSPEND

TRST

GIN4

JTAG active LOW input to asynchronously reset the BST

Reference clock select between XTALIN/REFIN and CLKIN

JTAG serial data output / Detects loss of PLL lock⁽¹⁾

Detects loss of the primary clock source⁽¹⁾

GIN5

CLK_SEL

GOUT0

GOUT1

TDO / LOSS_LOCK

LOSS_CLKIN

NOTE:

1. Please see detail description in Loss of Lock and Input Clock section.

EachPLL'sprogrammingregisterscanstoreuptofourdifferentDxandMxconfigurationsincombinationwithtwodifferent PconfigurationsinMFCmodes.

The post-divider should never be disabled in any of the two P configurations unless the output bank will never be used during normal operation. The PLL's

loopfiltersettingsalsohasfourdifferentconfigurationstostoreandselectfrom. ThiswillbeexplainedintheMODE1andMODE2sections. TheuseoftheGINx

pinsinMFCmodecontroltheselectionoftheseconfigurations.

MODE1 - Manual Frequency Control (MFC=1) Mode for PLL0 Only

In this mode, only 8 configurations of PLL0 can be changed during operation. The GIN0, GIN1 and GIN2 pins control the selection of eight different

configurations (D, M, Rz, Cz, Cp and Ip) of PLL0. GIN3 becomes PLL SUSPEND pin, GIN4 is not available to users, and GIN5 becomes CLK_SEL pin.

The output GOUT0 will become an indicator for loss of PLL lock (LOSS_LOCK). GOUT1 pin will become an indicator for loss of the primary clock

(LOSS_CLKIN).

The PLL0 has 4 sets of dedicated registers for D, M, Rz, Cz, Cp, Ip and ODIV. For additional 4 sets of registers, the PLL0 uses registers from CONFIG2

and CONFIG3 of PLL1 and PLL2. The PLL1 and PLL2 will still be fully operational, but have only one fixed configuration in this mode, and the default

configuration will be set to CONFIG0 of PLL1 and CONFIG0 of PLL2. (Please see page 18 for register location.)

TheoutputbankswilleachhavetwoPconfigurationsthatcanbeassociatedwitheachofthePLLconfigurations. EachofthetwoPconfigurationshasits

own set of PM bits (See the PRE-SCALERS, FEEDBACK-DIVIDERS, POST-DIVIDERS section for more detail on the PM bits). Use the ODIV bit to

choosewhichpost-dividerconfigurationtoassociatewithaspecificPLLconfiguration.

To enter this mode, users must set MFC bit to “1”, and I2C/JTAG pin must be left floating.

GIN2 Pin

GIN1 Pin

GIN0 Pin

PLL0 Configuration Selection (Mode 1)

0

Configuration0

0

1

0

1

0

1

0

1

0

1

0

1

Configuration1

Configuration2

Configuration3

Configuration4

Configuration5

Configuration6

Configuration7

14

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

MODE2 - Manual Frequency Control (MFC=0) Mode for all PLLs

Inthismode,theconfigurationofPLL0,PLL1,andPLL2canbechangedduringoperation. TheGINxpinsareusedtocontroltheselectionofuptofourdifferent

Dx, Mx, RZx, CZx, CPx, and IPx configurations for each PLL. GIN0 and GIN1 become configuration selection pins for D0 and M0 of PLL0, GIN2 and GIN3

becomeconfigurationselectionpinsforPLL1,andGIN4andGIN5becomeconfigurationselectionpinsforD2andM2ofPLL2. TheoutputGOUT0willbecome

an indicator for loss of PLL lock (LOSS_LOCK). GOUT1 pin will become an indicator for loss of the primary clock (LOSS_CLKIN).

TheoutputbankswillhavetwodifferentPconfigurationstochoosefromforeachofthefourPLLconfigurations. EachofthetwoPconfigurationshasitsown

setofPMbits(SeethePRE-SCALERS,FEEDBACK-DIVIDERS,POST-DIVIDERSsectionformoredetailonthePMbits). UsetheODIVbittochoosewhich

post-dividerconfigurationtoassociatewithaspecificPLLconfiguration. Forexample,ifODIV2_CONFIG2=1,thenwhenConfig2isselectedQx[9:0]_CONFIG1

isselectedasthepost-dividervaluetobeused. NotethatthereisanODIVxbitforeachofthePLLconfigurations. Inthisway,thepost-dividervaluescanchange

withtheconfiguration.

Toenterthismode, usersmustsetMFCbitto"0", andI²C/JTAGpinmustbeleftfloating.

GIN5 Pin GIN4 Pin

PLL2 Configuration Selection (Mode 2)

Configuration0

GIN1 Pin GIN0 Pin

PLL0 Configuration Selection (Mode 2)

Configuration0

0

1

0

1

0

1

0

1

0

1

0

1

Configuration1

Configuration2

Configuration3

GIN3 Pin GIN2 Pin

PLL1 Configuration Selection (Mode 2)

Configuration0

0

1

0

1

0

1

Configuration1

Configuration2

Configuration3

MODE3 - I²C Programming Mode

Inthismode,GIN0,GIN1,GIN3andGIN5becomeSDAT(I²Cdata),SCLK(I²Cclock),SUSPENDandCLK_SELsignalpins,respectively.TheoutputGOUT0

willbecomeanindicatorforlossofPLLlock(LOSS_LOCK). GOUT1pinwillbecomeanindicatorforlossoftheprimaryclock(LOSS_CLKIN). GIN2andGIN4

are not available to users.

To enter this mode, I²C/JTAGpin must be set HIGH.

MODE4 - JTAG Programming Mode

Inthismode,GIN0,GIN1,GIN2,GIN3,GIN4andGIN5willbecomeTDI(JTAGdatain),TCK(JTAGclock),TMS(JTAGcontrolsignal),SUSPEND,TRST

(JTAGreset)andCLK_SELsignalpins,respectively.TheoutputGOUT0willbecomeJTAGTDOsignal,andGOUT1willbeanindicatorforlossoftheselected

clock(LOSS_CLKIN).

Toenterthismode, I²C/JTAGpinmustbesetLOW.

Manual Frequency Control modes

Multi-Purpose pins

GIN0

Mode1

GIN0

Mode2

GIN0

JTAG

TDI

I²C

SDAT

GIN1

TCK

SCLK

GIN2

TMS

n/a

GIN3

SUSPEND

n/a

GIN3

SUSPEND

TRST

SUSPEND

n/a

GIN4

GIN5

CLK_SEL

LOSS_LOCK

LOSS_CLKIN

GIN5⁽¹⁾

CLK_SEL

TDO

CLK_SEL

LOSS_LOCK

LOSS_CLKIN

GOUT0

GOUT1

LOSS_LOCK

LOSS_CLKIN

NOTE:

1. The PLL(s) will lock onto the primary clock and the manual switchover can be controlled by the PRIMCLK bit.

15

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

Understanding the GIN Signals

During power up, the part will virtually be in MFC mode2, therefore, the values of GIN4, GIN3, GIN2, GIN1 and GIN0 will be latched and used for PLL

configurationselection,regardlessofthestateoftheI²C/JTAG pin. GIN5isnotlatched,andwillassumetheLOWstateinternallywheninprogrammingmode.

Thismeansthatwheninprogrammingmode,thePLLconfigurationcanonlybechangedbywritingdirectlytotheregistersofthecurrentlyselectedconfiguration.

WheninMFCmode2, configuration0or1(GIN5=0)shouldbeselectedifyoudonotwanttochangeconfigurationswhenenteringorleavingprogramming

mode. The GIN pins should be held LOW during power up to select configuration0 as default.

When not in programming mode, the GIN inputs directly control the selected configuration. The internal GINx signals can be individually disabled via

programmingtheGINENbits(0x06). WhendisabledbysettingGINENxto"0",theGINxinputsmaybeleftfloating,butduringpowerup,theGINpinswillstill

latch. DisabledinputsareinterpretedasLOWbytheinternalstatemachines. Evenifdisabled, GIN2, GIN1, GIN0andGIN4pinswillbeenabledifrequired

forI²CorJTAGprogrammingfunctionswheninprogrammingmode. TheSUSPENDandCLK_SELfunctionsontheGIN3andGIN5pins,respectively,will

berenderedcompletelynon-functionalwhendisabled.

SHUTDOWN/SUSPEND/ENABLEOFOUTPUTS

Thereare twoexternalpinsalongwithinternalbitsthatcontroltheenabling/disablingoftheoutputbanks. ThetwopinsaretheSHUTDOWN/OEpinand

theGIN3/SUSPENDpin. TheSHUTDOWN/OEpincanbeprogrammedtofunctionasanoutputenableorglobalshutdown. ThepolarityoftheSHUTDOWN/

OE signal pin can be programmed to be either active HIGH or LOW with the SP bit (0x1C). When SP is "0", the pin becomes active HIGH and when SP is

"1", the pin becomes active LOW. The SH bit(0x1C) determines the function of the SHUTDOWN/OE signal pin. If SH is "1", the signal pin is SHUTDOWN

and functions as a global shutdown. This will override the OEx (0x1C), OSx (0x1D), and PLLSx (0x1E) bits. If SH is "0", the signal pin is OE and functions

asanenable/disableoftheoutputbanks. Ifusedasanoutputenable/disable, eachoutputbankcanbeindividuallyprogrammedtobeenabledordisabled

bytheOEpin.bysettingOExbitsto"1". IftheOEsignalpinisasserted, theoutputbanksthathastheircorrespondingOExbitsetto"1"willbedisabled. The

OEMxbitsdeterminetheoutputs'disablestate. Whensetto"0x"theoutputswillbetristated. Whensetto"10",theoutputswillbepulledlow. Whensetto"11",

theoutputswillbepulledhigh. Invertedoutputswillbeparkedintheoppositestate. IftheOExbitsaresetto"0",thestatesofthecorrespondingoutputbanks

willnotbeimpactedbythestateoftheOEpin. Toindividuallyenable/disableviaprogramminginsteadoftheOEpin,hardwiretheOEpintoVddorGND(depending

if it is active HIGH or LOW) as if to disable the outputs. Then toggle the OEx bits to either "0" to enable or "1" to disable.

When the chip is in shutdown, the outputs, the reference oscillator, and the I²C /JTAG pin are powered down. The outputs will be tristated and the I²C

/JTAGpinwillbesettoMFCmode(MIDlevel). Programmingwillnotbeallowed. TheGINxpinsandclockinputsremainoperational. ThePLLisnotdisabled.

The SHUTDOWN pin must be reasserted in order to program the part or to resume operation.

The GIN3/SUSPEND pin, when used as a SUSPEND function, can be used to power down the PLL and/or output banks.. Each output bank can be

individuallyprogrammedtobeenabledordisabledbytheSUSPENDsignalpinbysettingtheOSxbitsto"1". IftheSUSPENDsignalpinisasserted,theoutput

banksthathastheircorrespondingOSxbitsetto"1"willbepowereddownandoutputstristated. IftheOSxbitsaresetto"0",thestatesofthecorresponding

output banks will not be impacted by the state of the SUSPEND pin. There is also an option to suspend individual PLLs by setting the PLLSx bits (0x1E) to

"1". This will associate the PLL to the SUSPEND pin. When the pin is asserted, the corresponding PLLs will be powered down. It will not only power down

the PLL but also any output bank associated with it. The PLLSx bits will override the OSx bits.

In the event of a PLL suspend, the PLL must achieve lock again after it has been re-enabled, In the event of a global shutdown, the PLL does not have

tore-acquirelocksinceitisnotdisabled.

16

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

MANUALFREQUENCYCONTROL(MFC)BLOCKDIAGRAM

OUTPUT MUX

PLL0

Prescaler "D"

CONFIG0

VCO

CONFIG1

CONFIG2

CONFIG3

Output Divider P2

CONFIG0

CONFIG1

Multiplier "M"

CONFIG0

CONFIG1

CONFIG2

CONFIG3

ODIV

Output Divider P3

CONFIG0

CONFIG1

PLL1

ODIV

Prescaler "D"

CONFIG0

CONFIG1

CONFIG2

CONFIG3

VCO

Multiplier "M"

CONFIG0

CONFIG1

CONFIG2

CONFIG3

ODIV

PLL2

Prescaler "D"

CONFIG0

CONFIG1

CONFIG2

CONFIG3

VCO

Multiplier "M"

CONFIG0

CONFIG1

CONFIG2

CONFIG3

ODIV

MFC = 0

NOTES:

This illustration shows how the configurations are arranged for each PLL. There is an ODIV bit associated with each of the four configurations.

-

GIN0 and GIN1 control four configurations from PLL0.

GIN2 and GIN3 control four configurations from PLL1.

GIN4 and GIN4 control four configurations from PLL2.

ODIV from each configuration determines the selection of two Output Divider Px Configurations.

17

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

MANUALFREQUENCYCONTROL(MFC)BLOCKDIAGRAM

OUTPUT MUX

PLL0

Prescaler "D"

CONFIG0

VCO

CONFIG1

CONFIG2

CONFIG3

Output Divider P2

CONFIG0

CONFIG1

Multiplier "M"

CONFIG0

CONFIG1

CONFIG2

CONFIG3

ODIV

Output Divider P3

CONFIG0

CONFIG1

PLL1

ODIV

Prescaler "D"

CONFIG0

VCO

CONFIG4

CONFIG5

Multiplier "M"

CONFIG0

ODIV

CONFIG4

CONFIG5

ODIV

PLL2

Prescaler "D"

CONFIG0

VCO

CONFIG6

CONFIG7

Multiplier "M"

CONFIG0

ODIV

CONFIG6

CONFIG7

ODIV

MFC = 1

NOTES:

This illustration shows how the configurations are arranged for PLL0. Register location for Config_4 and Config_5 are taken from PLL1, and Config_6 and Config_7 are taken from

PLL2. There is an ODIV bit associated with each of the configurations.

-

GIN0, GIN1, and GIN2 control eight shaded configurations for PLL0.

ODIV from each configuration determines the selection of two Output Divider Px Configurations.

18

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

BLOCKDIAGRAMFORSHUTDOWN/OECONTROLSIGNAL

OUT1

PM2

OE1

01

10

11

/2

OUT2

/2

Q2

+ 2

OE2

01

10

11

/2

OUT3

OUT4

Q3

+ 2

OE3

PM3

MUX

01

10

11

/2

Q4

+ 2

OUT4

OUT5

PM4

OE4

PM5

01

10

11

/2

Q5

+ 2

OUT5

PM6

OE5

01

10

11

/2

OUT6

/2

Q6

+ 2

OE6

OE MODE

SHUTDOWN/OE

Global SHUTDOWN Mode:

Assert to Shutdown power on the outputs

and 3-Level Pin

SP

SH

NOTE:

This illustration shows the internal logic behind the SHUTDOWN/OE pin and the bits associated with it.

19

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

POWER UP AND POWER SAVING FEATURES

If a global shutdown is enabled, SHUTDOWN pin asserted, most of the chip except for the PLLs will be powered down. In order to have a complete

power down of the chip, the PLLs must be powered down via the SUSPEND function or by setting the pre-scaler bits to '0x00' and disable the internal

GINx signals via the enable bits at memory address 0x05. Note that the register bits will not lose their state in the event of a chip power-down. The only

possibilitythattheregisterbitswilllosetheirstateisifthepartwaspower-cycled. Aftercomingoutof shutdownmode,thePLLswillrequiretimetorelock.

During power up, the values of GIN4, GIN3, GIN2, GIN1 and GIN0 will be latched and used for PLL configuration selection, regardless of the state of the

I²C/JTAG pin and GINx being disabled via the GINENx bits. GIN5 will have an internal state of LOW. The GIN pins should be held LOW during power up

toselectconfiguration0asdefault. Theoutputlevelswillbeatanundefinedstateduringpowerup.

The post-divider should never be disabled via PM bits after power up, or else it will render the output bank completely non-functional during normal

operation,(unlesstheoutputbankitselfwillnotbeusedatall).

Duringpowerup, theVDD rampmustbemonotonic.

LOSS OF LOCK AND INPUT CLOCK

Thedeviceemploysalossoflockandlossofinputclockdetectioncircuitry. TheGOUT0/LOSS_LOCKandGOUT1/LOSS_CLKINaretheoutputsthat

indicate such failures. LOSS_LOCK signal will be asserted if any of the three powered up PLLs loses frequency lock for any event other than PLL

shutdown. Lockisdeterminedbycheckingthatthereferenceandfeedbackclocksarewithin1/2periodofeachother.Loss_LOCKsignalmaybefalsely

assertedwhen

- Spread Spectrum is turned on for any of the PLLs

- Fractional divider is used for any of the PLLs

- the reference and feedback clocks are not within 1/2 period of each other.

LOSS_CLKINisassertedwhenthecurrentlyselectedclockislostorisassertedwhenbothclocksarelost. Intheeventoftheselectedclockbeing

absentuponpowerup, thelossoftheselectedclockdetectioncircuitrywillreferenceaninternaloscillator. LOSS_LOCKandLOSS_CLKINcannotbe

usedasreliableinputstootherdevices.

SWITCHOVERMODES

TheIDT5V9885TfeaturesredundantclockinputswhichsupportsbothAutomaticandManualswitchovermode. Thesetwomodesaredeterminedby

the configuration bits, SM (0x34). The primary clock source can be programmed, via the PRIMCLK bit, to be either XTALIN/REFIN or CLKIN, which is

determined by the PRIMCLK bit. The other clock source input will be considered as the secondary source. This is more detailed in the 'REFERENCE

CLOCK INPUT PINS AND SELECTION'. Note that the switchover modes are asynchronous. If the reference clocks are directly routed to OUTx with no

phase relationship, short pulses can be generated during switchover. The automatic switchover mode will work only when the primary clock source is

XTALIN/REFIN.

MANUAL SWITCHOVER MODE

When SM[1:0] is "0x", the redundant inputs are in manual switchover mode. In this mode, CLK_SEL pin is used to switch between the primary and

secondaryclocksources. Aspreviouslymentioned, theprimaryandsecondaryclocksourcesettingisdeterminedbythePRIMCLKbit. Duringthe

switchover, no glitches will occur at the output of the device, although there may be frequency and phase drift, depending on the exact phase and

frequencyrelationshipbetweentheprimaryandsecondaryclocks. IfGOUT1isusedasLOSS_CLKIN, itindicateslossofprimaryclock.

AUTOMATICSWITCHOVERMODE

WhenSM[1:0]is"11", theredundantinputsareinautomaticrevertiveswitchovermode.

20

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

Revertive

Theinputclockselectionwillswitchtothesecondaryclocksourcewhentherearenotransitionsontheprimaryclocksource. LOSS_CLKINsignalswill

beasserted. Afterastableandvalidprimaryclocksourceispresent,theinputclockselectionwillautomaticallyswitchbacktotheprimaryclocksourceand

LOSS_CLKINsignalwillbedeasserted.TheCLK_SELpincanbeleftfloatinginthisauto-revertivemode.Notethatbothclockinputsmustbeatthesame

frequency(within1000ppm)inorderfortheauto-revertiveswitchovertofunctionproperly. Ifbothreferenceclocksareatdifferentfrequencies, thedevice

willalwaysremainontheprimaryclockunlessitisabsentfortwosecondaryclockcycles.

CLOCK SWITCH MATRIX AND OUTPUTS

All three PLL outputs and the currently selected input clock source are routed into and through a clock matrix. The user is able to select which PLL output

and clock source is routed to which output bank via the SRCx bits (0x34, 0x35). Each output bank has its own set of SRC bits. Refer to the RAM table for

moreinformation. NotethatOUT1willbebasedoffthereferenceclockandtheonlyoutputbanktogglingunderthedefaultRAMbitsettings.

Outputs 1, 2 and 3 are 3.3V LVTTL. Outputs banks 4 and 5 can be 3.3V LVTTL, LVPECL or LVDS. The LVDS and LVPECL selection is determined

by the LVLx bits (0x54, 0x58). Each output bank has individual slew-rate control (SLEWx bits). Each output can be individually inverted (INVx bits);

when using LVPECL or LVDS modes, one of the outputs in each LVPECL/LVDS pair should be inverted. All output banks except OUT1 have a

programmable10-bitpost-divider(Qxbits)withtwoselectabledivideconfigurationsviatheODIVxbits.

There are four settings for the programmable slew rate, 0.7V/ns, 1.25V/ns, 2V/ns, and 2.75V/ns; this only applies to the 3.3V LVTTL outputs. The

differentialoutputsarenotslewrateprogrammable inLVPECLorLVDSmodes. SLEW4and/orSLEW5mustbesetto2.75V/nsforstableoutputoperation

. For LVTTL output frequency rates higher than 100MHz, a slew rate of 2V/ns or greater should be selected. The post-dividers can be disabled using

the PMx bit, which is described in the PRE-SCALER, FEEDBACK-DIVIDER, AND POST-DIVIDER section. Each output can also be enabled/disabled,

whichisdescribedinthe'SHUTDOWN/SUSPEND/ENABLEof OUTPUTS'section. RefertotheRAMtableforallbinarysettings.

HIGH LEVEL BLOCK DIAGRAM FOR CONFIGURATION SCHEME

I/Os

Non-Volatile

Configuration

PLLs and Control

Blocks

EEPROM

Cell

Volatile

Configuration

I ²C or JTAG

interface

Write Enable

Programming

Interface Block

NOTE: Diagram does not represent actual number of die on chip.

21

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

PROGRAMMINGTHEDEVICE

I²CandJTAGmaybeusedtoprogramthe5V9885T. TheI²C/JTAGpinselectstheI²CwhenHIGHandJTAGwhenLOW. Notethatthe TRSTpinneeds

to be LOW for I²C mode.

Hardwired Parameters for the IDT5V9885T

JTAGidentificationnumber=32'b0000_0000001110101100_00000110011_1

Device (slave) address = 7'b1101010

ID Byte for the 5V9885T = 8'b00010000

I²C PROGRAMMING

The5V9885TisprogrammedthroughanI²C-Busserialinterface, andisanI²Cslavedevice. Thereadandwritetransferformatsaresupported. Thefirst

byteofdataafterawriteframetothecorrectslaveaddressisinterpretedastheregisteraddress;thisaddressauto-incrementsaftereachbytewrittenorread.

Theframeformatsareshownbelow.

SDA

SCL

P

S

Data Frame

Data is stable during

clock HIGH

Stop

Condition

Start

Condition

Figure 1: Framing

Each frame starts with a "Start Condition" and ends with an "End Condition". These are both generated by the Master device.

MSB

1

LSB

1

0

1

0

1

0

R/W

7-bit slave address

R/W

0 - Slave will be written by master

1 - Slave will be read by master

ACK from Slave

The first byte transmitted by the Master is the Slave Address followed by the R/W bit.

The Slave acknowledges by sending a "1" bit.

Figure 2: First Byte Transmittetd on I²C Bus

22

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

EXTERNAL I²C INTERFACE CONDITION

KEY:

From Master to Slave

FromMastertoSlave, butcanbeomittediffollowedbythecorrectsequence

NormallydatatransferisterminatedbyaSTOPconditiongeneratedbytheMaster. However,iftheMasterstillwishestocommunicateonthebus,itcan

generatearepeatedSTARTcondition, andaddressanotherSlaveaddresswithoutfirstgeneratingaSTOPcondition.

From Slave to Master

SYMBOLS:

ACK - Acknowledge (SDA LOW)

NACK - Not Acknowledge (SDA HIGH)

Sr-RepeatedStartCondition

S - START Condition

P - STOP Condition

PROGWRITE

S

Address R/W ACK Command Code ACK Register ACK Data ACK

7-bits 1-bit 8-bits: xxxxxx00 1-bit 8-bits 1-bit 8-bits 1-bit

P

0

Figure 3: Progwrite Command Frame

WritescancontinueaslongasaStopconditionisnotsentandeachbytewillincrementtheregisteraddress.

PROGREAD

Note: If the expected read command is not from the next higher register to the previous read or write command, then set a known "read" register address

priortoareadoperationbyissuingthefollowingcommand:

S

Address R/W ACK Command Code ACK Register ACK

7-bits 1-bit 8-bits: xxxxxx00 1-bit 8-bits 1-bit

P

0

Figure 4a: Prior to Progread Command Set Register Address

TheusercanignoretheSTOPconditionaboveandusearepeatedSTARTconditioninstead,straightaftertheslaveacknowledgementbit(i.e.,followedby

theProgreadcommand):

Data_1

8-bits

Data_2

8-bits

Data_last

8-bits

P

Sr Address R/W ACK ID Byte ACK

7-bits 1-bit 8 bits

ACK

1-bit

ACK

1-bit

NACK

1-bit

1

1-bit

Figure 4b: Progread Command Frame

Note:Figure4babovebyitselfistheProgreadcommandformat. TheIDbyteforthe5V9885Tis10hex. Eachbyterecievedincrementstheregisteraddress.

23

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

PROGSAVE

JTAGINSTRUCTIONREGISTER

DESCRIPTION

P

S

Address R/W ACK Command Code ACK

7-bits 1-bit 8-bits:xxxxxx01 1-bit

IR (3)

IR (2)

IR (1)

IR (0)

Instructions

EXTEST⁽¹⁾

SAMPLE/PRELOAD⁽¹⁾

IDCODE⁽¹⁾

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NOTE:

PROGWRITE is for writing to the 5V9885T registers.

PROGREAD is for reading the 5V9885T registers.

PROGSAVE is for saving all the contents of the 5V9885T registers to the EEPROM.

PROGRESTORE is for loading the entire EEPROM contents to the 5V9885T registers.

REGADDR⁽²⁾

REGDATAW / PROGWRITE⁽³⁾

REGDATAR / PROGREAD⁽⁴⁾

PROGSAVE⁽⁵⁾

PROGRESTORE⁽⁶⁾

CLAMP⁽¹⁾

HIGHZ^(1,7)

BYPASS⁽¹⁾

PROGRESTORE

P

S

Address R/W ACK Command Code ACK

7-bits 1-bit 8-bits:xxxxxx10 1-bit

NOTES:

0

1. IEEE 1149.1 definition

2. REGADDR is for setting a specific 5V9885T register address.

3. REGDATAW/PROGWRITE is for writing to the 5V9885T registers.

4. REGDATAR/PROGREAD is for reading the 5V9885T registers.

JTAGINTERFACE

5. PROGSAVE is for saving all the contents of the 5V9885T registers to the EEPROM.

6. PROGRESTORE is for loading the entire EEPROM contents to the 5V9885T registers.

7. The OEMs bits for OUT1-6 must be set for tri-state when using the HIGHZ instruction

InadditiontotheIEEE1149.1instructionsEXTEST,SAMPLE/PRELOAD,

CLAMP, HIGH-Z and BYPASS, the 5V9885T allows access to internal

programmingregistersusingtheREGADDR(setregisteraddress),REGDATAR

(read register) and REGDATW (write register instructions. Data is always

accessedbybyte,andtheregisteraddressincrementsaftereachreadorwrite.

Thefullinstructionsetfollows. TheIDT5V9885Twillbeupdatingtheregisters

duringprogramming.

The JTAG TAP controller can be reset in one of four ways:

1) Power up in JTAG mode

2) PowerupinI²CmodeandthengointoJTAGmode,orgooutofandback

intoJTAGmodewiththeI²C/JTAGpin

3) Apply TRST while in JTAG mode

4) Apply five rising edges of TCK with TMS high while in JTAG mode

EEPROMINTERFACE

TheIDT5V9885TcanalsostoreitsconfigurationinaninternalEEPROM. Thecontentsofthedevice'sinternalprogrammingregisterscanbesavedtothe

EEPROMbyissuingasaveinstruction(ProgSave)andcanbeloadedbacktotheinternalprogrammingregistersbyissuingarestoreinstruction(ProgRestore).

ToinitiateasaveorrestoreusingI²C,onlytwobytesaretransferred.TheDeviceAddressisissuedwiththeread/writebitsetto"0",followedbytheappropriate

commandcode.ThesaveorrestoreinstructionexecutesaftertheSTOPconditionisissuedbytheMaster,duringwhichtimetheIDT5V9885Twillnotgenerate

Acknowledgebits. TheIDT5V9885Twillacknowledgetheinstructionsafterithascompletedexecutionofthem. Duringthattime,theI²Cbusshouldbeinterpreted

as busy by all other users of the bus.

UsingJTAG,theProgSaveandProgRestoreinstructionsselectstheBYPASSregisterpathforshiftingthedatafromTDItoTDOduringthedataregisterscanning.

DuringtheexecutionofaProgSaveorProgRestoreinstruction,theIDT5V9885Twillnotacceptanewprogramminginstruction(read,write,save,orrestore).

Allnon-programmingJTAGinstructionswillfunctionproperly,buttheusershouldwaituntilthesaveorrestoreiscompletebeforeissuinganewprogramming

instruction. Ifanewprogramminginstructionisissuedbeforethesaveorrestorecompletes,thenewinstructionisignored,andtheBYPASSregisterpathremains

ineffectforshiftingdatafromTDItoTDOduringdataregisterscanning.

Thetimeittakesforthesave(TSAVE)andrestore(TRESTORE)instructionstocompleteis:

TSAVE = 100ms max, TRESTORE = 10 ms max

24

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

Inorderforthesaveandrestoreinstructionstofunctionproperly,theIDT5V9885Tmustnotbeinshutdownmode(SHUTDOWNpinasserted). Intheevent

ofaninterruptofsomesortsuchasapowerdownofthepartinthemiddleofasaveorrestoreoperation,thecontentstoorfromtheEEPROMwillbepartially

loaded, and a CRC error will be generated. The CERR bit (0x81) will be asserted to indicate that an error has occurred. The LOSS_LOCK signal will also

beasserted.

Onpower-upoftheIDT5V9885T,anautomaticrestoreisperformedtoloadtheEEPROMcontentsintotheinternalprogrammingregisters. Theauto-restore

willnotfunctionproperlyifthedeviceisinshutdownmode(SHUTDOWNpinasserted). TheIDT5V9885Twillbereadytoacceptaprogramminginstruction

onceitacknowledgesits7-bitI²Caddress.

tTCLK

t4

t2

t1

TCLK

t3

TDI/TMS

tDS

tDH

TDO

tDO

t6

TRST

t5

Standard JTAG Timing

NOTE:

t1 = tTCLKLOW

t2 = tTCLKHIGH

t3 = tTCLKFALL

t4 = tTCLKRISE

t5 = tRST (reset pulse width)

t6 = tRSR (reset recovery)

JTAG

SYSTEMINTERFACEPARAMETERS

ACELECTRICALCHARACTERISTICS

Symbol

Parameter

DataOutput⁽¹⁾

Min.

Max.

Units

tDO

—

20

ns

Symbol

Parameter

Min.

100

40

Max.

Units

tDOH

tDS

DataOutputHold⁽¹⁾

DataInput, tRISE =3ns

DataInput, tFALL =3ns

0

—

ns

tTCLK

JTAG Clock Input Period

JTAG Clock HIGH

JTAG Clock Low

—

ns

10

—

ns

tTCLKHIGH

tTCLKLOW

tTCLKRISE

tTCLKFALL

tRST

—

ns

tDH

10

—

ns

40

—

ns

JTAG Clock Rise Time

JTAG Clock Fall Time

JTAGReset

—

5⁽¹⁾

—

ns

NOTE:

1. 50pF loading on external output signals.

—

ns

50

ns

tRSR

JTAG Reset Recovery

50

—

ns

NOTE:

1. Guaranteed by design.

25

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

I²C BUS DC CHARACTERISTICS

Symbol

VIH

Parameter

Conditions

Min

Typ

Max

Unit

V

Input HIGH Level

InputLOWLevel

Hysteresis of Inputs

InputLeakageCurrent

OutputLOWVoltage

0.7 * VDD

VIL

0.3 * VDD

V

VHYS

IIN

0.05 * VDD

V

±1.0

0.4

µA

V

VOL

IOL = 3 mA

I²C BUS AC CHARACTERISTICS FOR STANDARD MODE

Symbol

FSCLK

tBUF

Parameter

Min

0

Typ

Max

Unit

KHz

µs

ns

Serial Clock Frequency (SCLK)

Bus free time between STOP and START

SetupTime,START

100

4.7

4

tSU:START

tHD:START

tSU:DATA

tHD:DATA

tOVD

HoldTime, START

SetupTime,datainput(SDAT)

HoldTime, datainput(SDAT)⁽¹⁾

Outputdatavalidfromclock

Capacitive Load for Each Bus Line

Rise Time, data and clock (SDAT, SCLK)

Fall Time, data and clock (SDAT, SCLK)

HIGH Time, clock (SCLK)

LOW Time, clock (SCLK)

250

0

µs

pF

3.45

400

CB

tR

1000

300

ns

tF

ns

tHIGH

4

4.7

4

µs

tLOW

tSU:STOP

SetupTime, STOP

NOTE:

1. A device must internally provide a hold time of at least 300ns for the SDAT signal (referred to the VIHMIN of the SCLK signal) to bridge the undefined region of the falling edge

of SCLK.

I²C BUS AC CHARACTERISTICS FOR FAST MODE

Symbol

FSCLK

tBUF

Parameter

Min

0

Typ

Max

Unit

KHz

µs

ns

Serial Clock Frequency (SCLK)

Bus free time between STOP and START

SetupTime,START

400

1.3

0.6

100

0

tSU:START

tHD:START

tSU:DATA

tHD:DATA

tOVD

HoldTime, START

SetupTime,datainput(SDAT)

HoldTime, datainput(SDAT)⁽¹⁾

Outputdatavalidfromclock

Capacitive Load for Each Bus Line

Rise Time, data and clock (SDAT, SCLK)

Fall Time, data and clock (SDAT, SCLK)

HIGH Time, clock (SCLK)

LOW Time, clock (SCLK)

µs

pF

0.9

400

300

CB

tR

20 + 0.1 * CB

ns

tF

20 + 0.1 * CB

ns

tHIGH

0.6

1.3

0.6

µs

tLOW

tSU:STOP

SetupTime, STOP

NOTE:

1. A device must internally provide a hold time of at least 300ns for the SDAT signal (referred to the VIHMIN of the SCLK signal) to bridge the undefined region of the falling edge

of SCLK.

26

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

Symbol

VDD

Description

Internal Power Supply Voltage

Input Voltage

Max

-0.5 to +4.6

-0.5 to VDD + 0.5

150

Unit

V

VI

V

VO

Output Voltage⁽²⁾

V

TJ

Junction Temperature

Storage Temperature

°C

TSTG

–65 to +150

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. Not to exceed 4.6V.

(1)

CAPACITANCE (TA = +25°C, f = 1MHz, VIN = 0V)

Symbol

Parameter

Min.

Typ.

Max.

Unit

CIN

Input Capacitance

—

4

—

pF

Crystal Specifications

XTAL_FREQ

XTAL_MIN

XTAL_MAX

Crystal Frequency

8

—

3.5

50

—

MHz

pF

Minimum Crystal Load Capacitance

Maximum Crystal Load Capacitance

Crystal Load Capacitance Resolution

Voltage Swing (peak-to-peak, nominal)

—

35.4

0.125

2.3

pF

XTAL_VPP

V

NOTE:

1. Capacitance levels characterized but not tested.

RECOMMENDEDOPERATINGCONDITIONS

Symbol

Description

Min.

3

Typ.

Max.

Unit

VDD

PowerSupplyVoltageforLVTTL

Power Supply Voltage for LVDS/LVPECL

OperatingTemperature,Ambient

MaximumLoadCapacitance(LVTTLonly)

ExternalReferenceCrystal

3.3

—

3.6

3.465

+85

15

V

3.135

–40

—

TA

CLOAD_OUT

FIN

°C

pF

8

50

MHz

ExternalReferenceClock,Industrial

1

400

5

tPU

Power-uptimeforallVDDstoreachminimumspecifiedvoltage

(powerrampsmustbemonotonic)

0.05

ms

27

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

Symbol

VIHH

Parameter

Test Conditions

I²C/JTAG 3-Level Input

Min.

Typ.

—

Max.

Unit

V

Input HIGH Voltage Level⁽¹⁾

Input MID Voltage Level⁽¹⁾

InputLOWVoltageLevel⁽¹⁾

VDD – 0.4

—

VIMM

I²C/JTAG 3-Level Input

VIN = VDD

VDD/2 – 0.2

—

VDD/2 + 0.2

V

VILL

—

0.4

200

+50

—

V

HIGH Level

MID Level

LOW Level

—

I3

3-LevelInputDCCurrent

VIN = VDD/2

–50

–200

—

µA

mA

VIN = GND

—

IDD

IDDS

TotalPowerSupplyCurrent

(3.3V Supply, VDD)

2 outputs @166MHz; 4 outputs @ 83MHz

2 outputs @20MHz; 4 outputs @ 40MHz

120

40

—

Total Power Supply Current in

ShutdownMode⁽²⁾

GlobalShutdownMode

—

2

—

(PLLs, dividers, outputs, etc. powereddown)

NOTES:

1. These inputs are normally wired to VDD, GND, or left floating. If these inputs are switched dynamically after powerup, the function and timing of the outputs may be glitched, and

the PLL may require additional tAQ time before all datasheet limits are achieved.

2. Dividers must reload reprogrammed values via power-on reset or terminal count reload in order to ensure low-power mode.

DCELECTRICALCHARACTERISTICSFOR3.3VLVTTL⁽¹⁾

Symbol

IOH

Parameter

Output HIGH Current

OutputLOWCurrent

Input Voltage HIGH

InputVoltageLOW

Test Conditions

Min.

12

2

Typ.

24

Max.

—

Unit

mA

V

VOH = VDD - 0.5, VDD = 3.3V ± 0.3V

VOL = 0.5V, VDD = 3.3V ± 0.3V

IOL

24

—

VIH

—

VIL

—

0.8

10

V

IIH

Input HIGH Current⁽²)

VIN = VDD

VIN = 0V

—

µA

IIL

InputLOWCurrent

—

10

IOZD

OutputLeakageCurrent

3-stateoutputs

—

10

NOTES:

1. See RECOMMENDED OPERATING RANGE table.

2. IIH specification does not apply to inputs with internal pull-down.

POWERSUPPLYCHARACTERISTICSFORLVTTLOUTPUTS

Symbol

Parameter

Test Conditions

REF = LOW

Typ.

Max

Unit

IDDQ

Quiescent VDD Power Supply Current

6

12

mA

Outputsenabled,Alloutputsunloaded

VDD = Max., CL = 0pF

IDDD

ITOT

Dynamic VDD Power Supply

CurrentperOutput

40

60

µA/MHz

FREFERENCE CLOCK = 33MHz, CL = 15pf

FREFERENCE CLOCK = 133MHz, CL = 15pf

FREFERENCE CLOCK = 200MHz, CL = 15pf

26

80

40

Total Power VDD Supply Current

120

170

mA

112

28

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

DCELECTRICALCHARACTERISTICSFORLVDS

Symbol

VOT (+)

VOT (-)

∆ VOT

VOS

Parameter

Min.

247

-247

—

Typ.

—

1.2

—

9

Max

454

-454

50

Unit

mV

V

DifferentialOutputVoltagefortheTRUEbinarystate

DifferentialOutputVoltagefortheFALSEbinarystate

ChangeinVOTbetweenComplimentaryOutputStates

OutputCommonModeVoltage(OffsetVoltage)

ChangeinVOS betweenComplimentaryOutputStates

Outputs Short Circuit Current, VOUT+ or VOUT- = 0V or VDD

DifferentialOutputsShortCircuitCurrent,VOUT+=VOUT-

1.125

—

1.375

50

∆ VOS

IOS

mV

mA

—

24

IOSD

—

6

12

POWERSUPPLYCHARACTERISTICSFORLVDSOUTPUTS⁽¹⁾

Symbol

Parameter

Test Conditions⁽²⁾

REF = LOW

Typ.

Max

Unit

IDDQ

Quiescent VDD Power Supply Current

68

90

mA

Outputsenabled,Alloutputsunloaded

VDD = Max., CL = 0pF

IDDD

ITOT

Dynamic VDD Power Supply

CurrentperOutput

30

45

µA/MHz

FREFERENCE CLOCK = 100MHz, CL = 5pf

FREFERENCE CLOCK = 200MHz, CL = 5pf

FREFERENCE CLOCK = 400MHz, CL = 5pf

86

130

150

190

Total Power VDD Supply Current

100

122

mA

NOTES:

1. Output banks 4 and 5 are toggling. Other output banks are powered down.

2. The termination resistors are excluded from these measurements.

DCELECTRICALCHARACTERISTICSFORLVPECL

Symbol

VOH

Parameter

Min.

VDD - 1.2

VDD - 1.95

0.55

Typ.

—

Max

VDD - 0.9

VDD - 1.61

0.93

Unit

V

Output Voltage HIGH, terminated through 50Ωtied to VDD - 2V

OutputVoltageLOW, terminatedthrough50ΩtiedtoVDD -2V

Peak to Peak Output Voltage Swing

VOL

—

V

VSWING

—

V

POWERSUPPLYCHARACTERISTICSFORLVPECLOUTPUTS⁽¹⁾

Symbol

Parameter

Test Conditions⁽²⁾

REF = LOW

Typ.

Max

Unit

IDDQ

Quiescent VDD

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