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产品型号6SVP820M的概述

芯片6SVP820M的概述 芯片6SVP820M是一款广泛应用于电子设备中的高性能微控制器,主要用于数据处理和控制功能。随着现代科技的发展,对高效、低功耗的微控制器需求日益增加,6SVP820M以其卓越的性能和灵活的结构,成为各类电子系统的重要组成部分。 这种芯片的设计旨在满足复杂应用的需要。它支持多种通信协议,使其在物联网设备、工业自动化、汽车电子等领域具有广泛的适用性。其核心功能包括数据采集、信号处理、以及对外部设备的控制。 芯片6SVP820M的详细参数 6SVP820M的详细参数包括但不限于: - 工作电压:2.4到5.5V,适应多种电源环境 - 工作频率:主频高达80MHz,确保快速的数据处理能力 - 存储器:包括256KB的闪存和64KB的SRAM,满足大部分应用需求 - GPIO引脚:最多可支持32个通用输入输出引脚,可以灵活配置 - ADC模块:内置12位的模数转换器(...

产品型号6SVP820M的Datasheet PDF文件预览

PTH04040W  
www.ti.com  
SLTS238ASEPTEMBER 2005REVISED FEBRUARY 2006  
60-A, 3.3/5-V INPUT, NONISOLATED WIDE-OUTPUT  
ADJUST POWER MODULE  
FEATURES  
APPLICATIONS  
Advanced Computing and Server Applications  
60-A Output Current  
3.3-V and 5-V Input Voltage  
Wide-Output Voltage Adjust (0.8 V to 2.5 V)  
Efficiencies up to 93%  
On/Off Inhibit  
Differential Output Sense  
Output Overcurrent Protection  
(Nonlatching, Auto-Reset)  
Overtemperature Protection  
Auto-Track™ Sequencing  
Start Up Into Output Prebias  
Margin Up/Down Controls  
Operating Temperature: –40°C to 85°C  
Multi-Phase, Switch-Mode Topology  
Programmable Undervoltage Lockout (UVLO)  
NOMINAL SIZE =  
2.05 in x 1.05 in  
(52 mm x 26,7 mm)  
Safety Agency Approvals: UL/cUL 60950,  
EN60950, VDE (Pending)  
DESCRIPTION  
The PTH04040W is a high-performance 60-A rated, nonisolated, power module, which uses the latest  
multi-phase switched-mode topology. This provides a small, ready-to-use module, that can power the most  
densely populated multiprocessor systems.  
The PTH04040W operates over an input voltage range of 2.95 V to 5.5 V, and can be set to any output voltage  
over the range, 0.8 V to 2.5 V, using a single external resistor. The combination of a wide input voltage and  
wide-output adjust range allows the PTH04040W to be used in many of high-performance applications. These  
include advanced computing platforms and servers that utilize either a 3.3-V or 5-V distribution bus.  
These modules incorporate a comprehensive list of features. They include an on/off inhibit and margin up/down  
controls. A differential remote output voltage sense ensures tight load regulation, and an output overcurrent and  
overtemperature shutdown protect against most load faults. A programmable undervoltage lockout allows the  
turn-on threshold to be customized.  
The PTH04040W incorporates Auto-Track™. Auto-Track is a popular feature of the PTH family that allows the  
outputs of multiple modules to track a common voltage during power-up and power-down transitions. This greatly  
simplifies the sequencing of voltages for VLSI ICs that operate off multiple power rails.  
The double-sided surface mount construction has a low profile and compact footprint. It is available in both  
throughhole and surface-mount packages.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Auto-Track, POLA, TMS320 are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2005–2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
PTH04040W  
www.ti.com  
SLTS238ASEPTEMBER 2005REVISED FEBRUARY 2006  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
STANDARD APPLICATION  
19  
20  
18  
11  
9
Margin  
Up  
Margin  
Down  
Track  
+Sense  
2
V
I
V
I
4
6
8
12  
V
O
PTH04040W  
Vo  
15  
14  
+
UVLO  
−Sense  
C
C
Inhibit  
GND  
GND  
10 13  
VoAdj  
+
+
C
I
A
7
1
3
5
16 17  
R
1000 µF  
(Required)  
C 1  
O
330 µF  
C 2  
O
330 µF  
SET  
B
1%  
0.05 W  
UDG−05085  
A. For CI, a minimum of 1,000 µF (or 2 × 470 µF) of input capacitance is required for proper operation.  
B. RSET is required to set the desired output voltage from the module higher than the minimum value.  
C. For CO1 and CO2, a minimum of 660 µF (or 2 × 330 µF) of input capacitance is required load transient regulation.  
ORDERING INFORMATION  
For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see  
the TI website at www.ti.com.  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range (unless otherwise noted)  
UNIT  
Signal input voltages  
Track control (pin 18)  
–0.3 V to VI + 0.3 V  
TA  
Operating temperature range over VI range  
–40°C to 85°C  
(1)  
Wave solder  
temperature  
Surface temperature of module body or pins (5  
seconds)  
PTH04040WAH  
260°C  
Twave  
(1)  
PTH04040WAS  
PTH04040WAZ  
235°C  
Solder reflow  
temperature  
Treflow  
TS  
Surface temperature of module body or pins  
(1)  
260°C  
Storage temperature  
Mechanical shock  
Mechanical vibration  
Weight  
–40°C to 125°C  
500 G(2)  
Per Mil-STD-883D, Method 2002.3, 1 msec, 1/2 Sine, mounted  
Mil-STD-883D, Method 2007.2, 20–2000 Hz  
10 G(2)  
22.5 grams  
Flammability  
Meets UL94V-O  
(1) During soldering of package version, do not elevate peak temperature of the module, pins or internal components above the stated  
maximum.  
(2) Qualification limits  
2
Submit Documentation Feedback  
PTH04040W  
www.ti.com  
SLTS238ASEPTEMBER 2005REVISED FEBRUARY 2006  
ELECTRICAL CHARACTERISTICS  
TA = 25°C, VI = 5 V, VO = 2.5 V, CI = 1000 µF, CO = 660 µF, and IO = IOmax (unless otherwise stated)  
PARAMETER  
Output current  
TEST CONDITIONS  
MIN  
0
TYP  
MAX UNIT  
IO  
60°C, 200 LFM airflow  
60(1)  
5.5  
A
VI  
Input voltage range  
Set-point voltage tolerance  
Temperature variation  
Line regulation  
Over IO range  
2.95(2)  
V
VOtol  
±2(3)  
%VO  
%VO  
mV  
mV  
%VO  
Regtemp  
Regline  
Regload  
Regtot  
–40°C < TA < 85°C  
Over VI range  
±0.5  
±5  
Load regulation  
Over IO range  
±5  
Total output variation  
Includes set-point, line, load, –40°C TA 85°C  
2.95 VI 4.5 V(3)  
±3(3)  
1.65  
2.5  
0.8  
0.8  
-
-
VO, ADJ  
Output adjust range  
V
4.5 VI 5.5 V(3)  
RSET = 2.21 k, VO = 2.5 V  
RSET = 5.49 k, VO = 1.8 V  
RSET = 8.87 k, VO = 1.5 V  
RSET = 17.4 k, VO = 1.2 V  
RSET = 6.92 k, VO = 1.65 V  
RSET = 8.87 k, VO = 1.5 V  
RSET = 36.5 k, VO = 1 V  
All voltages  
93%  
90%  
88%  
86%  
92%  
91%  
87%  
15  
VI = 5 V, IO = 45 A  
η
Efficiency  
VI = 3.3 V, IO = 45 A  
VR  
VO ripple (peak-to-peak)  
Overcurrent threshold  
Transient response  
20-MHz bandwidth  
mVPP  
A
IOtrip  
Reset, followed by auto-recovery  
90  
1 A/µs load step, 50 to 100% IOmax, CO = 660 µF  
trr  
Recovery time  
VO over/undershoot  
100  
200  
µS  
mV  
%
Vtr  
Margin up down adjust  
Margin input current  
From a given set-point voltage  
Pin to GND  
±5%  
–8(4)  
IILmargin  
IILtrack  
dV/dt  
µA  
Track input current (pin 18)  
Track slew rate capability  
Undervoltage lockout  
Pin to GND  
–0.11(5)  
1
mA  
V/ms  
|VTRACK – VO | 50 mV and V(TRACK) < VO(nom)  
UVLO  
Pin 8 open  
On-threshold  
Hysterisis  
2.6(6)  
0.6(6)  
V
Inhibit control (pin 7)  
Input high voltage  
Referenced to GND  
VIH  
2.5  
Open(5)  
0.5  
V
VIL  
Input low voltage  
–0.2  
IILinhibit  
IIinh  
f s  
Input low current  
Pin to GND  
0.5  
60  
mA  
mA  
kHz  
µF  
Input standby current  
Switching frequency  
External input capacitance  
Inhibit (pin 7) to GND  
Over VI and IO ranges  
675  
825  
975  
CI  
940(7)  
(1) See SOA curves or consult factory for appropriate derating.  
(2) The nominal input voltage must be at least 2 × VO. Output voltage regulation is guaranteed with an input voltage within ±10% from  
nominal 3.3 V or 5 V. For example, for VI = 5 V and VO = 2.5 V, the input can vary between 4.5 V and 5.5 V.  
(3) The set-point voltage tolerance is affected by the tolerance of RSET. The stated limit is unconditionally met if RSET has a tolerance of 1%  
with 100 ppm/°C or better temperature stability.  
(4) A small, low-leakage (<100 nA) MOSFET is recommended to control this pin. The open-circuit voltage is less than 1 Vdc.  
(5) This control pin has an internal pull-up to VI. If it is left open-circuit the module operates when input power is applied. A small,  
low-leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. Do not place an external  
pull-up on this pin. See the Application Information section for further guidance.  
(6) These are the default voltages. They may be adjusted using the UVLO Prog control input. See the Application Information section for  
further guidance.  
(7) A minimum capacitance of 940 µF is required at the input for proper operation. The capacitance must be rated for a minimum of 400  
mArms of ripple current.  
3
Submit Documentation Feedback  
PTH04040W  
www.ti.com  
SLTS238ASEPTEMBER 2005REVISED FEBRUARY 2006  
ELECTRICAL CHARACTERISTICS (continued)  
TA = 25°C, VI = 5 V, VO = 2.5 V, CI = 1000 µF, CO = 660 µF, and IO = IOmax (unless otherwise stated)  
PARAMETER  
External output capacitance  
Reliability  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
Nonceramic  
Ceramic  
660(8)  
14000(9)  
µF  
Capacitance value  
CO  
400  
Equivalent series resistance (nonceramic)  
Per Bellcore TR-332 50% stress, TA = 40°C, ground benign  
2(10)  
2.1  
mΩ  
106Hrs  
MTBF  
(8) A minimum value of output capacitance is required for proper operation. Adding additional capacitance at the load will further improve  
transient response.  
(9) This is the calculated maximum. The minimum ESR requirement often results in a lower value. See the Application Information section  
for further guidance.  
(10) This is the typcial ESR for all the electrolytic (nonceramic) output capacitance. Use 4 mas the minimum when using max-ESR values  
to calculate.  
4
Submit Documentation Feedback  
PTH04040W  
www.ti.com  
SLTS238ASEPTEMBER 2005REVISED FEBRUARY 2006  
DEVICE INFORMATION  
TERMINAL FUNCTIONS  
TERMINAL  
DESCRIPTION  
NAME  
NO.  
1, 3, 5, 10, 13, This is the common ground connection for the VI and VO power connections. It is also the 0 Vdc  
GND  
16  
reference for the control inputs.  
VI  
2, 4, 6  
9, 12, 15  
The positive input voltage power node to the module, which is referenced to common GND.  
The regulated positive power output with respect to the GND node.  
VO  
The Inhibit pin is an open-collector/drain negative logic input that is referenced to GND. Applying a  
lowlevel ground signal to this input disables the module’s output and turns off the output voltage. When  
the Inhibit control is active, the input current drawn by the regulator is significantly reduced. If the Inhibit  
pin is left open-circuit, the module produces an output whenever a valid input source is applied. Do not  
place an external pull-up on this pin.  
Inhibit(1)  
7
A 1%, 0.05-W resistor must be connected between this pin and GND to set the output voltage higher  
than the minimum value. The set-point range for the output voltage is from 0.8 V to 2.5 V. The resistor  
required for a given output voltage may be calculated from the following formula. If left open circuit, the  
module output defaults to its lowest output voltage value. For further information on the adjustment  
and/or trimming of the output voltage, see the related Application Information section. Note: The  
specification table gives the preferred resistor values for a number of standard output voltages.  
VO Adjust  
17  
The sense inputs allow the regulation circuit to compensate for voltage drop between the module and  
the load. For optimal voltage accuracy, +Sense should be connected to VO. If it is left open, a low-value  
internal resistor ensures that the output remains in regulation.  
+Sense  
–Sense  
11  
14  
For optimal voltage accuracy, –Sense should be connected to the ground return at the load. If it is left  
open, a low-value internal resistor ensures that the output remains in regulation.  
Connecting a resistor from this pin to signal ground allows the on threshold of the input undervoltage  
lockout (UVLO) to be adjusted higher than the default value. The hysterisis can also be independenly  
reduced by connecting a second resistor from this pin to VI. For further information, see the Application  
Information section.  
UVLO Prog  
Track  
8
This is an analog control input that allows the output voltage to follow another voltage during power up  
and power down sequences. The pin is active from 0 V, up to the nominal set-point voltage. Within this  
range, the module output follows the voltage at the Track pin on a volt-for-volt basis. When the control  
voltage is raised above this range, the module regulates at its nominal output voltage. If unused, this  
input should be connected to VI for a faster power up. For further information, see the related  
Application Information section.  
18  
When this input is asserted to GND, the output voltage is decreased by 5% from the nominal. The input  
requires an open-collector (open-drain) interface. It is not TTL compatible. A lower percent change can  
be accommodated with a series resistor. For further information, see the related Application Information  
section.  
Margin Down(1)  
Margin Up(1)  
20  
19  
When this input is asserted to GND, the output voltage is increased by 5%. The input requires an open  
collector (open-drain) interface. It is not TTL compatible. The percent change can be reduced with a  
series resistor. For further information, see the related Application Information section.  
(1) Denotes negative logic: Open = Normal operation; Ground = Function active  
16  
16  
15  
14 13  
11 10  
8
12  
9
17  
18  
19  
20  
PTHXX040W  
(Top View)  
1
2
3
4
7
6
5
5
Submit Documentation Feedback  
PTH04040W  
www.ti.com  
SLTS238ASEPTEMBER 2005REVISED FEBRUARY 2006  
(1)(2)  
TYPICAL CHARACTERISTICS (VI = 3.3 V)  
CHARACTERISTIC DATA  
EFFICIENCY  
vs  
LOAD CURRENT  
OUTPUT RIPPLE  
vs  
LOAD CURRENT  
POWER DISSIPATION  
vs  
LOAD CURRENT  
25  
100  
90  
15  
12  
9
20  
15  
V
= 1 V  
O
V
= 1.5 V  
O
80  
70  
60  
50  
V
= 1.5 V  
O
10  
6
V
= 1 V  
50  
O
5
0
3
0
0
10  
20  
30  
40  
60  
0
10  
20  
30  
40  
50  
60  
0
10  
20  
30  
40  
50  
60  
I
− Load Current − A  
I
− Load Current − A  
I
− Load Current − A  
L
L
L
Figure 1.  
Figure 2.  
Figure 3.  
TEMPERATURE DERATING  
vs  
LOAD CURRENT  
90  
80  
70  
60  
50  
40  
Nat Cinv  
200 LFM  
400 LFM  
30  
20  
0
10  
20  
30  
40  
50  
60  
I
− Load Current − A  
L
Figure 4.  
(1) The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the  
converter. Applies to Figure 1, Figure 2, and Figure 3.  
(2) SOA curves represent the conditions at which internal components are at or below the manufacturer’s maximum operating  
temperatures. Derating limits apply to modules soldered directly to a 4 inchs × 4 inchs double-sided PCB with 1 oz. copper. Applies to  
Figure 4.  
6
Submit Documentation Feedback  
 
 
PTH04040W  
www.ti.com  
SLTS238ASEPTEMBER 2005REVISED FEBRUARY 2006  
(1)(2)  
TYPICAL CHARACTERISTICS (VI = 5 V)  
EFFICIENCY  
vs  
LOAD CURRENT  
OUTPUT RIPPLE  
vs  
LOAD CURRENT  
POWER DISSIPATION  
vs  
LOAD CURRENT  
25  
20  
15  
15  
12  
9
100  
90  
V
= 2.5 V  
O
V
= 1.8 V  
O
V
= 1.8 V  
80  
V = 1.8 V  
O
O
V
= 1.5 V  
O
V
= 1.2 V  
O
10  
6
70  
60  
50  
V
= 1.2 V  
O
V
= 1.2 V  
O
5
0
3
0
0
10  
20  
30  
40  
50  
60  
0
10  
20  
30  
40  
50  
60  
0
10  
20  
30  
40  
50  
60  
I − Load Current − A  
L
I
− Load Current − A  
I
− Load Current − A  
L
L
Figure 5.  
Figure 6.  
Figure 7.  
TEMPERATURE DERATING  
vs  
LOAD CURRENT  
90  
80  
70  
60  
50  
40  
Nat Cinv  
200 LFM  
400 LFM  
30  
20  
V = 5 V  
I
0
10  
20  
30  
40  
50  
60  
I
− Load Current − A  
L
Figure 8.  
(1) The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the  
converter. Applies to Figure 5, Figure 6, and Figure 7.  
(2) SOA curves represent the conditions at which internal components are at or below the manufacturer’s maximum operating  
temperatures. Derating limits apply to modules soldered directly to a 4 inchs × 4 inchs double-sided PCB with 1 oz. copper. Applies to  
Figure 8.  
7
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APPLICATION INFORMATION  
CAPACITOR RECOMMENDATIONS FOR THE PTH04040W POWER MODULE  
The PTH04040W uses state-of-the-art multi-phase power converter topology that employs multiple parallel  
switching and filter inductor paths between the input and output capacitors. The PTH04040W uses three  
switching paths. The three paths share the total load current, operate at the same frequency, and are evenly  
displaced in phase.  
With multiple switching paths the transient output current capability is significantly increased. This reduces the  
amount of external output capacitance required to support a load transient. The ripple current, as seen by the  
input and output capacitors, is reduced in magnitude and effectively tripled in frequency.  
INPUT CAPACITOR  
The improved transient response of a multi-phase converter places a bigger burden on the transient capability of  
the input source. The size and value of the input capacitor is therefore determined by this converter’s transient  
performance capability. The minimum amount of input capacitance required is 940 µF (2 × 470 µF or 3 × 330 µF),  
with an RMS ripple current rating of 400 mA. This minimum value assumes that the converter is supplied with a  
responsive, low-inductance input source. This source should have ample capacitive decoupling and be  
distributed the converter via PCB power and ground planes. For highperformance applications, or wherever the  
transient capability of the input source is limited, 2,200 µF of input capacitance is recommended.  
Ripple current and less than 100 mequivalent series resistance (ESR) values are the major considerations,  
along with temperature, when designing with different types of capacitors. Unlike polymer tantalum, conventional  
tantalum capacitors have a recommended minimum voltage rating of 2 × (maximum dc voltage + ac ripple). This  
is standard practice to ensure reliability.  
For improved ripple reduction on the input bus, ceramic capacitors may be used to complement electrolytic types  
and achieve the minimum required capacitance.  
OUTPUT CAPACITORS RECOMMENDED  
In order to respond with load transients (sudden changes in load current) the regulator requires external output  
capacitance. The minimum output capacitance is 660 µF (2 × 330 µF or 1 × 680 µF) with an ESR of at least  
2 m. This output capacitance is required for the module to meet its transient response specification. For most  
applications, a high quality computer grade aluminum electrolytic capacitor is suitable. These capacitors provide  
adequate decoupling over the frequency range, 2 kHz to 150 kHz, and when ambient temperatures are above  
0°C. For operation below 0°C, tantalum, ceramic, or Os-Con type capacitors are recommended.  
When using one or more nonceramic capacitors, the calculated equivalent ESR should be no lower than 4 mΩ  
7 musing the manufacturer’s maximum ESR for a single capacitor. A list of preferred low-ESR type capacitors  
are identified in Table 1.  
CERAMIC CAPACITORS  
Above 150 kHz, the performance of aluminum electrolytic capacitors becomes less effective. To further improve,  
the reflected input ripple current or the output transient response, multilayer ceramic capacitors can also be  
added. Ceramic capacitors have very low ESR and their resonant frequency is higher than the bandwidth of the  
regulator. When used on the output their combined ESR is not critical as long as the total value of ceramic  
capacitance does not exceed 300 µF. Also, to prevent the formation of local resonances, do not place more than  
five identical ceramic capacitors in parallel with values of 10 µF or greater..  
TANTALUM CAPACITORS  
Tantalum type capacitors can be used at both the input and output, and are recommended for applications where  
the ambient operating temperature can be less than 0°C. The AVX TPS, Sprague 593D/594/595, and Kemet  
T495/ T510 capacitor series are suggested over many other tantalum types due to their higher rated surge,  
power dissipation, and ripple current capability. As a caution, many general-purpose tantalum capacitors have  
considerably higher ESR, reduced power dissipation and lower ripple current capability. These capacitors are  
also less reliable when determining their power dissipation and surge current capability. Tantalum capacitors that  
do not have a stated ESR or surge current rating are not recommended for power applications.  
8
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APPLICATION INFORMATION (continued)  
When specifying Os-Con and polymer tantalum capacitors for the output, the minimum ESR limit is encountered  
before the maximum capacitance value is reached.  
CAPACITOR TABLE  
Table 1 identifies the characteristics of capacitors from a number of vendors with acceptable ESR and ripple  
current (rms) ratings. The recommended number of capacitors required at both the input and output buses is  
identified for each capacitor type.  
Note: This is not an extensive capacitor list. Capacitors from other vendors are available with comparable  
specifications. Those listed are for guidance. The RMS ripple current rating and ESR (at 100kHz) are critical  
parameters necessary to insure both optimum regulator performance and long capacitor life.  
DESIGNING FOR VERY FAST LOAD TRANSIENTS  
The transient response of the dc/dc converter has been characterized using a load transient with a di/dt of  
1 A/µs. The typical voltage deviation for this load transient is given in the data sheet specification table using the  
minimum required value of output capacitance. As the di/dt of a transient is increased, the response of a  
converter’s regulation circuit ultimately depends on its output capacitor decoupling network. This is an inherent  
limitation with any dc/dc converter once the speed of the transient exceeds its bandwidth capability. If the target  
application specifies a higher di/dt or lower voltage deviation, the requirement can only be met with additional  
output capacitor decoupling. In these cases special attention must be paid to the type, value and ESR of the  
capacitors selected. Additional input capcitance may be requried to insure the stability of the input bus during  
higher current transient di/dt.  
9
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APPLICATION INFORMATION (continued)  
Table 1. Input/Output Capacitors(1)  
Capacitor Characteristics  
Max Ripple  
Quantity  
Capacitor Vendor,  
Type Series (Style)  
Working  
Voltage  
Value  
(µF)  
Max. ESR  
at 100 kHz  
Physical  
Size (mm)  
Input Output  
Current at  
85°C (I rms)  
Vendor Part No.  
Bus  
Bus  
Panasonic  
FC (Radial)  
FK (SMD)  
10 V  
10 V  
10 V  
1000  
1000  
1000  
0.068 Ω  
0.0650 Ω  
0.080 Ω  
>1050 mA  
1205 mA  
850 mA  
10 × 16  
12.5 × 16.5  
10 × 10.2  
1
1
1
1
1
1
EEUFC1A102  
EEVFC1A102LQ  
EEVFK1A102P  
United Chemi-Con  
FX, Oscon (Radial)  
6.3 V  
6.3 V  
10 V  
10 V  
1000  
820  
680  
0.013 Ω  
0.010 Ω  
0.007 Ω  
0.068 Ω  
4935 mA  
5500 mA  
>5800 mA  
1050 mA  
10 × 10.5  
10 × 12.2  
10 × 11.5  
10 × 16  
1
2
2
1
1
1
3  
1
6FX1000M  
PXA6.3VC820MJ12TP  
PSA6.3VB680MJ11  
PXA, (Poly-Aluminum (SMD)  
PSA (Poly-Aluminum)  
LXZ, Aluminum (Radial)  
1000  
LXZ10VB102M10X16LL  
Nichicon, Aluminum  
HD (Radial)  
PM (Radial)  
6.3 V  
10 V  
1000  
1000  
0.053 Ω  
0.065 Ω  
1030 mA  
1040 mA  
10 × 12.5  
12.5 × 15  
1
1
1
1
UHD0J102MPR  
UPM1A102MHH6  
Sanyo, Os-Con  
SP, (Radial)  
SVP, (SMD)  
10 V  
6.3 V  
470  
820  
0.015 Ω  
0.012 Ω  
>4500 mA  
>5440 mA  
10x10.5  
10x12.7  
2(2)  
2
5  
43  
10SP470M  
6SVP820M  
Panasonic, Poly-Aluminum:  
S/SE (SMD)  
63 V  
180  
0.005 Ω  
4000 mA  
7.3x4.3x4.2  
N/R  
2  
EEFSE0J181R  
AVX, Tantalum, Series III  
TPS (SMD)  
10 V  
10 V  
470  
470  
0.045 Ω  
0.060 Ω  
1723 mA  
1826 mA  
7,3 L  
× 5,7 W  
× 4,1 H  
2(2)  
2(2)  
7  
7  
TPSE477M010R0045  
TPSV477M010R0060  
Kemet, Poly-Tantalum  
T520 (SMD)  
T530 (SMD)  
6.3 V  
10 V  
6.3 V  
470  
330  
470  
0.018 Ω  
0.015 Ω  
0.012 Ω  
>1200 mA  
>3800 mA  
4200 mA  
4,3 W  
× 7.3 L  
× 4 H  
2(2)  
3
2(2)  
6  
4  
3  
T520X477M006SE018  
T530X337M010AS  
T530X477M006AS  
Vishay-Sprague  
7.2 L × 6 W  
595D, Tantalum (SMD)  
94SA, Os-con (Radial)  
10 V  
16 V  
470  
2200  
0.100 Ω  
0.015 Ω  
1440 mA  
9740 mA  
× 4.1 H  
16 × 25  
2(2)  
1
7  
4  
595D477X0010R2T  
94SA108X0016HBP  
Kemet, Ceramic X5R (SMD)  
16 V  
6.3 V  
10  
47  
0.002 Ω  
0.002 Ω  
1210 case  
3225 mm  
1(3)  
1(3)  
9  
8  
C1210C106M4PAC  
C1210C476K9PAC  
Murata, Ceramic X5R (SMD)  
6.3 V  
6.3 V  
16 V  
16 V  
100  
47  
22  
0.002 Ω  
0.002 Ω  
1210 case  
3225 mm  
1(3)  
1(3)  
1(3)  
4  
8  
8  
9  
GRM32ER60J107M  
GRM32ER60J476M  
GRM32ER61C226K  
GRM32DR61C106K  
10  
TDK, Ceramic X5R (SMD)  
6.3 V  
6.3 V  
16 V  
16 V  
100  
47  
22  
1210 case  
3225 mm  
1(3)  
1(3)  
1(3)  
4  
8  
8  
9  
C3225X5R0J107MT  
C3225X5R0J476MT  
C3225X5R1C226MT  
C3225X5R1C106MT  
10  
(1) Capacitor Supplier Verification  
1.Please verify availability of capacitors identified in this table. Capacitor suppliers may recommend alternative part numbers because of  
limited availability or obsolete products. In some instances, the capacitor product life cycle may be in decline and have short-term  
consideration for obsolescence.  
RoHS, Lead-free and Material Details  
2.Please consult capacitor suppliers regarding material composition, RoHS status, lead-free status, and manufacturing process  
requirements. Component designators or part number deviations can occur when material composition or soldering requirements are  
updated.  
(2) The total capacitance is slightly lower than 1000 µF, but is acceptable based on the combined ripple current rating.  
(3) Ceramic capacitors can be used to complement electrolytic types at the input to further reduce high-frequency ripple current.  
10  
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ADJUSTING THE OUTPUT VOLTAGE OF THE PTH04040W WIDE-OUTPUT ADJUST POWER  
MODULE  
The VO Adjust control (pin 17) sets the output voltage of the PTH04040W to a value higher than 0.8 V. The  
adjustment range is from 0.8 V to 2.5 V. For an output voltage other than 0.8 V a single external resistor, RSET 1,  
must be connected directly between the VO Adjust (pin 17) and the output GND (pin 16)(2). Table 2 gives the  
preferred value of the external resistor for a number of standard voltages, along with the actual output voltage  
that this resistance value provides.  
For other output voltages, the value of the required resistor is calculated using the following formula, or by  
selecting from the range of values given in Table 3. Figure 9 shows the placement of the required resistor.  
0.8 V  
R
+ 10 kW   
* 2.49 kW  
set  
V
* 0.8 V  
out  
(1)  
Table 2. Preferred Values of Rset for Standard Output Voltages  
(1)  
VOUT (Standard)  
RSET (Preferred Value)  
VOUT (Actual)  
2.502 V  
2.010 V  
1.803 V  
1.504 V  
1.202 V  
1.005 V  
0.8 V  
2.5 V  
2 V  
2.21 Ω  
4.12 Ω  
5.49 Ω  
8.87 Ω  
17.4 Ω  
36.5 Ω  
Open  
1.8 V  
1.5 V  
1.2 V  
1 V  
0.8 V  
(1) The nominal input voltage must be at least 2 × VO. Output voltage regulation is guaranteed with an input voltage within ±10% from  
nominal 3.3 V or 5 V. For example, for VI = 5 V and VO = 2.5 V, the input can vary between 4.5 V and 5.5 V.  
18  
Track  
11  
+Sense  
9
V
O
12  
V
PTH04040W  
O
15  
14  
Sense  
Adjust  
GND  
10 13 16 17  
C
R
SET  
O
1%  
0.05W  
GND  
GND  
Figure 9. VO Adjust Resistor Placement  
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Table 3. Output Voltage Set-Point Resistor Values  
VOUT  
0.8  
RSET  
VOUT  
1.425  
1.45  
1.475  
1.5  
RSET  
Open  
10.3 kΩ  
9.82 kΩ  
9.36 kΩ  
8.94 kΩ  
8.18 kΩ  
7.51 kΩ  
6.92 kΩ  
6.4 kΩ  
0.825  
0.85  
0.875  
0.9  
318 kΩ  
158 kΩ  
104 kΩ  
77.5 kΩ  
61.5 kΩ  
50.8 kΩ  
43.2 kΩ  
37.5 kΩ  
33.1 kΩ  
29.5 kΩ  
26.6 kΩ  
24.2 kΩ  
22.1 kΩ  
20.4 kΩ  
18.8 kΩ  
17.5 kΩ  
16.3 kΩ  
15.3 kΩ  
14.4 kΩ  
13.5 kΩ  
12.7 kΩ  
12.1 kΩ  
11.4 kΩ  
10.8 kΩ  
1.55  
1.6  
0.925  
0.95  
0.975  
1
1.65  
1.7  
1.75  
1.8  
5.93 kΩ  
5.51 kΩ  
5.13 kΩ  
4.78 kΩ  
4.47 kΩ  
4.18 kΩ  
3.91kΩ  
3.66 kΩ  
3.44 kΩ  
3.22 kΩ  
3.03 kΩ  
2.84 kΩ  
2.67 kΩ  
2.51 kΩ  
2.36 kΩ  
2.22 kΩ  
1.025  
1.05  
1.075  
1.1  
1.85  
1.9  
1.95  
2
1.125  
1.15  
1.175  
1.2  
2.05  
2.1  
2.15  
2.2  
1.225  
1.25  
1.275  
1.3  
2.25  
2.3  
2.35  
2.4  
1.325  
1.35  
1.375  
1.4  
2.45  
2.5  
NOTES:  
1. A 0.05-W rated resistor can be used. The tolerance should be 1%, with temperature stability of 100 ppm/°C  
(or better). Place the resistor as close to the regulator as possible. Connect the resistor directly between pins  
17 and 16 using dedicated PCB traces.  
2. Never connect capacitors from VO Adjust to either GND or VO. Any capacitance added to the VO Adjust pin  
affects the stability of the regulator.  
ADJUSTING THE UNDERVOLTAGE LOCKOUT (UVLO) OF THE PTH04040W POWER MODULES  
The PTH04040W power modules incorporate an input undervoltage lockout (UVLO). The UVLO feature prevents  
the operation of the module until there is sufficient input voltage to produce a valid output voltage. This enables  
the module to provide a monotonic powerup for the load circuit, and also limits the magnitude of current drawn  
from the module’s input source during the power-up sequence.  
The UVLO characteristic is defined by the on-threshold (VTHD) and hysterisis (VHYS) voltages. Below the on  
threshold, the Inhibit control is overriden, and the module does not produce an output. Hysterisis voltage is the  
difference between the on and off threshold voltages. It ensures a clean power-up, even when the input voltage  
is rising slowly. The hysterisis prevents start-up oscillations, which can occur if the input voltage droops slightly  
when the module begins drawing current from the input source.  
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UVLO ADJUSTMENT  
The UVLO feature of the PTH04040W gives the user the option of adjusting the on-threshold voltage higher than  
the default value. This might be desirable if the module is powered from a 5-V input bus. This prevents the  
module from operating until the input bus has risen closer to its regulation voltage.  
The adjustment method uses the UVLO Prog control (pin 8). If the UVLO Prog pin is left open circuit, the  
onthreshold voltage remains at its nominal value of 2.63 V (see electrical specification table). This ensures that  
the unadjusted module produces a regulated output when the minimum input voltage is applied. The hysterisis  
voltage is approximately 0.62 V, which correlates to an off-threshold voltage of about 2 V. The magnitude of the  
hysterisis is automatically set to about 22% of the onthreshold. So if the on-threshold voltage is increased, then  
the hystersis also increases.  
ADJUSTMENT METHOD  
Figure 10 shows the placement of the resistor, RTHD, for adjusting the UVLO on-threshold voltage. It connects  
from the UVLO Prog control pin to GND. Equation 2 determines the value of RTHD required to adjust VTHD to a  
new value. The default value is 2.63 V, and it can only be adjusted higher. Once the value of RTHD has been set,  
Equation 3 is used to determine the new hystersis voltage.  
12.9  
=
RTHD  
k  
VTHD − 2.63  
(2)  
(3)  
1
VHYS  
+
= 2.191  
0.283  
V
RTHD  
2
4
6
V
I
PTH04040W  
V
I
8
UVLO Prog  
Inhibit GND  
3
5
7
1
C
R
I
THD  
1,000 mF  
GND  
Figure 10. UVLO Program Resistor Placement  
FEATURES OF THE PTH FAMILY OF NONISOLATED WIDE OUTPUT ADJUST POWER  
MODULES  
POLA™ COMPATIBILITY  
The PTH/PTV family of nonisolated, wide-output adjustable power modules are optimized for applications that  
require a flexible, high performance module that is small in size. Each of these products are POLA™ compatible.  
POLA-compatible products are produced by a number of manufacturers, and offer customers advanced,  
nonisolated modules with the same footprint and form factor. POLA parts are also assured to be interoperable,  
thereby providing customers with second-source availability.  
Many of the POLA-compatible parts include a feature called Auto-Track™. Auto-Track was specifically designed  
to simplify the task of sequencing the supply voltages in a power system. This and other features are described  
the following sections.  
Soft-Start Power Up  
The Auto-Track feature allows the power-up of multiple PTH modules to be directly controlled from the Track pin.  
However in a stand-alone configuration, or when the Auto-Track feature is not being used, the Track pin should  
be directly connected to the input voltage, Vin (see Figure 11).  
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10  
9
8
5
Up Dn  
Sense  
Track  
5 V  
3.3 V  
2
6
V
V
PTH05020W  
I
O
Inhibit  
Adjust  
GND  
3
1
7
4
+
+
C
C
R
O
I
SET  
698 W  
0.1 W, 1%  
330 mF  
1,000 mF  
GND  
GND  
Figure 11. Power-Up Application Circuit  
When the Track pin is connected to the input voltage the Auto-Track function is permanently disengaged. This  
allows the module to power up entirely under the control of its internal soft-start circuitry. When power up is  
under soft-start control, the output voltage rises to the set-point at a quicker and more linear rate.  
From the moment a valid input voltage is applied, the soft-start control introduces a short time delay (typically  
5 ms–10 ms) before allowing the output voltage to rise.  
V
(1 V/Div)  
I
V
(1 V/Div)  
O
I
(5 A/Div)  
I
t - Time = 5 msec/Div  
Figure 12. Power-Up Waveforms  
The output then progressively rises to the module’s setpoint voltage. Figure 12 shows the soft-start power-up  
characteristic of the 22-A output product (PTH05020W), operating from a 5-V input bus and configured for a  
3.3-V output. The waveforms were measured with a 5-A resistive load and the Auto-Track feature disabled. The  
initial rise in input current when the input voltage first starts to rise is the charge current drawn by the input  
capacitors. Power-up is complete within 15 ms.  
OVERCURRENT PROTECTION  
For protection against load faults, all modules incorporate output overcurrent protection. Applying a load that  
exceeds the regulator’s overcurrent threshold causes the regulated output to shut down. Following shutdown, a  
module periodically attempts to recover by initiating a soft-start powerup. This is described as a hiccup mode of  
operation, whereby the module continues in a cycle of successive shutdown and power up until the load fault is  
removed. During this period, the average current flowing into the fault is significantly reduced. Once the fault is  
removed, the module automatically recovers and returns to normal operation.  
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OVERTEMPERATURE PROTECTION (OTP)  
Products with a high output current capability (>20 A), incorporate overtemperature protection. This feature is  
provided by an on-board temperature sensor that protects the module’s internal circuitry against excessively high  
temperatures. A rise in the internal temperature may be the result of a drop in airflow, or a high ambient  
temperature. If the internal temperature exceeds the OTP threshold, the module’s Inhibit control is automatically  
pulled low. This turns the output off. The output voltage drops as the external output capacitors are discharged  
by the load circuit. The recovery is automatic, and begins with a soft-start power up. It occurs when the the  
sensed temperature decreases by about 10°C below the trip point.  
Note: The overtemperature protection is a last resort mechanism to prevent thermal stress to the regulator.  
Operation at or close to the thermal shutdown temperature is not recommended, and reduces the long-term  
reliability of the module. Always operate the regulator within the specified safe operating area (SOA) limits for  
the worst-case conditions of ambient temperature and airflow.  
OUTPUT ON/OFF INHIBIT  
For applications requiring output voltage on/off control, each series of the PTH family incorporates an output  
Inhibit control pin. The inhibit feature can be used wherever there is a requirement for the output voltage from the  
regulator to be turned off.  
The power modules function normally when the Inhibit pin is left open-circuit, providing a regulated output  
whenever a valid source voltage is connected to Vin with respect to GND.  
Figure 13 shows the typical application of the inhibit function. Note the discrete transistor (Q1). The Inhibit control  
has its own internal pull-up to VI potential. The input is not compatible with TTL logic devices. An open-collector  
(or open-drain) discrete transistor is recommended for control.  
V
Sense  
O
10  
9
8
5
V
V
O
I
2
6
PTH05020W  
3
1
7
4
+
+
L
C
I
R
C
SET  
O
A
D
O
1,000 mF  
1 = Inhibit  
GND  
Q1  
330 mF  
BSS138  
GND  
Figure 13. Inhibit Control Circuit  
Turning Q1 on applies a low voltage to the Inhibit control and disables the output of the module. If Q1 is then  
turned off, the module executes a soft-start powerup. A regulated output voltage is produced within 20 ms.  
Figure 14 shows the typical rise in both the output voltage and input current, following the turn-off of Q1. The turn  
off of Q1 corresponds to the rise in the waveform, Q1 Vds. The waveforms were measured with a 5-A constant  
current load.  
15  
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V
(2 V/Div)  
O
I
(2 A/Div)  
I
Q1Vds (5 V/Div)  
t - Time = 10 msec/Div  
Figure 14. Power-Up from Inhibit Control  
REMOTE SENSE  
The remote sense feature allows the regulator to compensate for limited amounts of voltage drop, that may be  
incurred between the converter and load, due to resistance in the PCB traces. Connecting the +Sense and  
–Sense pins to the respective VO and GND output nodes improves the load regulation of the regulator output at  
those connection points. This is recommended even if the load circuit is located close to the module.  
If either the +Sense and –Sense are left open-circuit, an internal low-value resistor (15-or less), connected  
from the respective sense pin to either VO or GND, ensures the output voltage remains in regulation.  
With the sense pins connected, the difference between the voltage measured across the VO and GND pins of the  
regulator, and that measured at +Sense with respect to +Sense, is the amount of IR drop being compensated by  
the regulator. This should be limited to a maximum of 0.3 V.  
Note: The remote sense feature is not designed to compensate for the forward drop of nonlinear or  
frequency dependent components that may be placed in series with the converter output. Examples include  
OR-ing diodes, filter inductors, ferrite beads, and fuses. When these components are enclosed by the remote  
sense connection they are effectively placed inside the regulation control loop, which can adversely affect the  
stability of the regulator.  
Auto-Track™ FUNCTION  
The Auto-Track function is unique to the PTH/PTV family, and is available with the all POLA-compatible  
products. Auto-Track was designed to simplify the amount of circuitry required to make the output voltage from  
each module power up and power down in sequence. The sequencing of two or more supply voltages during  
power up is a common requirement for complex mixed-signal applications, that use dual-voltage VLSI ICs such  
as the TMS320™ DSP family, micro-processors, and ASICs.  
HOW Auto-Track™ WORKS  
Auto-Track works by forcing the module’s output voltage to follow a voltage presented at the Track control pin.  
This control range is limited to between 0 V and the module’s set-point voltage. Once the Track input is raised  
above the set-point voltage, the module’s output remains at its set-point 1. As an example, if the Track pin of a  
2.5-V regulator is at 1 V, the regulated output will be 1 V. But, if the voltage at the Track pin rises to 3 V, the  
regulated output does not go higher than 2.5 V.  
When the Track input is used to connect a number of modules together, it forces the output voltage from each  
module to follow a common signal during power-up and power-down. The control signal can be an externally  
generated master ramp waveform, or the output voltage from another power supply circuit.(3) For convenience,  
each module’s Track input incorporates an internal RC charge circuit. This operates off the module’s input  
voltage to provide a suitable rising voltage ramp waveform.  
TYPICAL APPLICATION  
Connecting the Track inputs of two or more modules forces their Track input to follow the same collective RC  
ramp waveform, and allows their power-up sequence to be coordinated from a common Track control signal.  
This can be an open-collector (or open drain) device, such as a power-up reset voltage supervisor IC.  
16  
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To coordinate a power-up sequence the Track control must first pulled to ground potential. This should be done  
at or before input power is applied to the modules. The ground signal should be maintained for at least 10 ms  
after input power has been applied. This brief period gives the modules time to complete their internal soft-start  
initialization, enabling them to produce an output voltage. A low-cost supply voltage supervisor IC, that includes  
built-in time delay, is an ideal component for automatically controlling the Track inputs at power up.  
Figure 15 shows how the TPS3808G50 supply voltage supervisor IC (U3) can be used to coordinate the  
sequenced power-up of two 5-V input Auto-Track modules. The output of the TPS3808 supervisor becomes  
active above an input voltage of 0.8 V, enabling it to assert a ground signal to the common Track control well  
before the input voltage has reached the module’s undervoltage lockout threshold. The ground signal is  
maintained until approximately 27 ms after the input voltage has risen above U3’s voltage threshold, which is  
4.65 V. The 27-ms time period is controlled by the capacitor C3. The value of 4700 µF provides sufficient time  
delay for the modules to complete their internal soft-start initialization. The output voltage of each module  
remains at zero until the Track control voltage is allowed to rise. When U3 removes the ground signal, the Track  
control voltage automatically rises to the input voltage. This causes the output voltage of each module to rise  
simultaneously with the other modules, until each reaches its respective set-point voltage.  
Figure 15 shows the output voltage waveforms from the circuit of Figure 16 after input voltage is applied to the  
circuit. The waveforms, VO1 and VO2, represent the output voltages from the two power modules, U1 (3.3 V) and  
U2 (1.8 V), respectively. VTRK, VO1, and VO2 are shown rising together to produce the desired simultaneous  
power-up characteristic.  
The same circuit also provides a power-down sequence. When the input voltage falls below U3's voltage  
threshold, the ground signal is re-applied to the common Track control. This pulls the Track inputs to zero volts,  
forcing the output of each module to follow, as shown in Figure 17. In order for a simultaneous power-down to  
occur, the Track inputs must be pulled low before the input voltage has fallen below the modules' undervoltage  
lockout. This is an important constraint. Once the modules recognize that a valid input voltage is no longer  
present, their outputs can no longer follow the voltage applied at their Track input. During a power-down  
sequence, the fall in the output voltage from the modules is limited by the maximum output capacitance and the  
Auto-Track slew rate.  
17  
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NOTES ON USE OF Auto-Track™  
1. The Track pin voltage must be allowed to rise above the module’s set-point voltage before the module can  
regulate at its adjusted set-point voltage.  
2. The Auto-Track function tracks almost any voltage ramp during power up, and is compatible with ramp  
speeds of up to 1 V/ms.  
3. The absloute maximum voltage that may be applied to the Track pin is VI.  
4. The module does not follow a voltage at its Track input until it has completed its soft-start initialization. This  
takes at least 10 ms from the time that the module has sensed that a valid voltage is present. During this  
period, the Track input should be held at ground potential.  
5. The module is capable of both sinking and sourcing current when following a voltage at its Track input.  
Therefore startup into an output prebias is not supported when the module is under Auto-Track control.  
Prebias holdoff is not necessary when all supply voltages simultaneously under the control of Auto-Track.  
6. The Auto-Track function can be disabled by connecting the Track pin to the input voltage (VI). With  
Auto-Track disabled, the output voltage rises at a quicker and more linear rate after input power is applied.  
14  
13  
TT  
U1  
Track  
10  
+Sense  
+5 V  
2, 6  
5, 9  
V
I
V
O
PTH05T210W  
V
C
= 3.3 V  
O1  
1
11  
−Sense  
V Adj  
INH/UVLO  
GND GND  
3, 4 7, 8  
O
+
O1  
12  
+
C
I1  
R
SET1  
1.62 k  
U3  
6
V
CC  
5
3
R
50 Ω  
TRK#  
MR SENSE  
1
RESET  
C4  
0.1 µF  
TPS3808G50  
CT  
4
GND  
U2  
19  
20  
18  
2
C3  
4700 pF  
MarginMargin Track  
11  
Up Down  
PTH04040W  
+Sense  
V
I
2
4
6
9
12  
15  
V
I
V
O
V
O2  
= 1.8 V  
8
14  
−Sense  
UVLO Prog  
Inhibit GND  
R
= 100 /N  
TRK#  
N = Number of track pins connected together  
GND  
10 13 16  
V Adj  
O
+
7
1
3
5
17  
C
O2  
+
C
I2  
R
SET2  
5.49 kΩ  
Figure 15. Sequenced Power Up and Power Down using Auto-Track  
18  
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V
TRK  
(1 V/div)  
V
TRK  
(1 V/div)  
V 1 (1 V/div)  
0
V 1 (1 V/div)  
0
V 2 (1 V/div)  
0
V 2 (1 V/div)  
0
t − Time − 200 µs/div  
t − Time − 20 ms/div  
Figure 16. Auto-Track Simultaneous Power Up  
Waveforms  
Figure 17. Auto-Track Simultaneous Power Down  
Waveforms  
MARGIN UP/DOWN CONTROLS  
The PTHxx060, PTHxx010, PTHxx020, and PTHxx030 products incorporate Margin Up and Margin Down control  
inputs. These controls allow the output voltage to be momentarily adjusted(1), either up or down, by a nominal  
5%. This provides a convenient method for dynamically testing the operation of the load circuit over its supply  
margin or range. It can also be used to verify the function of supply voltage supervisors. The ±5% change is  
applied to the adjusted output voltage, as set by the external resistor, Rset at the Vo Adjust pin.  
The 5% adjustment is made by pulling the appropriate margin control input directly to the GND terminal 2. A  
low-leakage open-drain device, such as an n-channel MOSFET or p-channel JFET is recommended for this  
purpose(3). Adjustments of less than 5% can also be accommodated by adding series resistors to the control  
inputs. The value of the resistor can be selected from Table 4, or calculated using the following formula.  
UP/DOWN ADJUST RESISTANCE CALCULATION  
499  
- 99.8 kW  
R
or R  
=
D
U
D %  
(4)  
Where % = The desired amount of margin adjusted in percent.  
NOTES  
1. The Margin Up and Margin Down controls were not intended to be activated simultaneously. If they are  
activated simultaneously, the effects on the output voltage may not completely cancel, resulting in the  
possibility of a higher error in the output voltage set point.  
2. The ground reference should be a direct connection to the module GND at pin 7 (pin 1 for the PTHxx050).  
This produces a more accurate adjustment at the load circuit terminals. The transistors Q1 and Q2 should be  
located close to the regulator.  
3. The Margin Up and Margin Down control inputs are not compatible with devices that source voltage. This  
includes TTL logic. These are analog inputs and should only be controlled with a true open-drain device  
(preferably discrete MOSFET transistor). The device selected should have low off-state leakage current.  
Each input sources 8 µA when grounded, and has an open-circuit voltage of 0.8 V.  
19  
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Table 4. Margin Up/Down Resistor Values  
% ADJUST  
RU / RD  
0 kΩ  
5
4
3
2
1
24.9 kΩ  
66.5 kΩ  
150.0 kΩ  
397.0 kΩ  
10  
9
8
1
7
+V  
O
0 V  
PTH05010W  
(Top View)  
V
+V  
I
O
2
6
3
4
5
R
R
D
U
+
R
SET  
+
C
I
0.1 W, 1%  
C
L
O
Q1  
O
A
D
Margin Down  
Q2  
Margin Up  
GND  
GND  
Figure 18. Margin Up/Down Application Schematic  
PREBIAS STARTUP CAPABILITY  
A prebias startup condition occurs as a result of an external voltage being present at the output of a power  
module prior to its output becoming active. This often occurs in complex digital systems when current from  
another power source is backfed through a dual-supply logic component, such as an FPGA or ASIC. Another  
path might be via clamp diodes as part of a dual-supply power-up sequencing arrangement. A prebias can cause  
problems with power modules that incorporate synchronous rectifiers. This is because under most operating  
conditions, these types of modules can sink as well as source output current.  
The PTH/PTV family of power modules incorporate synchronous rectifiers, but does not sink current during  
startup(1), or whenever the Inhibit pin is held low. However, to ensure satisfactory operation of this function,  
certain conditions must be maintained(2). Figure 20 shows an application demonstrating the prebias startup  
capability. The start-up waveforms are shown in Figure 19. Note that the output current from the PTH03010W (Io)  
shows negligible current until its output voltage rises above that backfed through diodes D1 and D2.  
Note: The prebias start-up feature is not compatible with Auto-Track. When the module is under Auto-Track  
control, it sinks current if the output voltage is below that of a back-feeding source. To ensure a prebias  
hold-off, one of two approaches must be followed when input power is applied to the module. The Auto-Track  
function must be disabled(3), or the module’s output held off (for at least 50 ms) using the Inhibit pin. Either  
approach ensures that the Track pin voltage is above the set-point voltage at start up.  
NOTES  
1. Startup includes the short delay (approximately 10 ms) prior to the output voltage rising, followed by the rise  
of the output voltage under the module’s internal soft-start control. Startup is complete when the output  
voltage has risen to either the set-point voltage or the voltage at the Track pin, whichever is lowest.  
2. To ensure that the regulator does not sink current when power is first applied (even with a ground signal  
applied to the Inhibit control pin), the input voltage must always be greater than the output voltage throughout  
the powerup and power-down sequence.  
3. The Auto-Track function can be disabled at power up by immediately applying a voltage to the module’s  
Track pin that is greater than its set-point voltage. This can be easily accomplished by connecting the Track  
20  
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pin to Vin.  
V
(1 V/Div)  
I
V
(1 V/Div)  
O
I
(5 A/Div)  
O
t - Time = 5 msec/Div  
Figure 19. Pre-Bias Startup Waveforms  
V = 3.3 V  
I
10  
9
8
5
Track  
Sense  
V
= 2.5 V  
2
6
O
V
V
PTH03010W  
I
O
+
V
Adj  
Inhibit  
GND  
I
o
3
1
7
4
VCCIO  
VCORE  
R2  
2k21  
+
+
C
C
I
O
330 mF  
330 mF  
ASIC  
Figure 20. Application Circuit Demonstrating Prebias Startup  
21  
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配单直通车
6SVP820M产品参数
型号:6SVP820M
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Transferred
IHS 制造商:SANYO ELECTRIC CO LTD
包装说明:, 4141
Reach Compliance Code:unknown
ECCN代码:EAR99
风险等级:5.69
Is Samacsys:N
电容:820 µF
电容器类型:ALUMINUM ELECTROLYTIC CAPACITOR
介电材料:ALUMINUM (SOLID POLYMER)
ESR:12 m Ω
JESD-609代码:e4
漏电流:0.775 mA
制造商序列号:SVP
安装特点:SURFACE MOUNT
负容差:20%
端子数量:2
最高工作温度:105 °C
最低工作温度:-55 °C
封装形状:CYLINDRICAL PACKAGE
极性:POLARIZED
正容差:20%
额定(直流)电压(URdc):6.3 V
纹波电流:272 mA
尺寸代码:4141
表面贴装:YES
Delta切线:0.15
端子面层:Silver (Ag)
端子形状:FLAT
Base Number Matches:1
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