74ABTH182502APMG4中文资料应用文章市场行情现货热卖使用介绍-中国IC网-芯三七

SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A

SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996

Members of the Texas Instruments

One Boundary-Scan Cell Per I/O

SCOPE Family of Testability Products

Architecture Improves Scan Efficiency

Members of the Texas Instruments

Widebus Family

SCOPE Instruction Set

– IEEE Standard 1149.1-1990 Required

Instructions and Optional CLAMP and

HIGHZ

– Parallel-Signature Analysis at Inputs

– Pseudo-Random Pattern Generation

From Outputs

– Sample Inputs/Toggle Outputs

– Binary Count From Outputs

– Device Identification

Compatible With the IEEE Standard

1149.1-1990 (JTAG) Test Access Port

and Boundary-Scan Architecture

UBT (Universal Bus Transceiver)

Combines D-Type Latches and D-Type

Flip-Flops for Operation in Transparent,

Latched, or Clocked Mode

Bus Hold on Data Inputs Eliminates the

Need for External Pullup Resistors

– Even-Parity Opcodes

Packaged in 64-Pin Plastic Thin Quad Flat

(PM) Packages Using 0.5-mm

Center-to-Center Spacings and 68-Pin

Ceramic Quad Flat (HV) Packages Using

25-mil Center-to-Center Spacings

B-Port Outputs of ’ABTH182502A Devices

Have Equivalent 25-Ω Series Resistors, So

No External Resistors Are Required

State-of-the-Art EPIC-ΙΙB BiCMOS Design

SN54ABTH18502A, SN54ABTH182502A . . . HV PACKAGE

(TOP VIEW)

9

8

7

6 5 4 3 2 1 68 67 66 65 64 63 62 61

1A3

1A4

1A5

GND

1A6

1A7

1A8

1A9

NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

60 1B4

59 1B5

58 1B6

57 GND

56 1B7

55 1B8

54 1B9

53

V

CC

52 NC

51 2B1

50 2B2

49 2B3

48 2B4

47 GND

46 2B5

45 2B6

44 2B7

V

CC

2A1

2A2

2A3

GND

2A4

2A5

2A6

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

NC – No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE, Widebus, UBT, and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A

SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996

SN74ABTH18502A, SN74ABTH182502A . . . PM PACKAGE

(TOP VIEW)

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1A3

1A4

1A5

GND

1A6

1A7

1A8

1A9

1B4

1B5

1B6

GND

1B7

1B8

1B9

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

2

3

4

5

6

7

8

V

CC

9

V

2B1

2B2

2B3

2B4

GND

2B5

2B6

2B7

CC

10

11

12

13

14

15

16

2A1

2A2

2A3

GND

2A4

2A5

2A6

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

description

The ’ABTH18502A and ’ABTH182502A scan test devices with 18-bit universal bus transceivers are members

of the Texas Instruments SCOPE testability integrated-circuit family. This family of devices supports IEEE

Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to

the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are 18-bit universal bus transceivers that combine D-type latches and D-type

flip-flops to allow data flow in transparent, latched, or clocked modes. They can be used either as two 9-bit

transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples

of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP

in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),

and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when

LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level.

Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the

B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is

similar to A-to-B data flow but uses the OEBA, LEBA, and CLKBA inputs.

In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited and the test circuitry

is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs

boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A

SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996

description (continued)

Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data

output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing

functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation

(PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

Improved scan efficiency is accomplished through the adoption of a one boundary-scan cell (BSC) per I/O pin

architecture. This architecture is implemented in such a way as to capture the most pertinent test data. A

PSA/COUNTinstruction also is included to ease the testing of memories and other circuits where a binary count

addressing scheme is useful.

Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.

The B-port outputs of ’ABTH182502A, which are designed to source or sink up to 12 mA, include 25-Ω series

resistors to reduce overshoot and undershoot.

The SN54ABTH18502A and SN54ABTH182502A are characterized for operation over the full military

temperature range of –55°C to 125°C. The SN74ABTH18502A and SN74ABTH182502A are characterized for

operation from –40°C to 85°C.

†

FUNCTION TABLE

(normal mode, each register)

INPUTS

OUTPUT

B

OEAB

LEAB

CLKAB

A

X

L

‡

B

0

L

H

L

↑

L

H

L

↑

H

L

H

X

H

X

H

Z

†

‡

A-to-B data flow is shown. B-to-A data flow is similar

but uses OEBA, LEBA, and CLKBA.

Output level before the indicated steady-state input

conditions were established

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A

SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996

functional block diagram

Boundary-Scan Register

60

1LEAB

59

1CLKAB

V

CC

62

1OEAB

1LEBA

54

55

1CLKBA

1OEBA

V

CC

53

C1

1D

C1

1D

63

51

1B1

1A1

C1

1D

C1

1D

One of Nine Channels

22

23

2LEAB

2CLKAB

V

CC

21

2OEAB

2LEBA

28

27

2CLKBA

2OEBA

V

CC

30

C1

1D

C1

1D

10

40

2B1

2A1

C1

1D

One of Nine Channels

Bypass Register

Boundary-Control

Register

Identification

Register

V

58

CC

24

TDO

Instruction

Register

TDI

V

CC

56

TMS

TCK

TAP

Controller

26

Pin numbers shown are for the PM package.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A

SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996

Terminal Functions

TERMINAL NAME

DESCRIPTION

1A1–1A9,

2A1–2A9

Normal-function A-bus I/O ports. See function table for normal-mode logic.

1B1–1B9,

2B1–2B9

Normal-function B-bus I/O ports. See function table for normal-mode logic.

1CLKAB, 1CLKBA,

2CLKAB, 2CLKBA

Normal-function clock inputs. See function table for normal-mode logic.

Ground

GND

1LEAB, 1LEBA,

2LEAB, 2LEBA

Normal-function latch enables. See function table for normal-mode logic.

1OEAB, 1OEBA,

2OEAB, 2OEBA

Normal-functionoutput enables. See function table for normal-mode logic. An internal pullup at each terminal forces the

terminal to a high level if left unconnected.

Testclock. OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.Testoperationsofthedevicearesynchronous

to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK.

TCK

TDI

Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data

through the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.

Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data

through the instruction register or selected data register.

TDO

TMS

Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP

controller states. An internal pullup forces TMS to a high level if left unconnected.

V

CC

Supply voltage

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A

SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996

test architecture

Serial-test information is conveyed by means of a 4-wire test bus or TAP that conforms to IEEE Standard

1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The

TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the

synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip

control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.

The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and

output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully

one-half of the TCK cycle.

The functional block diagram illustrates the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan

architecture and the relationship among the test bus, the TAP controller, and the test registers. As illustrated,

the device contains an 8-bit instruction register and four test-data registers: a 48-bit boundary-scan register, a

3-bit boundary-control register, a 1-bit bypass register, and a 32-bit device-identification register.

Test-Logic-Reset

TMS = H

TMS = L

TMS = H

Run-Test/Idle

Select-DR-Scan

TMS = L

Select-IR-Scan

TMS = L

TMS = H

Capture-DR

TMS = L

Capture-IR

TMS = L

Shift-DR

Shift-IR

TMS = L

TMS = H

Exit1-IR

TMS = H

Exit1-DR

TMS = L

Pause-DR

TMS = H

Pause-IR

TMS = H

Exit2-IR

TMS = L

Exit2-DR

TMS = H

Update-DR

Update-IR

TMS = H

TMS = L

TMS = H

TMS = L

Figure 1. TAP-Controller State Diagram

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A

SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996

state diagram description

TheTAPcontrollerisasynchronousfinitestatemachinethatprovidestestcontrolsignalsthroughoutthedevice.

The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller

proceeds through its states based on the level of TMS at the rising edge of TCK.

As shown, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow in

the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for consecutive

TCK cycles. Any state that does not meet this criterion is an unstable state.

There are two main paths through the state diagram: one to access and control the selected data register and

one to access and control the instruction register. Only one register can be accessed at a time.

Test-Logic-Reset

The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset

and is disabled so that the normal logic function of the device is performed. The instruction register is reset to

an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data

registers also can be reset to their power-up values.

The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more

than five TCK cycles if TMS is left high. TMS has an internal pullup resistor that forces it high if left unconnected

or if a board defect causes it to be open circuited.

For the ’ABTH18502A and ’ABTH182502A, the instruction register is reset to the binary value 10000001, which

selects the IDCODE instruction. Bits 47–44 in the boundary-scan register are reset to logic 1, ensuring that

these cells, which control A-port and B-port outputs, are set to benign values (i.e., if test mode were invoked,

the outputs would be at high-impedance state). Reset values of other bits in the boundary-scan register should

be considered indeterminate. The boundary-control register is reset to the binary value 010, which selects the

PSA test operation.

Run-Test/Idle

The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test

operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.

Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle. The test

operations selected by the boundary-control register are performed while the TAP controller is in the

Run-Test/Idle state.

Select-DR-Scan, Select-lR-Scan

No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits

either of these states on the next TCK cycle. These states allow the selection of either data-register scan or

instruction-register scan.

Capture-DR

When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the

Capture-DR state, the selected data register can capture a data value as specified by the current instruction.

Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the Capture-DR

state.

Shift-DR

Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO, and on the

first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic

level present in the least-significant bit of the selected data register.

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A

SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996

Shift-DR (continued)

While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.

The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during

the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).

The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.

Exit1-DR, Exit2-DR

The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return

to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling

edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.

Pause-DR

No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain

indefinitely. The Pause-DR state can suspend and resume data-register scan operations without loss of data.

Update-DR

If the current instruction calls for the selected data register to be updated with current data, such update occurs

on the falling edge of TCK, following entry to the Update-DR state.

Capture-IR

When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In

the Capture-IR state, the instruction register captures its current status value. This capture operation occurs

on the rising edge of TCK, upon which the TAP controller exits the Capture-IR state. For the ’ABTH18502A and

’ABTH182502A, the status value loaded in the Capture-IR state is the fixed binary value 10000001.

Shift-IR

Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO, and

on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to

the logic level present in the least-significant bit of the instruction register.

While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK

cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs

during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to

Shift-IR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-IR state.

Exit1-IR, Exit2-IR

The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to

return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the

first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.

Pause-IR

No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain

indefinitely. The Pause-IR state can suspend and resume instruction-register scan operations without loss of

data.

Update-IR

The current instruction is updated and takes effect on the falling edge of TCK, following entry to the Update-IR

state.

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A

SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996

register overview

With the exception of the bypass and device-identification registers, any test register can be thought of as a

serial-shift register with a shadow latch on each bit. The bypass and device-identification registers differ in that

they contain only a shift register. During the appropriate capture state (Capture-IR for instruction register,

Capture-DR for data registers), the shift register can be parallel loaded from a source specified by the current

instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted

out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or

Update-DR), the shadow latches are updated from the shift register.

instruction register description

The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information

contained in the instruction includes the mode of operation (either normal mode, in which the device performs

itsnormallogicfunction, ortestmode, inwhichthenormallogicfunctionisinhibitedoraltered), thetestoperation

to be performed, which of the four data registers is to be selected for inclusion in the scan path during

data-register scans, and the source of data to be captured into the selected data register during Capture-DR.

Table 3 lists the instructions supported by the ’ABTH18502A and ’ABTH182502A. The even-parity feature

specified for SCOPE devices is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any

instructions that are defined for SCOPE devices but are not supported by this device default to BYPASS.

During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted

out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value

that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated

and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the

binary value 10000001, which selects the IDCODE instruction. The IR order of scan is shown in Figure 2.

Bit 7

Parity

(MSB)

Bit 0

(LSB)

TDI

TDO

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Figure 2. Instruction Register Order of Scan

9

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SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A

SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996

data register description

boundary-scan register

The boundary-scan register (BSR) is 48 bits long. It contains one boundary-scan cell (BSC) for each

normal-function input pin and one BSC for each normal-function I/O pin (one single cell for both input data and

output data). The BSR is used to store test data that is to be applied externally to the device output pins, and/or

to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device

input pins.

The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The

contents of the BSR can change during Run-Test/Idle as determined by the current instruction. At power up or

in Test-Logic-Reset, BSCs 47–44 are reset to logic 1, ensuring that these cells, which control A-port and B-port

outputs, are set to benign values (i.e., if test mode were invoked, the outputs would be at high-impedance state).

Reset values of other BSCs should be considered indeterminate.

The BSR order of scan is from TDI through bits 47–0 to TDO. Table 1 shows the BSR bits and their associated

device pin signals.

Table 1. Boundary-Scan Register Configuration

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

47

46

45

44

43

42

41

40

39

38

37

36

2OEAB

1OEAB

2OEBA

1OEBA

2CLKAB

1CLKAB

2CLKBA

1CLKBA

2LEAB

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

2A9-I/O

2A8-I/O

2A7-I/O

2A6-I/O

2A5-I/O

2A4-I/O

2A3-I/O

2A2-I/O

2A1-I/O

1A9-I/O

1A8-I/O

1A7-I/O

1A6-I/O

1A5-I/O

1A4-I/O

1A3-I/O

1A2-I/O

1A1-I/O

17

16

15

14

13

12

11

10

9

2B9-I/O

2B8-I/O

2B7-I/O

2B6-I/O

2B5-I/O

2B4-I/O

2B3-I/O

2B2-I/O

2B1-I/O

1B9-I/O

1B8-I/O

1B7-I/O

1B6-I/O

1B5-I/O

1B4-I/O

1B3-I/O

1B2-I/O

1B1-I/O

1LEAB

8

2LEBA

7

1LEBA

6

5

4

3

2

1

0

10

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SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A

SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996

boundary-control register

The boundary-control register (BCR) is three bits long. The BCR is used in the context of the boundary-run test

(RUNT) instruction to implement additional test operations not included in the basic SCOPE instruction set.

Such operations include PRPG, PSA, and binary count up (COUNT). Table 4 shows the test operations that

are decoded by the BCR.

During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is

reset to the binary value 010, which selects the PSA test operation. The BCR order of scan is shown in

Figure 3.

Bit 2

(MSB)

Bit 0

(LSB)

TDI

TDO

Bit 1

Figure 3. Boundary-Control Register Order of Scan

bypass register

The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path,

reducing the number of bits per test pattern that must be applied to complete a test operation. During

Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in

Figure 4.

TDI

TDO

Bit 0

Figure 4. Bypass Register Order of Scan

11

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SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A

SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996

device-identification register

The device-identification register (IDR) is 32 bits long. It can be selected and read to identify the manufacturer,

part number, and version of this device.

For the ’ABTH18502A , the binary value 00000000000000100111000000101111 (0002702F, hex) is captured

(during Capture-DR state) in the IDR to identify this device as Texas Instruments SN54/74ABTH18502A.

For the ’ABTH182502A , the binary value 00000000000000101011000000101111 (0002B02F, hex) is captured

(during Capture-DR state) in the IDR to identify this device as Texas Instruments SN54/74ABTH182502A.

The IDR order of scan is from TDI through bits 31–0 to TDO. Table 2 shows the IDR bits and their significance.

Table 2. Device-Identification Register Configuration

IDR BIT

NUMBER

IDENTIFICATION

SIGNIFICANCE

IDR BIT

NUMBER

IDENTIFICATION

SIGNIFICANCE

IDR BIT

NUMBER

IDENTIFICATION

SIGNIFICANCE

†

31

30

29

28

VERSION3

VERSION2

VERSION1

VERSION0

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

PARTNUMBER15

PARTNUMBER14

PARTNUMBER13

PARTNUMBER12

PARTNUMBER11

PARTNUMBER10

PARTNUMBER09

PARTNUMBER08

PARTNUMBER07

PARTNUMBER06

PARTNUMBER05

PARTNUMBER04

PARTNUMBER03

PARTNUMBER02

PARTNUMBER01

PARTNUMBER00

11

10

9

MANUFACTURER10

MANUFACTURER09

MANUFACTURER08

MANUFACTURER07

MANUFACTURER06

MANUFACTURER05

MANUFACTURER04

MANUFACTURER03

MANUFACTURER02

MANUFACTURER01

MANUFACTURER00

8

7

6

5

4

3

2

1

†

LOGIC1

0

†

Note that for TI products, bits 11–0 of the device-identification register always contain the binary value 000000101111

(02F, hex).

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instruction-register opcode description

The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of each

instruction.

Table 3. Instruction-Register Opcodes

†

BINARY CODE

BIT 7 → BIT 0

MSB → LSB

SELECTED DATA

REGISTER

SCOPE OPCODE

DESCRIPTION

MODE

00000000

10000001

10000010

00000011

10000100

00000101

00000110

10000111

10001000

00001001

00001010

10001011

00001100

10001101

10001110

00001111

All others

EXTEST

IDCODE

Boundary scan

Identification read

Boundary scan

Device identification

Boundary scan

Bypass

Test

Normal

Modified test

Test

SAMPLE/PRELOAD

Sample boundary

‡

BYPASS

HIGHZ

Bypass scan

Bypass

Bypass scan

Bypass

Control boundary to high impedance

Control boundary to 1/0

Bypass scan

Bypass

CLAMP

Bypass

‡

BYPASS

Bypass

Normal

Test

RUNT

Boundary-run test

Bypass

READBN

READBT

CELLTST

TOPHIP

SCANCN

SCANCT

BYPASS

Boundary read

Boundary scan

Bypass

Normal

Test

Boundary read

Boundary self test

Boundary toggle outputs

Boundary-control register scan

Bypass scan

Normal

Test

Boundary control

Bypass

Normal

Test

Normal

†

‡

Bit 7 is used to maintain even parity in the 8-bit instruction.

The BYPASS instruction is executed in lieu of a SCOPE instruction that is not supported in the ’ABTH18502A or ’ABTH182502A.

boundary scan

This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST instruction. The BSR is selected in the

scan path. Data appearing at the device input and I/O pins is captured in the associated BSCs. Data that has

been scanned into the I/O BSCs for pins in the output mode is applied to the device I/O pins. Data present at

the device pins, except for output-enables, is passed through the BSCs to the normal on-chip logic. For I/O pins,

the operation of a pin as input or output is determined by the contents of the output-enable BSCs (bits 47–44

of the BSR). When a given output enable is active (logic 0), the associated I/O pins operate in the output mode.

Otherwise, the I/O pins operate in the input mode. The device operates in the test mode.

identification read

This instruction conforms to the IEEE Standard 1149.1-1990 IDCODE instruction. The IDR is selected in the

scan path. The device operates in the normal mode.

sample boundary

This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is

selected in the scan path. Data appearing at the device input pins and I/O pins in the input mode is captured

in the associated BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the BSCs

associated with I/O pins in the output mode. The device operates in the normal mode.

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bypass scan

This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is

selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device

operates in the normal mode.

control boundary to high impedance

This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is

selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device

operates in a modified test mode in which all device I/O pins are placed in the high-impedance state, the device

input pins remain operational, and the normal on-chip logic function is performed.

control boundary to 1/0

This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is

selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the I/O

BSCs for pins in the output mode is applied to the device I/O pins. The device operates in the test mode.

boundary-run test

The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during

Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during

Run-Test/Idle. The five test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP),

PRPG, PSA, simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up

(PSA/COUNT).

boundary read

The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This

instruction is useful for inspecting data after a PSA operation.

boundary self test

The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR.

In this way, the contents of the shadow latches can be read out to verify the integrity of both shift-register and

shadow-latch elements of the BSR. The device operates in the normal mode.

boundary toggle outputs

The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during

Capture-DR. Data in the shift-register elements of the selected output-mode BSCs is toggled on each rising

edge of TCK in Run-Test/Idle, updated in the shadow latches, and applied to the associated device I/O pins on

each falling edge of TCK in Run-Test/Idle. Data in the input-mode BSCs remains constant. Data appearing at

the device input or I/O pins is not captured in the input-mode BSCs. The device operates in the test mode.

boundary-control-register scan

The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This

operation must be performed before a RUNT operation to specify which test operation is to be executed.

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boundary-control-register opcode description

TheBCRopcodesaredecodedfromBCRbits2–0asshowninTable4. Theselectedtestoperationisperformed

while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation

of each BCR instruction and illustrate the associated PSA and PRPG algorithms.

Table 4. Boundary-Control Register Opcodes

BINARY CODE

BIT 2 → BIT 0

MSB → LSB

DESCRIPTION

X00

X01

X10

011

111

Sample inputs/toggle outputs (TOPSIP)

Pseudo-random pattern generation/36-bit mode (PRPG)

Parallel-signature analysis/36-bit mode (PSA)

Simultaneous PSA and PRPG/18-bit mode (PSA/PRPG)

Simultaneous PSA and binary count up/18-bit mode (PSA/COUNT)

While the control input BSCs (bits 47–36) are not included in the toggle, PSA, PRPG, or COUNT algorithms,

theoutput-enableBSCs(bits47–44oftheBSR)controlthedrivestate(activeorhighimpedance)oftheselected

device output pins. These BCR instructions are valid only when both bytes of the device are operating in one

direction of data flow (that is, 1OEAB ≠ 1OEBA and 2OEAB ≠ 2OEBA) and in the same direction of data flow

(that is, 1OEAB = 2OEAB and 1OEBA = 2OEBA). Otherwise, the bypass instruction is operated.

sample inputs/toggle outputs (TOPSIP)

Data appearing at the selected device input-mode I/O pins is captured in the shift-register elements of the

associated BSCs on each rising edge of TCK. Data in the shift-register elements of the selected output-mode

BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated

device I/O pins on each falling edge of TCK.

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pseudo-random pattern generation (PRPG)

A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge

of TCK, updated in the shadow latches, and applied to the associated device output-mode I/O pins on each

falling edge of TCK. Figures 5 and 6 illustrate the 36-bit linear-feedback shift-register algorithms through which

the patterns are generated. An initial seed value should be scanned into the BSR before performing this

operation. A seed value of all zeroes does not produce additional patterns.

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

=

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

Figure 5. 36-Bit PRPG Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)

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pseudo-random pattern generation (PRPG) (continued)

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

=

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

Figure 6. 36-Bit PRPG Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0)

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parallel-signature analysis (PSA)

Data appearing at the selected device input-mode I/O pins is compressed into a 36-bit parallel signature in the

shift-register elements of the selected BSCs on each rising edge of TCK. Data in the shadow latches of the

selected output-mode BSCs remains constant and is applied to the associated device I/O pins. Figures 7 and 8

illustrate the 36-bit linear-feedback shift-register algorithms through which the signature is generated. An initial

seed value should be scanned into the BSR before performing this operation.

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

=

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

Figure 7. 36-Bit PSA Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)

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parallel-signature analysis (PSA) (continued)

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

=

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

Figure 8. 36-Bit PSA Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0)

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simultaneous PSA and PRPG (PSA/PRPG)

Data appearing at the selected device input-mode I/O pins is compressed into an 18-bit parallel signature in

the shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, an

18-bit pseudo-random pattern is generated in the shift-register elements of the selected output-mode BSCs on

each rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each

falling edge of TCK. Figures 9 and 10 illustrate the 18-bit linear-feedback shift-register algorithms through which

the signature and patterns are generated. An initial seed value should be scanned into the BSR before

performing this operation. A seed value of all zeroes does not produce additional patterns.

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

=

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

Figure 9. 18-Bit PSA/PRPG Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)

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simultaneous PSA and PRPG (PSA/PRPG) (continued)

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

=

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

Figure 10. 18-Bit PSA/PRPG Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0)

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simultaneous PSA and binary count up (PSA/COUNT)

Data appearing at the selected device input-mode I/O pins is compressed into an 18-bit parallel signature in

the shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, an

18-bit binary count-up pattern is generated in the shift-register elements of the selected output-mode BSCs on

each rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each

falling edge of TCK. Figures 11 and 12 illustrate the 18-bit linear-feedback shift-register algorithms through

which the signature is generated. An initial seed value should be scanned into the BSR before performing this

operation.

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

MSB

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

LSB

=

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

Figure 11. 18-Bit PSA/COUNT Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)

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simultaneous PSA and binary count up (PSA/COUNT) (continued)

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

MSB

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

LSB

=

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

Figure 12. 18-Bit PSA/COUNT Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0)

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timing description

All test operations of the ’ABTH18502A and ’ABTH182502A are synchronous to TCK. Data on the TDI, TMS,

andnormal-functioninputsiscapturedontherisingedgeofTCK. DataappearsontheTDOandnormal-function

output pins on the falling edge of TCK. The TAP controller is advanced through its states (as shown in Figure 1)

by changing the value of TMS on the falling edge of TCK and then applying a rising edge to TCK.

A simple timing example is shown in Figure 13. In this example, the TAP controller begins in the

Test-Logic-Reset state and is advanced through its states, to perform one instruction-register scan and one

data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data, and TDO is used

to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 5 details the

operation of the test circuitry during each TCK cycle.

Table 5. Explanation of Timing Example

TCK

CYCLE(S)

TAP STATE

AFTER TCK

DESCRIPTION

TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward

the desired state.

1

Test-Logic-Reset

2

3

4

Run-Test/Idle

Select-DR-Scan

Select-IR-Scan

The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the

Capture-IR state.

5

6

Capture-IR

Shift-IR

TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on

the rising edge of TCK as the TAP controller advances to the next state.

One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value

11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned

out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next TCK

cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR.

7–13

Shift-IR

14

15

16

Exit1-IR

Update-IR

TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.

The IR is updated with the new instruction (BYPASS) on the falling edge of TCK.

Select-DR-Scan

The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the

Capture-DR state.

17

18

Capture-DR

Shift-DR

TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on

the rising edge of TCK as the TAP controller advances to the next state.

19–20

21

Shift-DR

Exit1-DR

The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.

TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.

In general, the selected data register is updated with the new data on the falling edge of TCK.

22

Update-DR

23

Select-DR-Scan

Select-IR-Scan

24

25

Test-Logic-Reset Test operation completed

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timing description (continued)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

TCK

TMS

TDI

TDO

TAP

Controller

State

3-State (TDO) or Don’t Care (TDI)

Figure 13. Timing Example

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V

CC

Input voltage range, V : except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V

I

I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V

Voltage range applied to any output in the high state or power-off state, V

. . . . . . . . . . . . . . –0.5 V to 5.5 V

O

Current into any output in the low state, I : SN54ABTH18502A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA

O

SN54ABTH182502A (A port or TDO) . . . . . . . . . . . . . . . . . 96 mA

SN54ABTH182502A (B port) . . . . . . . . . . . . . . . . . . . . . . . . 30 mA

SN74ABTH18502A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA

SN74ABTH182502A (A port or TDO) . . . . . . . . . . . . . . . . 128 mA

SN74ABTH182502A (B port) . . . . . . . . . . . . . . . . . . . . . . . . 30 mA

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA

IK

OK

I

Output clamp current, I

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA

O

Continuous current through V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 mA

CC

Continuous current through GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152 mA

Maximum power dissipation at T = 55°C (in still air) (see Note 2): PM package . . . . . . . . . . . . . . . . . . . . 1 W

A

stg

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings can be exceeded if the input and output clamp-current ratings are observed.

2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 75 mils.

Formoreinformation, refertothePackageThermalConsiderationsapplicationnoteintheABTAdvancedBiCMOSTechnologyData

Book, literature number SCBD002.

25

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recommended operating conditions

SN54ABTH18502A SN74ABTH18502A

UNIT

MIN

4.5

2

MAX

MIN

4.5

2

MAX

V

Supply voltage

5.5

V

CC

IH

High-level input voltage

Low-level input voltage

Input voltage

0.8

V

IL

0

V

0

V

CC

V

I

CC

I

High-level output current

Low-level output current

Input transition rise or fall rate

Operating free-air temperature

–24

–32

mA

ns/V

°C

OH

48

64

OL

∆t/∆v

10

T

–55

125

–40

85

A

26

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SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54ABTH18502A

PARAMETER

TEST CONDITIONS

T

A

= 25°C

T

A

= –55°C to 125°C

UNIT

V

†

TYP

MIN

MAX

MIN

MAX

V

CC

V

CC

V

CC

V

CC

V

CC

= 4.5 V,

= 5 V,

I = –18 mA

–1.2

IK

I

= –3 mA

= –24 mA

= 48 mA

2.5

3

2.5

3

OH

OL

V

OH

OL

= 4.5 V,

2

0.55

V

CLK, LE, TCK

V

= 0 to 5.5 V,

V = V

or GND

±1

CC

I

CC

V

CC

= 0 to 5.5 V,

I

µA

A or B ports

V

CC

V

CC

V

CC

= 5.5 V,

V = V

I

V = V

I

V = GND

I

V = 0.8 V

I

±20

10

±20

10

CC

I

OE, TDI, TMS

µA

IH

–40

75

–150

500

–40

75

–150

500

IL

220

‡

I

A or B ports

TDO

V

CC

= 4.5 V

µA

I(hold)

V = 2 V

I

–75

–180

–500

–75

–500

V

= 2.1 V to 5.5 V,

= 2.7 V, OE = 2 V

CC

O

10

–10

±50

10

–10

±50

I

OZH

V

= 2.1 V to 5.5 V,

= 0.5 V, OE = 2 V

CC

O

TDO

OZL

V

= 0 to 2.1 V,

= 2.7 V or 0.5 V,

CC

O

TDO

OZPU

OZPD

OE = 0.8 V

V

= 2.1 V to 0,

= 2.7 V or 0.5 V,

CC

O

TDO

OE = 0.8 V

I

V

= 0,

V or V ≤ 4.5 V

±100

50

µA

off

CC

I

O

Outputs high

= 5.5 V,

V

= 5.5 V

50

–200

5.5

CEX

O

§

V

= 2.5 V

–50

–110

1.6

19

–200

5.5

–50

mA

O

Outputs high

Outputs low

V

I

= 5.5 V,

= 0,

CC

O

I

A or B ports

24

mA

CC

V = V

I

or GND

CC

= 5.5 V, One input at 3.4 V,

Outputs disabled

0.9

3.6

V

CC

Other inputs at V

¶

1.5

mA

∆I

CC

or GND

CC

V = 2.5 V or 0.5 V

C

Control inputs

A or B ports

TDO

7

10

7

pF

i

I

V

O

V

O

= 2.5 V or 0.5 V

io

o

†

‡

§

¶

All typical values are at V

= 5 V.

CC

includes the off-state output leakage current.

The parameter I

I(hold)

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

This is the increase in supply current for each input that is at the specified TTL voltage level rather than V

or GND.

CC

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SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN74ABTH18502A

PARAMETER

TEST CONDITIONS

T

A

= 25°C

T

A

= –40°C to 85°C

UNIT

†

TYP

MIN

MAX

MIN

MAX

V

= 4.5 V,

= 5 V,

I = –18 mA

–1.2

V

IK

CC

I

= –3 mA

= –24 mA

= –32 mA

= 48 mA

= 64 mA

2.5

3

2.5

3

OH

OL

V

OH

2

V

= 4.5 V

CC

2

0.55

±1

V

OL

V

0.55

±1

CLK, LE, TCK

A or B ports

V

CC

V

CC

V

CC

V

CC

= 0 to 5.5 V,

= 5.5 V,

V = V

or GND

I

CC

I

µA

V = V

I

±20

10

±20

10

I

OE, TDI, TMS

= 5.5 V,

V = V

I

µA

IH

= 5.5 V,

V = GND

I

–40

75

–150

500

–40

75

–150

500

–500

IL

V = 0.8 V

I

220

‡

A or B ports

V

CC

= 4.5 V

µA

I

I(hold)

V = 2 V

I

–75

–180 –500

–75

V

= 2.1 V to 5.5 V,

= 2.7 V, OE = 2 V

CC

O

TDO

10

–10

±50

µA

I

OZH

V

= 2.1 V to 5.5 V,

= 0.5 V, OE = 2 V

CC

O

–10

±50

OZL

V

= 0 to 2.1 V,

= 2.7 V or 0.5 V, OE = 0.8 V

CC

O

OZPU

OZPD

V

= 2.1 V to 0,

= 2.7 V or 0.5 V,

CC

O

OE = 0.8 V

I

V

= 0,

V or V ≤ 4.5 V

±100

50

±100

50

µA

off

CC

I

O

Outputs high

= 5.5 V,

V

= 5.5 V

CEX

O

§

V

= 2.5 V

–50

–110 –200

–50

–200

2.2

24

mA

O

Outputs high

Outputs low

1.6

19

2.2

24

2

V

I

= 5.5 V,

= 0,

CC

O

I

A or B ports

mA

CC

V = V

or GND

I

CC

Outputs disabled

0.9

2

V

= 5.5 V, One input at 3.4 V,

CC

Other inputs at V

¶

1.5

mA

∆I

CC

or GND

CC

V = 2.5 V or 0.5 V

C

Control inputs

A or B ports

TDO

5

10

8

pF

i

I

V

= 2.5 V or 0.5 V

io

o

O

V

†

‡

§

¶

All typical values are at V

= 5 V.

CC

The parameter I

includes the off-state output leakage current.

I(hold)

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.

CC

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timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (normal mode) (see Figure 14)1

SN54ABTH18502A SN74ABTH18502A

UNIT

MIN

MAX

MIN

MAX

f

t

Clock frequency

Pulse duration

CLKAB or CLKBA

0

100

0

100

MHz

ns

clock

CLKAB or CLKBA high or low

LEAB or LEBA high

3.8

3.5

4.0

2

3.5

2

w

A before CLKAB↑ or B before CLKBA↑

t

Setup time

Hold time

CLK high

CLK low

ns

su

A before LEAB↓ or B before LEBA↓

A after CLKAB↑ or B after CLKBA↑

A after LEAB↓ or B after LEBA↓

2.9

4.0

0.5

3

h

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (test mode) (see Figure 14)

SN54ABTH18502A SN74ABTH18502A

UNIT

MIN

MAX

MIN

MAX

f

t

Clock frequency

Pulse duration

TCK

0

50

0

50

MHz

ns

clock

TCK high or low

8

w

A, B, CLK, LE, or OE before TCK↑

TDI before TCK↑

6

t

Setup time

Hold time

4.5

3

4.5

3

ns

su

h

TMS before TCK↑

A, B, CLK, LE, or OE after TCK↑

TDI after TCK↑

2.9

1

1.5

1

t

TMS after TCK↑

1.5

50*

1*

1.5

50

1

t

Delay time

Rise time

Power up to TCK↑

ns

d

V

CC

power up

µs

r

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

29

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SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (normal mode) (see Figure 14)1

SN54ABTH18502A

FROM

(INPUT)

TO

(OUTPUT)

V

T

= 5 V,

= 25°C

V

= 4.5 V to 5.5 V,

CC

A

CC

T = –55°C to 125°C

A

PARAMETER

UNIT

MIN

100

1.5

2.8

2

TYP

130

3.1

3.6

3.7

3.8

3.9

3.6

4

MAX

MIN

100

MAX

f

t

CLKAB or CLKBA

A or B

MHz

ns

max

PLH

PHL

PLH

PHL

PLH

PHL

PZH

PZL

PHZ

PLZ

5

1.5

2.8

2

6

B or A

5.2

5.5

5.8

7.2

6

6.4

6.5

7.5

8.9

7.5

CLKAB or CLKBA

LEAB or LEBA

ns

OEAB or OEBA

4.2

5.9

4.5

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (normal mode) (see Figure 14)

SN74ABTH18502A

FROM

(INPUT)

TO

(OUTPUT)

V

T

= 5 V,

= 25°C

V

= 4.5 V to 5.5 V,

CC

A

CC

T = –40°C to 85°C

A

PARAMETER

UNIT

MIN

100

1.5

3

TYP

130

3.1

3.6

3.7

3.8

3.9

3.6

4

MAX

MIN

100

MAX

f

t

CLKAB or CLKBA

A or B

MHz

ns

max

PLH

PHL

PLH

PHL

PLH

PHL

PZH

PZL

PHZ

PLZ

5

1.5

3

5.5

B or A

5.5

6

5

CLKAB or CLKBA

LEAB or LEBA

ns

5

5.5

5.8

7

6

7

OEAB or OEBA

4.2

5.9

4.5

7

8

2

6

2

7

30

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switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (test mode) (see Figure 14)

V

T

= 5 V,

= 25°C

CC

A

SN54ABTH18502A

SN74ABTH18502A

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

UNIT

MIN

50

2.5

2

TYP

90

MAX

MIN

50

2.5

2

MAX

MIN

50

2.5

2

MAX

f

t

TCK

MHz

ns

max

PLH

PHL

PLH

PHL

PZH

PZL

PZH

PZL

PHZ

PLZ

PHZ

PLZ

7.4

7.6

3.8

4

11

10.8

5.1

14.5

14

7

13.1

12.4

5.6

13.4

13.6

6.6

6.9

15

TCK↓

A or B

TDO

TCK↓

ns

2

5.1

2

7

2

4

8

11.5

11.8

5.7

4

14.5

15

7.5

8

4

A or B

TDO

4

8

4

2

3.9

4.2

10.8

9.1

5.3

4.2

2

6.2

2

4

13

4

18

17.5

8

4

A or B

TDO

3

13.3

6.8

3

15

3

7.2

6.3

2.5

5.5

2.5

8

2.5

31

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recommended operating conditions

SN54ABTH182502A SN74ABTH182502A

UNIT

MIN

4.5

2

MAX

MIN

4.5

2

MAX

V

CC

V

IH

V

IL

V

I

Supply voltage

5.5

V

High-level input voltage

Low-level input voltage

Input voltage

0.8

0

V

CC

0

V

CC

A port, TDO

B port

–24

–12

48

–32

–12

64

I

High-level output current

Low-level output current

mA

OH

OL

A port, TDO

B port

I

12

∆t/∆v

Input transition rise or fall rate

Operating free-air temperature

10

ns/V

T

A

–55

125

–40

85

°C

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

32

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SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

T

= 25°C

SN54ABTH182502A SN74ABTH182502A

A

PARAMETER

A port, TDO

B port

TEST CONDITIONS

UNIT

†

MIN TYP

MAX

MIN

MAX

MIN

MAX

V

= 4.5 V, I = –18 mA

–1.2

V

IK

CC

I

= 4.5 V,

= 5 V,

I

= –3 mA

= –24 mA

= –32 mA

= –1 mA

= –3 mA

= –12 mA

= 48 mA

= 64 mA

= 8 mA

2.5

3

2.5

3

2.5

3

OH

OL

2

V

CC

= 4.5 V

2*

2

3.35

3.85

3.1

V

OH

V

= 4.5 V,

= 5 V,

3.35

3.85

3.1

2.6*

3.3

3.8

3

CC

V

= 4.5 V

CC

2.6

0.55

0.55*

0.8

0.55

0.8

A port, TDO

B port

V

0.55

0.65

0.8

V

OL

V

CC

= 12 mA

0.8*

= 0 to 5.5 V,

or GND

CC

CLK, LE, TCK

A or B ports

±1

V = V

I

CC

= 5.5 V,

I

µA

V

CC

V = V

±20

or GND

I

CC

= 5.5 V, V = V

I

OE, TDI, TMS

V

10

–150

500

10

–150

500

µA

IH

CC

I

CC

V

= 5.5 V, V = GND

–40

–150

–40

75

IL

I

V = 0.8 V

75

220

I

‡

A or B ports

V

CC

= 4.5 V

µA

I

I(hold)

V = 2 V

I

–75

–180

–500

–75

–500

V

= 2.1 V to 5.5 V,

OE = 2 V

CC

O

TDO

10

–10

±50

10

–10

±50

µA

I

OZH

= 2.7 V,

V

= 2.1 V to 5.5 V,

CC

O

–10

OZL

= 0.5 V,

OE = 2 V

V

= 0 to 2.1 V,

= 2.7 V or 0.5 V, OE = 0.8 V

CC

O

OZPU

OZPD

V

= 2.1 V to 0,

= 2.7 V or 0.5 V, OE = 0.8 V

CC

O

I

V

= 0, V or V ≤ 4.5 V

±100

50

±100

50

µA

off

CC

I

O

Outputs high

A port, TDO

B port

= 5.5 V,

V

= 5.5 V

= 2.5 V

50

–200

–100

2.2

CEX

O

= 5.5 V,

V

–50

–25

–110

–55

1.6

–200

–100

2.2

–50

–25

–50

–25

–200

–100

2.2

§

mA

I

O

Outputs high

Outputs low

V

= 5.5 V,

CC

21

27

I

O

= 0,

I

A or B ports

mA

CC

V = V

or

I

CC

Outputs

disabled

0.9

2

GND

V

= 5.5 V, One input at 3.4 V,

CC

Other inputs at V

¶

1.5

∆I

CC

or GND

CC

* On products compliant to MIL-PRF-38535, this parameter does not apply.

†

‡

§

¶

All typical values are at V

= 5 V.

CC

includes the off-state output leakage current.

The parameter I

I(hold)

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.

CC

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

33

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCAN TEST DEVICES

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SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

T

= 25°C

SN54ABTH182502A SN74ABTH182502A

MIN MAX MIN MAX

A

PARAMETER

TEST CONDITIONS

UNIT

†

MIN TYP

MAX

Control

inputs

C

V = 2.5 V or 0.5 V

I

5

pF

i

C

A or B ports

TDO

V

= 2.5 V or 0.5 V

= 5 V.

10

8

pF

io

o

O

†

All typical values are at V

CC

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (normal mode) (see Figure 14)12

SN54ABTH182502A SN74ABTH182502A

UNIT

MIN

MAX

MIN

MAX

f

t

Clock frequency

Pulse duration

CLKAB or CLKBA

0

100

0

100

MHz

ns

clock

CLKAB or CLKBA high or low

LEAB or LEBA high

3.5

2

3.5

2

w

A before CLKAB↑ or B before CLKBA↑

t

Setup time

Hold time

CLK high

CLK low

ns

su

h

A before LEAB↓ or B before LEBA↓

A after CLKAB↑ or B after CLKBA↑

A after LEAB↓ or B after LEBA↓

0.5

3

0.5

3

t

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (test mode) (see Figure 14)

SN54ABTH182502A SN74ABTH182502A

UNIT

MIN

MAX

MIN

MAX

f

t

Clock frequency

Pulse duration

TCK

0

50

0

50

MHz

ns

clock

TCK high or low

8

w

A, B, CLK, LE, or OE before TCK↑

TDI before TCK↑

6

t

Setup time

Hold time

4.5

3

4.5

3

ns

su

h

TMS before TCK↑

A, B, CLK, LE, or OE after TCK↑

TDI after TCK↑

1.5

1

1.5

1

t

TMS after TCK↑

1.5

50

1

1.5

50

1

t

Delay time

Rise time

Power up to TCK↑

ns

d

V

CC

power up

µs

r

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

34

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A

SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (normal mode) (see Figure 14)12

V

T

= 5 V,

= 25°C

CC

A

SN54ABTH182502A SN74ABTH182502A

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

UNIT

MIN

TYP

MAX

MIN

MAX

MIN

MAX

CLKAB or

CLKBA

f

100

130

100

MHz

ns

max

t

1.5

3

3.1

3.6

3.1

3.6

3.7

4

5

5.6

5

1.5

3

6

6.4

6

1.5

3

5.5

6.2

5.5

6.1

6.2

5.5

6.3

6.2

6

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

PZH

PZL

PHZ

PLZ

A

B

A

ns

5

6

5.4

5.8

5

6.2

6.4

6

CLKAB

CLKBA

LEAB

LEBA

B

A

3.7

3.8

3.9

3.6

3.9

3.6

4

5

6

5.6

5.5

5.8

7

6.5

7.5

8.5

7.5

B

A

6

7

B or A

OEAB or OEBA

4.2

5.9

4.5

7

8

2

6

2

7

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (test mode) (see Figure 14)

V

T

= 5 V,

= 25°C

CC

A

SN54ABTH182502A SN74ABTH182502A

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

UNIT

MIN

50

2.5

2

TYP

90

MAX

MIN

50

2.5

2

MAX

MIN

50

2.5

2

MAX

f

t

TCK

MHz

ns

max

PLH

PHL

PLH

PHL

PZH

PZL

PZH

PZL

PHZ

PLZ

PHZ

PLZ

7.4

7.6

3.8

4

11

10.8

5.1

14.5

14

7

13.1

12.4

5.6

13.4

13.6

6.6

6.9

15

TCK↓

A or B

TDO

TCK↓

ns

2

5.1

2

7

2

4

8

11.5

11.8

5.7

4

14.5

15

7.5

8

4

A or B

TDO

4

8

4

2

3.9

4.2

10.8

9.1

5.3

4.2

2

6.2

2

4

13

4

18

17.5

8

4

A or B

TDO

3

13.3

6.8

3

15

3

7.2

6.3

2.5

5.5

2.5

8

2.5

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

35

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A

SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996

PARAMETER MEASUREMENT INFORMATION

7 V

S1

500 Ω

Open

GND

From Output

Under Test

TEST

S1

t

/t

Open

7 V

PLH PHL

/t

C

= 50 pF

L

t

500 Ω

PLZ PZL

/t

(see Note A)

Open

PHZ PZH

LOAD CIRCUIT

3 V

0 V

Timing Input

Data Input

1.5 V

t

w

t

h

su

3 V

0 V

3 V

0 V

Input

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

3 V

0 V

3 V

0 V

Output

Control

1.5 V

Input

1.5 V

t

PZL

t

PHL

PLH

PHL

t

PLZ

Output

Waveform 1

S1 at 7 V

V

3.5 V

OH

1.5 V

Output

V

+ 0.3 V

– 0.3 V

OL

V

OL

(see Note B)

t

PHZ

t

PLH

t

PZH

Output

Waveform 2

S1 at Open

(see Note B)

V

OH

V

OH

1.5 V

Output

0 V

OL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

NOTES: A.

C includes probe and jig capacitance.

L

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

O

r

f

D. The outputs are measured one at a time with one transition per measurement.

Figure 14. Load Circuit and Voltage Waveforms

36

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

18-Jul-2006

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

5962-9561401QXA

ACTIVE

CFP

HV

68

64

1

TBD

POST-PLATE N / A for Pkg Type

74ABTH182502APMG4

LQFP

PM

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

74ABTH18502APMRG4

SN74ABTH182502APM

SN74ABTH18502APM

SN74ABTH18502APMG4

SN74ABTH18502APMR

SNJ54ABTH18502AHV

ACTIVE

LQFP

CFP

PM

HV

64

68

1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

1

TBD

POST-PLATE N / A for Pkg Type

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Mar-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

SN74ABTH18502APMR

LQFP

PM

64

1000

330.0

24.4

12.3

2.5

16.0

24.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Mar-2008

*All dimensions are nominal

Device

Package Type Package Drawing Pins

LQFP PM 64

SPQ

Length (mm) Width (mm) Height (mm)

346.0 346.0 41.0

SN74ABTH18502APMR

1000

Pack Materials-Page 2

MECHANICAL DATA

MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996

PM (S-PQFP-G64)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

M

0,08

33

48

49

32

64

17

0,13 NOM

1

16

7,50 TYP

Gage Plane

10,20

SQ

9,80

0,25

12,20

SQ

0,05 MIN

0°–7°

11,80

1,45

1,35

0,75

0,45

Seating Plane

0,08

1,60 MAX

4040152/C 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

D. May also be thermally enhanced plastic with leads connected to the die pads.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

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