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产品型号74AHCT74D的概述

芯片74AHCT74D的概述 74AHCT74D是一款双D触发器，它基于74系列逻辑芯片，适用于高速数字电路设计中。74AHCT74D使用AHCT（Advanced High-speed CMOS Technology）技术，这使其在较高频率下仍能保持出色的性能，尤其是在低电压条件下的稳定性和功耗方面。该芯片适合在高达大约5V的电源电压下工作，宽广的电压范围使其能在多种应用中发挥作用。 74AHCT74D的基本功能是储存二进制信息。D触发器能够在时钟信号的上升沿或下降沿（取决于具体连接方式）捕捉输入端D的状态，并将其存储在输出端Q中。这种特性使其在数据寄存、状态机以及同步电路设计中尤为重要。芯片74AHCT74D的详细参数电气特性 - 电源电压 (Vcc): 4.5V 至 5.5V - 输入电平: - 高电平（VIH）: 2.0V 最小 - 低电平（VIL）: 0.8V...

产品型号74AHCT74D的Datasheet PDF文件预览

INTEGRATED CIRCUITS

DATA SHEET

74AHC74; 74AHCT74

Dual D-type flip-flop with set and

reset; positive-edge trigger

Product speciﬁcation

1999 Sep 23

Supersedes data of 1999 Aug 05

File under Integrated Circuits, IC06

Philips Semiconductors

Product speciﬁcation

Dual D-type ﬂip-ﬂop with set and reset;

positive-edge trigger

74AHC74; 74AHCT74

FEATURES

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C; t_r= t_f≤ 3.0 ns.

• ESD protection:

HBM EIA/JESD22-A114-A

exceeds 2000 V

MM EIA/JESD22-A115-A

exceeds 200 V

TYPICAL

SYMBOL

PARAMETER

CONDITIONS

UNIT

AHC AHCT

t_PHL/t_PLHpropagation delay

nCP to nQ, nQ

C_L= 15 pF;

V_CC= 5 V

• Balanced propagation delays

3.7

3.3

3.7

• Inputs accepts voltages higher than

nS_D, nR_Dto nQ, nQ

V_CC

f_max

C_I

max. clock frequency

input capacitance

130 100

MHz

• For AHC only:

operates with CMOS input levels

V_I= V_CCor GND 4.0

4.0

C_PD

power dissipation

capacitance

C_L= 50 pF;

f = 1 MHz;

notes 1 and 2

• For AHCT only:

operates with TTL input levels

• Output capability: standard

• I_CCcategory: flip-flops

Notes

1. C_PDis used to determine the dynamic power dissipation (P_Din µW).

P_D= C_PD× V_CC²× f_i+ ∑ (C_L× V_CC²× f_o) where:

f_i= input frequency in MHz; f_o= output frequency in MHz;

∑ (C_L× V_CC²× f_o) = sum of outputs;

• Specified from

−40 to +85 and +125 °C.

DESCRIPTION

C_L= output load capacitance in pF;

The 74AHC/AHCT74 are high-speed

Si-gate CMOS devices and are pin

compatible with low power Schottky

TTL (LSTTL). They are specified in

compliance with JEDEC standard

No. 7A.

V_CC= supply voltage in Volts.

2. The condition is V_I= GND to V_CC

FUNCTION TABLES

Table 1 See note 1

INPUT

The 74AHC/AHCT74 dual

positive-edge triggered, D-type

flip-flops with individual data (D)

inputs, clock (CP) inputs, set (S_D) and

reset (R_D) inputs; also

OUTPUT

nS_D

nR_D

nCP

complementary Q and Q outputs.

The set and reset are asynchronous

active LOW inputs and operate

independently of the clock input.

Information on the data input is

transferred to the Q output on the

LOW-to-HIGH transition of the clock

pulse. The D inputs must be stable

one set-up time prior to the

Table 2 See note 1

INPUT

OUTPUT

nS_D

nR_D

nCP

nQ_n+1

↑

LOW-to-HIGH clock transition for

predictable operation.

Note to Tables 1 and 2

1. H = HIGH voltage level;

L = LOW voltage level;

X = don’t care;

Schmitt-trigger action in the clock

input makes the circuit highly tolerant

to slower clock rise and fall times.

↑ = LOW-to-HIGH CP transition;

Q_n+1= state after the next LOW-to-HIGH CP transition.

1999 Sep 23

Philips Semiconductors

Product speciﬁcation

Dual D-type ﬂip-ﬂop with set and reset;

positive-edge trigger

74AHC74; 74AHCT74

ORDERING INFORMATION

OUTSIDE

PACKAGE

NORTH

AMERICA

NORTH AMERICA

TEMPERATURE

RANGE

PINS

PACKAGE

MATERIAL

CODE

74AHC74D

−40 to +85 °C

plastic

SOT108-1

SOT402-1

SOT108-1

SOT402-1

74AHC74PW

74AHCT74D

74AHCT74PW

74AHC74PW DH

74AHCT74D

TSSOP

74AHCT74PW DH

TSSOP

PINNING

SYMBOL

DESCRIPTION

1 and 13

2 and 12

3 and 11

4 and 10

5 and 9

6 and 8

1R_Dand 2R_D

1D and 2D

1CP and 2CP

1S_Dand 2S_D

1Q and 2Q

GND

asynchronous reset-direct input (active LOW)

data inputs

clock input (LOW-to-HIGH, edge-triggered)

asynchronous set-direct input (active LOW)

true ﬂip-ﬂop outputs

complement ﬂip-ﬂop outputs

ground (0 V)

V_CC

DC supply voltage

handbook, halfpage

1S 2S

1CP

2CP

1CP

2CP

10 2S

1R 2R

GND

1 13

MNA418

MNA417

Fig.1 Pin configuration.

Fig.2 Logic diagram.

1999 Sep 23

Philips Semiconductors

Product speciﬁcation

Dual D-type ﬂip-ﬂop with set and reset;

positive-edge trigger

74AHC74; 74AHCT74

handbook, halfpage

1CP

handbook, halfpage

2CP

MNA419

MNA420

Fig.3 IEC logic symbol.

Fig.4 Functional diagram.

handbook, full pagewidth

MNA421

Fig.5 Logic diagram (one flip-flop).

1999 Sep 23

Philips Semiconductors

Product speciﬁcation

Dual D-type ﬂip-ﬂop with set and reset;

positive-edge trigger

74AHC74; 74AHCT74

RECOMMENDED OPERATING CONDITIONS

74AHC

74AHCT

UNIT

SYMBOL

PARAMETER

DC supply voltage

CONDITIONS

MIN. TYP. MAX. MIN. TYP. MAX.

V_CC

V_I

2.0

5.0

−

5.5

4.5

5.0

−

5.5

input voltage

5.5

V_O

output voltage

−

V_CC

+85

−

V_CC

+85

T_amb

operating ambient temperature

see DC and AC

characteristics per

device

−40

+25

−40

+25

°C

+125 −40

+125 °C

t_r,t_f(∆t/∆f) input rise and fall rates

V_CC= 3.3 V ±0.3 V

V_CC= 5 V ±0.5 V

−

100

−

ns/V

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).

SYMBOL

PARAMETER

DC supply voltage

CONDITIONS

MIN. MAX. UNIT

V_CC

V_I

−0.5 +7.0

input voltage

I_IK

DC input diode current

DC output diode current

V_I< −0.5 V; note 1

V_O< −0.5 V or V_O> V_CC+ 0.5 V; note 1

−

−20

±20

±25

±75

I_OK

I_O

−

DC output source or sink current −0.5 V < V_O< V_CC+ 0.5 V

DC V_CCor GND current

−

I_CC

T_stg

P_D

−

storage temperature

−65

−

+150 °C

500 mW

power dissipation per package

for temperature range: −40 to +85 °C; note 2

Notes

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. For SO packages: above 70 °C the value of P_Dderates linearly with 8 mW/K.

For TSSOP packages: above 60 °C the value of P_Dderates linearly with 5.5 mW/K.

1999 Sep 23

Philips Semiconductors

Product speciﬁcation

Dual D-type ﬂip-ﬂop with set and reset;

positive-edge trigger

74AHC74; 74AHCT74

DC CHARACTERISTICS

74AHC family

Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).

TEST CONDITIONS T_amb(°C)

−40 to +85 −40 to +125 UNIT

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

SYMBOL

PARAMETER

OTHER

V_CC(V)

V_IH

HIGH-level input

voltage

2.0

3.0

5.5

2.0

3.0

5.5

2.0

3.0

4.5

3.0

1.5

2.1

3.85

−

1.5

2.1

3.85

−

1.5

2.1

3.85

−

V_IL

LOW-level input

voltage

−

0.5

0.9

1.65

−

0.5

0.9

1.65

−

0.5

0.9

1.65

−

V_OH

HIGH-level output V_I= V_IHor V_IL;

voltage; all

outputs

1.9

2.9

4.4

2.58

2.0

3.0

4.5

−

1.9

2.9

4.4

2.48

1.9

2.9

4.4

2.40

I_O= −50 µA

−

HIGH-level output V_I= V_IHor V_IL;

−

voltage

I_O= −4.0 mA

V_I= V_IHor V_IL;

4.5

3.94

−

3.8

−

3.70

−

I_O= −8.0 mA

V_OL

LOW-level output V_I= V_IHor V_IL;

2.0

3.0

4.5

3.0

−

0.1

0.36

−

0.1

0.44

−

0.1

0.55

voltage; all

outputs

I_O= 50 µA

LOW-level output V_I= V_IHor V_IL;

voltage

I_O= 4 mA

V_I= V_IHor V_IL;

I_O= 8 mA

4.5

−

0.36

0.1

−

0.44

1.0

±2.5

−

0.55

2.0

I_I

input leakage

current

V_I= V_CCor GND 5.5

µA

I_OZ

I_CC

C_I

3-state output

OFF current

V_I= V_IHor V_IL;

V_O= V_CCor GND

5.5

±0.25 −

±10.0 µA

quiescent supply V_I= V_CCor GND; 5.5

2.0

−

µA

current

I_O= 0

input capacitance

−

1999 Sep 23

Philips Semiconductors

Product speciﬁcation

Dual D-type ﬂip-ﬂop with set and reset;

positive-edge trigger

74AHC74; 74AHCT74

74AHCT family

Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).

TEST CONDITIONS

T_amb(°C)

SYMBOL

PARAMETER

−40 to +85 −40 to +125 UNIT

OTHER V_CC(V)

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

V_IH

V_IL

HIGH-level input

voltage

4.5 to 5.5 2.0

−

2.0

−

2.0

−

LOW-level input

voltage

4.5 to 5.5 −

−

0.8

−

0.8

−

0.8

−

V_OH

HIGH-level output V_I= V_IHor V_IL;

4.5

4.4 4.5

4.4

voltage; all

outputs

I_O= −50 µA

HIGH-level output V_I= V_IHor V_IL;

voltage I_O= −8.0 mA

LOW-level output V_I= V_IHor V_IL;

4.5

3.94

−

3.8

−

3.70

−

V_OL

−

0.1

−

0.1

−

0.1

voltage; all

outputs

I_O= 50 µA

LOW-level output V_I= V_IHor V_IL;

4.5

5.5

−

0.36

0.1

−

0.44

1.0

−

0.55

2.0

voltage

I_O= 8 mA

I_I

input leakage

current

V_I= V_IHor V_IL

µA

I_OZ

3-state output

OFF current

V_I= V_IHor V_IL;

V_O= V_CCor GND

per input pin;

±0.25 −

±2.5

±10.0 µA

other inputs at

V_CCor GND;

I_O= 0

I_CC

quiescent supply

current

V_I= V_CCor GND; 5.5

I_O= 0

−

2.0

−

µA

∆I_CC

additional

V_I= V_CC− 2.1 V 4.5 to 5.5 −

1.35

1.5

quiescent supply

current per input

other inputs at

V_CCor GND;

I_O= 0

C_I

input capacitance

−

1999 Sep 23

Philips Semiconductors

Product speciﬁcation

Dual D-type ﬂip-ﬂop with set and reset;

positive-edge trigger

74AHC74; 74AHCT74

AC CHARACTERISTICS

Type 74AHC74

GND = 0 V; t_r= t_f≤ 3.0 ns.

TEST CONDITIONS

T_amb(°C)

SYMBOL

PARAMETER

−40 to +85 −40 to +125 UNIT

WAVEFORMS

C_L

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

V_CC= 3.0 to 3.6 V; note 1

t_PHL/t_PLHpropagation delay see Figs 6 and 8 15 pF

nCP to nQ, nQ

−

5.2

5.4

125

7.4

7.7

−

11.9 1.0

12.3 1.0

14.0 1.0

14.5 1.0

15.0 ns

15.5 ns

propagation delay see Figs 7 and 8

nS_DnR_Dto nQ, nQ

−

f_max

maximum clock

pulse frequency

−

_PHL/t_PLHpropagation delay see Figs 6 and 8 50 pF

15.4 1.0

15.8 1.0

17.5 1.0

18.0 1.0

19.5 ns

20.0 ns

nCP to nQ, nQ

propagation delay see Figs 7 and 8

nS_DnR_Dto nQ, nQ

−

t_W

clock pulse width

HIGH or LOW

see Figs 6 and 8

6.0

5.0

6.0

0.5

−

7.0

5.0

7.0

0.5

−

7.0

5.0

7.0

0.5

−

set or reset pulse

width LOW

see Figs 7 and 8

−

t_rem

t_su

removal time set or

reset

−

set-up time

nD to nCP

see Figs 6 and 8

−

t_h

hold time

−

nD to nCP

f_max

maximum clock

pulse frequency

1999 Sep 23

Philips Semiconductors

Product speciﬁcation

Dual D-type ﬂip-ﬂop with set and reset;

positive-edge trigger

74AHC74; 74AHCT74

TEST CONDITIONS

T_amb(°C)

SYMBOL

PARAMETER

−40 to +85 −40 to +125 UNIT

WAVEFORMS

C_L

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

V_CC= 4.5 to 5.5 V; note 2

t_PHL/t_PLHpropagation delay see Figs 6 and 8 15 pF

nCP to nQ, nQ

−

3.7

7.3

7.7

−

1.0

110

1.0

5.0

3.0

5.0

0.5

8.5

9.0

−

1.0

110

9.5

10.0 ns

propagation delay see Figs 7 and 8

nS_DnR_Dto nQ, nQ

f_max

maximum clock

pulse frequency

130 170

−

_PHL/t_PLHpropagation delay see Figs 6 and 8 50 pF

−

5.2

5.3

−

9.3

9.7

−

10.5 1.0

11.0 1.0

12.0 ns

12.5 ns

nCP to nQ, nQ

propagation delay see Figs 7 and 8

nS_Dto nQ, nQ

−

t_W

clock pulse width

HIGH or LOW

see Figs 6 and 8

5.0

3.0

5.0

0.5

−

5.0

3.0

5.0

0.5

−

set or reset pulse

width LOW

see Figs 7 and 8

−

t_rem

t_su

removal time set or

reset

−

set-up time

nD to nCP

see Figs 6 and 8

−

t_h

hold time

−

nD to nCP

f_max

maximum clock

pulse frequency

115

−

Notes

1. Typical values at V_CC= 3.3 V.

2. Typical values at V_CC= 5.0 V.

1999 Sep 23

Philips Semiconductors

Product speciﬁcation

Dual D-type ﬂip-ﬂop with set and reset;

positive-edge trigger

74AHC74; 74AHCT74

Type 74AHCT74

GND = 0 V; t_r= t_f≤ 3.0 ns.

TEST CONDITIONS

T_amb(°C)

SYMBOL

PARAMETER

−40 to +85 −40 to +125 UNIT

WAVEFORMS

C_L

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

V_CC= 4.5 to 5.5 V; note 1

t_PHL/t_PLHpropagation delay see Figs 6 and 8 15 pF

nCP to nQ, nQ

−

3.3

3.7

7.8

1.0

9.0

12.0 1.0

1.0

10.0 ns

13.0 ns

propagation delay see Figs 7 and 8

nS_DnR_Dto nQ, nQ

10.4 1.0

f_max

maximum clock

pulse frequency

100 160

−

_PHL/t_PLHpropagation delay see Figs 6 and 8 50 pF

−

4.8

5.3

−

8.8

1.0

10.0 1.0

13.0 1.0

11.0 ns

14.5 ns

nCP to nQ, nQ

propagation delay see Figs 7 and 8

nS_DnR_Dto nQ, nQ

−

11.4 1.0

t_W

clock pulse width

HIGH or LOW

see Figs 6 and 8

5.0

3.5

5.0

−

5.0

3.5

5.0

−

5.0

3.5

5.0

−

t_W(st)(rst)

t_rem

t_su

set or reset pulse

width LOW

see Figs 7 and 8

−

removal time set or

reset

−

set-up time

nD to nCP

see Figs 6 and 8

−

t_h

hold time

nD to nCP

−

f_max

maximum clock

pulse frequency

140

Note

1. Typical values at V_CC= 5.0 V.

1999 Sep 23

Philips Semiconductors

Product speciﬁcation

Dual D-type ﬂip-ﬂop with set and reset;

positive-edge trigger

74AHC74; 74AHCT74

AC WAVEFORMS

handbook, full pagewidth

(1)

nD INPUT

GND

1/f

max

(1)

nCP INPUT

GND

PHL

PLH

(1)

nQ OUTPUT

(1)

nQ OUTPUT

MNA422

PHL

PLH

(1)

V_IINPUT

REQUIREMENTS

V_M

INPUT

V_M

OUTPUT

FAMILY

AHC

GND to V_CC

50% V_CC50% V_CC

1.5 V 50% V_CC

AHCT

GND to 3.0 V

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig.6 The clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up, the

nCP to nD hold times, the output transition times and the maximum clock pulse frequency.

1999 Sep 23

Philips Semiconductors

Product speciﬁcation

Dual D-type ﬂip-ﬂop with set and reset;

positive-edge trigger

74AHC74; 74AHCT74

handbook, full pagewidth

(1)

nCP INPUT

GND

rem

(1)

nS INPUT

GND

(1)

nR INPUT

GND

PHL

PLH

(1)

nQ OUTPUT

(1)

nQ OUTPUT

MNA423

PHL

PLH

(1)

V_IINPUT

REQUIREMENTS

V_M

INPUT

V_M

OUTPUT

FAMILY

AHC

GND to V_CC

50% V_CC50% V_CC

1.5 V 50% V_CC

AHCT

GND to 3.0 V

Fig.7 The set (nS_D) and reset (nR_D) input to output (nQ, nQ) propagation delays, the set and reset pulse widths

and the nR_Dto nCP removal time.

1999 Sep 23

Philips Semiconductors

Product speciﬁcation

Dual D-type ﬂip-ﬂop with set and reset;

positive-edge trigger

74AHC74; 74AHCT74

handbook, full pagewidth

open

GND

1000 Ω

PULSE

D.U.T.

GENERATOR

MNA183

TEST

t_PLH/t_PHL

_PLZ/t_PZL

S₁

open

V_CC

t_PHZ/t_PZH

GND

Fig.8 Load circuitry for switching times.

1999 Sep 23

Philips Semiconductors

Product speciﬁcation

Dual D-type ﬂip-ﬂop with set and reset;

positive-edge trigger

74AHC74; 74AHCT74

PACKAGE OUTLINES

SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

(A )

pin 1 index

detail X

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

UNIT

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

8.75

8.55

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

1.75

1.27

0.050

1.05

0.25

0.01

0.25

0.1

0.25

0.01

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.35

0.014 0.0075 0.34

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.024

0.028

0.012

inches

0.041

0.01 0.004

0.069

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

95-01-23

97-05-22

SOT108-1

076E06S

MS-012AB

1999 Sep 23

Philips Semiconductors

Product speciﬁcation

Dual D-type ﬂip-ﬂop with set and reset;

positive-edge trigger

74AHC74; 74AHCT74

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

(A )

pin 1 index

detail X

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

(2)

(1)

UNIT

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.72

0.38

1.10

0.65

0.25

1.0

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

94-07-12

95-04-04

SOT402-1

MO-153

1999 Sep 23

Philips Semiconductors

Product speciﬁcation

Dual D-type ﬂip-ﬂop with set and reset;

positive-edge trigger

74AHC74; 74AHCT74

SOLDERING

If wave soldering is used the following conditions must be

observed for optimal results:

Introduction to soldering surface mount packages

• Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our “Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable

for surface mount ICs, or for printed-circuit boards with

high population densities. In these situations reflow

soldering is often used.

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

Reﬂow soldering

The footprint must incorporate solder thieves at the

downstream end.

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

• For packages with leads on four sides, the footprint must

be placed at a 45° angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

Several methods exist for reflowing; for example,

infrared/convection heating in a conveyor type oven.

Throughput times (preheating, soldering and cooling) vary

between 100 and 200 seconds depending on heating

method.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Typical reflow peak temperatures range from

215 to 250 °C. The top-surface temperature of the

packages should preferable be kept below 230 °C.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Wave soldering

Manual soldering

Conventional single wave soldering is not recommended

for surface mount devices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

To overcome these problems the double-wave soldering

method was specifically developed.

When using a dedicated tool, all other leads can be

soldered in one operation within 2 to 5 seconds between

270 and 320 °C.

1999 Sep 23

Philips Semiconductors

Product speciﬁcation

Dual D-type ﬂip-ﬂop with set and reset;

positive-edge trigger

74AHC74; 74AHCT74

Suitability of surface mount IC packages for wave and reﬂow soldering methods

SOLDERING METHOD

PACKAGE

WAVE

REFLOW⁽¹⁾

BGA, SQFP

not suitable

suitable

HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable⁽²⁾

PLCC⁽³⁾, SO, SOJ

LQFP, QFP, TQFP

SSOP, TSSOP, VSO

suitable

not recommended⁽³⁾⁽⁴⁾

not recommended⁽⁵⁾

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

Data sheet status

Objective speciﬁcation

Preliminary speciﬁcation

Product speciﬁcation

This data sheet contains target or goal speciﬁcations for product development.

This data sheet contains preliminary data; supplementary data may be published later.

This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

1999 Sep 23

Philips Semiconductors

Product speciﬁcation

Dual D-type ﬂip-ﬂop with set and reset;

positive-edge trigger

74AHC74; 74AHCT74

NOTES

1999 Sep 23

Philips Semiconductors

Product speciﬁcation

Dual D-type ﬂip-ﬂop with set and reset;

positive-edge trigger

74AHC74; 74AHCT74

NOTES

1999 Sep 23

Philips Semiconductors – a worldwide company

Argentina: see South America

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. +31 40 27 82785, Fax. +31 40 27 88399

Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,

Tel. +61 2 9704 8141, Fax. +61 2 9704 8139

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. +64 9 849 4160, Fax. +64 9 849 7811

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210

Norway: Box 1, Manglerud 0612, OSLO,

Tel. +47 22 74 8000, Fax. +47 22 74 8341

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773

Pakistan: see Singapore

Belgium: see The Netherlands

Brazil: see South America

Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,

Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,

Tel. +359 2 68 9211, Fax. +359 2 68 9102

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,

Tel. +48 22 5710 000, Fax. +48 22 5710 001

Portugal: see Spain

Romania: see Italy

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,

Tel. +1 800 234 7381, Fax. +1 800 943 0087

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

72 Tat Chee Avenue, Kowloon Tong, HONG KONG,

Tel. +852 2319 7888, Fax. +852 2319 7700

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Colombia: see South America

Czech Republic: see Austria

Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

Tel. +45 33 29 3333, Fax. +45 33 29 3905

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,

Tel. +27 11 471 5401, Fax. +27 11 471 5398

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. +358 9 615 800, Fax. +358 9 6158 0920

France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. +33 1 4099 6161, Fax. +33 1 4099 6427

South America: Al. Vicente Pinzon, 173, 6th floor,

04547-130 SÃO PAULO, SP, Brazil,

Tel. +55 11 821 2333, Fax. +55 11 821 2382

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. +49 40 2353 60, Fax. +49 40 2353 6300

Spain: Balmes 22, 08007 BARCELONA,

Tel. +34 93 301 6312, Fax. +34 93 301 4107

Hungary: see Austria

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,

Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,

Tel. +91 22 493 8541, Fax. +91 22 493 0966

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. +41 1 488 2741 Fax. +41 1 488 3263

Indonesia: PT Philips Development Corporation, Semiconductors Division,

Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,

Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,

TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. +353 1 7640 000, Fax. +353 1 7640 200

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,

Tel. +66 2 745 4090, Fax. +66 2 398 0793

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,

ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813

Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),

Tel. +39 039 203 6838, Fax +39 039 203 6800

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,

252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,

TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,

MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. +82 2 709 1412, Fax. +82 2 709 1415

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,

Tel. +1 800 234 7381, Fax. +1 800 943 0087

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. +60 3 750 5214, Fax. +60 3 757 4880

Uruguay: see South America

Vietnam: see Singapore

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Middle East: see Italy

Tel. +381 11 62 5344, Fax.+381 11 63 5777

For all other countries apply to: Philips Semiconductors,

Internet: http://www.semiconductors.philips.com

International Marketing & Sales Communications, Building BE-p, P.O. Box 218,

5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

545002/02/pp20

Date of release: 1999 Sep 23

Document order number: 9397 750 06291

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74AHCT74D产品参数

型号:	74AHCT74D
是否Rohs认证：	符合
生命周期：	Active
包装说明：	SOP,
Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01
风险等级：	5.07
系列：	AHCT/VHCT/VT
JESD-30 代码：	R-PDSO-G14
JESD-609代码：	e4
长度：	8.65 mm
逻辑集成电路类型：	D FLIP-FLOP
湿度敏感等级：	1
位数：	1
功能数量：	2
端子数量：	14
最高工作温度：	125 °C
最低工作温度：	-40 °C
输出特性：	3-STATE
输出极性：	COMPLEMENTARY
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
传播延迟（tpd）：	11 ns
认证状态：	Not Qualified
座面最大高度：	1.75 mm
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	AUTOMOTIVE
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
触发器类型：	POSITIVE EDGE
宽度：	3.9 mm
最小 fmax：	80 MHz
Base Number Matches：	1

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