74HC373现货热卖使用介绍供应商报价哪里找芯片批发报价-中国IC网-芯三七

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产品型号74HC373的概述

芯片74HC373的概述 74HC373是74系列逻辑芯片中的一个重要成员，属于高性能CMOS逻辑系列。该芯片主要用于数据存储，其功能是可以将8位输入数据在特定时刻通过控制信号锁存，从而保持数据的稳定性。74HC373被广泛应用于计算机和数字系统中，尤其是在需要双向数据传输和控制信号的场合。 74HC373的“HC”表明它采用了高速度的CMOS技术，具有较低的功耗和高抗干扰能力，适用于各种数字电路。该芯片的操作电压范围在2V到6V之间，适配了多种电源配置。在时序电路中，74HC373常常与其他逻辑电路配合使用，以实现数据的选择、存储和传输。芯片74HC373的详细参数 74HC373的主要参数特征如下： - 功能类型：8位数据锁存器 - 输入电压范围：2V到6V - 输出电压范围：2V到6V - 工作温度范围：-40℃至85℃ - 典型功耗：最大为500μA - 输入高电平最低值：3...

产品型号74HC373的Datasheet PDF文件预览

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT373

Octal D-type transparent latch;

3-state

September 1993

Product speciﬁcation

File under Integrated Circuits, IC06

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state

74HC/HCT373

input and an output enable (OE) input are common to all

latches.

FEATURES

• 3-state non-inverting outputs for bus oriented

The “373” consists of eight D-type transparent latches with

3-state true outputs. When LE is HIGH, data at the D_n

inputs enters the latches. In this condition the latches are

transparent, i.e. a latch output will change state each time

its corresponding D-input changes.

applications

• Common 3-state output enable input

• Functionally identical to the “563”, “573” and “533”

• Output capability: bus driver

• I_CCcategory: MSI

When LE is LOW the latches store the information that was

present at the D-inputs a set-up time preceding the

HIGH-to-LOW transition of LE. When OE is LOW, the

contents of the 8 latches are available at the outputs.

When OE is HIGH, the outputs go to the high impedance

OFF-state. Operation of the OE input does not affect the

state of the latches.

GENERAL DESCRIPTION

The 74HC/HCT373 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The “373” is functionally identical to the “533”, “563” and

“573”, but the “563” and “533” have inverted outputs and

the “563” and “573” have a different pin arrangement.

The 74HC/HCT373 are octal D-type transparent latches

featuring separate D-type inputs for each latch and 3-state

outputs for bus oriented applications. A latch enable (LE)

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C; t_r= t_f= 6 ns

TYPICAL

SYMBOL

_PHL/ t_PLH

PARAMETER

propagation delay

CONDITIONS

UNIT

HCT

C_L= 15 pF; V_CC= 5 V

D_nto Q_n

3.5

LE to Q_n

3.5

C_I

input capacitance

power dissipation capacitance per latch

C_PD

notes 1 and 2

Notes

1. C_PDis used to determine the dynamic power dissipation (P_Din µW):

P_D= C_PD× V_CC²× f_i+ ∑ (C_L× V_CC× f_o) where:

f_i= input frequency in MHz

f_o= output frequency in MHz

∑ (C_L× V_CC× f_o) = sum of outputs

C_L= output load capacitance in pF

V_CC= supply voltage in V

2. For HC the condition is V_I= GND to V_CC. For HCT the condition is V_I= GND to V_CC− 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

September 1993

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state

74HC/HCT373

PIN DESCRIPTION

PIN NO.

SYMBOL

NAME AND FUNCTION

3-state output enable input (active LOW)

3-state latch outputs

2, 5, 6, 9, 12, 15, 16, 19

Q₀to Q₇

D₀to D₇

GND

3, 4, 7, 8, 13, 14, 17, 18

data inputs

ground (0 V)

latch enable input (active HIGH)

positive supply voltage

V_CC

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

September 1993

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state

74HC/HCT373

FUNCTION TABLE

INPUTS

OE LE D_n

OUTPUTS

INTERNAL

OPERATING

MODES

LATCHES

Q₀to Q₇

enable and

read

(transparent

mode)

latch and

read register

latch register

and disable

outputs

Notes

Fig.4 Functional diagram.

1. H = HIGH voltage level

h = HIGH voltage level one set-up time prior to the

HIGH-to-LOW LE transition

L = LOW voltage level

I = LOW voltage level one set-up time prior to the

HIGH-to-LOW LE transition

X = don’t care

Z = high impedance OFF-state

Fig.5 Logic diagram (one latch).

Fig.6 Logic diagram.

September 1993

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state

74HC/HCT373

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: bus driver

I_CCcategory: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HC

SYMBOL

PARAMETER

UNIT

WAVEFORMS

V_CC

(V)

+25

−40 to +85 −40 to +125

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

D_nto Q_n

150

190

225

2.0 Fig.7

4.5

6.0

_PHL/ t_PLHpropagation delay

LE to Q_n

175

220

265

2.0 Fig.8

4.5

6.0

_PZH/ t_PZL3-state output enable time

OE to Q_n

150

190

225

2.0 Fig.9

4.5

6.0

_PHZ/ t_PLZ3-state output disable time

OE to Q_n

150

190

225

2.0 Fig.9

4.5

6.0

_THL/ t_TLHoutput transition time

2.0 Fig.7

4.5

6.0

t_W

t_su

t_h

LE pulse width

HIGH

100

120

2.0 Fig.8

4.5

6.0

set-up time

D_nto LE

2.0 Fig.10

4.5

6.0

hold time

D_nto LE

−8

−3

−2

2.0 Fig.10

4.5

6.0

September 1993

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state

74HC/HCT373

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: bus driver

I_CCcategory: MSI

Note to HCT types

The value of additional quiescent supply current (∆I_CC) for a unit load of 1 is given in the family specifications.

To determine ∆I_CCper input, multiply this value by the unit load coefficient shown in the table below.

INPUT

UNIT LOAD COEFFICIENT

D_n

0.30

1.50

1.00

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HCT

SYMBOL

PARAMETER

UNIT

WAVEFORMS

V_CC

(V)

+25

−40 to +85 −40 to +125

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

D_nto Q_n

4.5 Fig.7

4.5 Fig.8

4.5 Fig.9

4.5 Fig.7

4.5 Fig.8

4.5 Fig.10

t_PHL/ t_PLHpropagation delay

LE to Q_n

_PZH/ t_PZL3-state output enable time

OE to Q_n

t_PHZ/ t_PLZ3-state output disable time

OE to Q_n

t_THL/ t_TLHoutput transition time

t_W

t_su

t_h

LE pulse width

HIGH

set-up time

D_nto LE

hold time

D_nto LE

−1

September 1993

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state

74HC/HCT373

AC WAVEFORMS

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT : V_M= 1.3 V; V_I= GND to 3 V.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT : V_M= 1.3 V; V_I= GND to 3 V.

Fig.8 Waveforms showing the latch enable input

(LE) pulse width, the latch enable input to

output (Q_n) propagation delays and the

output transition times.

Fig.7 Waveforms showing the input (D_n) to output

(Q_n) propagation delays and the output

transition times.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT : V_M= 1.3 V; V_I= GND to 3 V.

Fig.9 Waveforms showing the 3-state enable and disable times.

The shaded areas indicate when the input is permitted to

change for predictable output performance.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT : V_M= 1.3 V; V_I= GND to 3 V.

Fig.10 Waveforms showing the data set-up and hold times for D_ninput to LE input.

September 1993

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state

74HC/HCT373

PACKAGE OUTLINES

See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

September 1993

74HC373相关文章

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74HC373BQ产品参数

型号:	74HC373BQ
是否Rohs认证：	符合
生命周期：	Transferred
IHS 制造商：	PHILIPS SEMICONDUCTORS
包装说明：	QCCN, LCC20,.1X.18,20
Reach Compliance Code：	unknown
风险等级：	5.72
JESD-30 代码：	R-PQCC-N20
负载电容（CL）：	50 pF
逻辑集成电路类型：	D LATCH
最大I（ol）：	0.006 A
位数：	8
功能数量：	1
端子数量：	20
最高工作温度：	125 °C
最低工作温度：	-40 °C
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCN
封装等效代码：	LCC20,.1X.18,20
封装形状：	RECTANGULAR
封装形式：	CHIP CARRIER
包装方法：	TAPE AND REEL
电源：	2/6 V
Prop。Delay @ Nom-Sup：	45 ns
认证状态：	Not Qualified
子类别：	FF/Latches
表面贴装：	YES
技术：	CMOS
温度等级：	AUTOMOTIVE
端子形式：	NO LEAD
端子节距：	0.5 mm
端子位置：	QUAD
Base Number Matches：	1

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