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  • 74HCF4054图
  • 深圳市一线半导体有限公司

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  • 74HCF4054
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产品型号74HCHCT21的Datasheet PDF文件预览

INTEGRATED CIRCUITS  
DATA SHEET  
For a complete data sheet, please also download:  
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications  
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information  
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines  
74HC/HCT21  
Dual 4-input AND gate  
December 1990  
Product specification  
File under Integrated Circuits, IC06  
Philips Semiconductors  
Product specification  
Dual 4-input AND gate  
74HC/HCT21  
FEATURES  
GENERAL DESCRIPTION  
Output capability: standard  
ICC category: SSI  
The 74HC/HCT21 are high-speed Si-gate CMOS devices  
and are pin compatible with low power Schottky TTL  
(LSTTL). They are specified in compliance with JEDEC  
standard no. 7A.  
The 74HC/HCT21 provide the 4-input AND function.  
QUICK REFERENCE DATA  
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns  
TYPICAL  
SYMBOL PARAMETER  
CONDITIONS  
UNIT  
ns  
HC  
HCT  
12  
tPHL/ tPLH  
CI  
propagation delay nA, nB, nC, nD to nY  
CL = 15 pF; VCC = 5 V 10  
3.5  
input capacitance  
3.5  
16  
pF  
pF  
CPD  
power dissipation capacitance per package  
notes 1 and 2  
15  
Notes  
1. CPD is used to determine the dynamic power dissipation (PD in µW):  
PD = CPD × VCC2 × fi + (CL × VCC2 × fO) where:  
fi = input frequency in MHz  
fo = output frequency in MHz  
CL = output load capacitance in pF  
VCC = supply voltage in V  
(CL × VCC2 × fo) = sum of outputs  
2. For HC the condition is VI = GND to VCC  
For HCT the condition is VI = GND to VCC 1.5 V  
ORDERING INFORMATION  
See “74HC/HCT/HCU/HCMOS Logic Package Information”.  
December 1990  
2
Philips Semiconductors  
Product specification  
Dual 4-input AND gate  
74HC/HCT21  
PIN DESCRIPTION  
PIN NO.  
1, 9  
SYMBOL  
1A, 2A  
1B, 2B  
n.c.  
NAME AND FUNCTION  
data inputs  
2, 10  
3, 11  
4, 12  
5, 13  
6, 8  
data inputs  
not connected  
data inputs  
1C, 2C  
1D, 2D  
1Y, 2Y  
GND  
data inputs  
data outputs  
7
ground (0 V)  
14  
VCC  
positive supply voltage  
Fig.1 Pin configuration.  
Fig.2 Logic symbol.  
Fig.3 IEC logic symbol.  
December 1990  
3
Philips Semiconductors  
Product specification  
Dual 4-input AND gate  
74HC/HCT21  
Fig.4 Functional diagram.  
Fig.5 Logic diagram (one gate).  
FUNCTION TABLE  
INPUTS  
OUTPUT  
nY  
nA  
nB  
nC  
nD  
L
X
X
X
H
X
L
X
X
L
X
X
X
L
L
L
L
L
H
X
X
H
X
H
H
Notes  
1. H = HIGH voltage level  
L = LOW voltage level  
X = don’t care  
December 1990  
4
Philips Semiconductors  
Product specification  
Dual 4-input AND gate  
74HC/HCT21  
DC CHARACTERISTICS FOR 74HC  
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.  
Output capability: standard  
ICC category: SSI  
AC CHARACTERISTICS FOR 74HC  
GND = 0 V; tr = tf = 6 ns; CL = 50 pF  
Tamb (°C)  
TEST CONDITIONS  
74HC  
SYMBOL PARAMETER  
UNIT  
WAVEFORMS  
VCC  
(V)  
+25  
40 to+85  
40 to+125  
min. typ. max. min. max. min. max.  
tPHL/ tPLH propagation delay  
nA, nB, nC, nD to nY  
33  
12  
10  
19  
7
110  
22  
19  
75  
15  
13  
140  
28  
24  
95  
19  
16  
165  
33  
ns  
2.0  
4.5  
6.0  
2.0  
4.5  
6.0  
Fig.6  
Fig.6  
28  
t
THL/ tTLH output transition time  
110  
22  
ns  
6
19  
December 1990  
5
Philips Semiconductors  
Product specification  
Dual 4-input AND gate  
74HC/HCT21  
DC CHARACTERISTICS FOR 74HCT  
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.  
Output capability: standard  
ICC category: SSI  
Note to HCT types  
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications.  
To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.  
INPUT  
UNIT LOAD COEFFICIENT  
nA, nB,  
nC, nD  
1.50  
1.50  
AC CHARACTERISTICS FOR 74HCT  
GND = 0 V; tr = tf = 6 ns; CL = 50 pF  
Tamb (°C)  
TEST CONDITIONS  
74HCT  
SYMBOL PARAMETER  
UNIT  
WAVEFORMS  
VCC  
(V)  
+25  
40 to+85  
40 to+125  
min. typ. max. min. max. min. max.  
tPHL/ tPLH propagation delay  
nA, nB nC, nD to nY  
15  
7
27  
15  
34  
19  
41  
22  
ns  
ns  
4.5  
4.5  
Fig.6  
Fig.6  
t
THL/ tTLH output transition time  
AC WAVEFORMS  
(1) HC: VM = 50%; VI = GND to VCC  
.
HCT: VM = 1.3 V; VI = GND to 3 V.  
Fig.6 Waveforms showing the input (nA, nB, nC, nD) to output (nY) propagation delays and the output transition  
times.  
PACKAGE OUTLINES  
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.  
December 1990  
6
配单直通车
74HCT00BQ产品参数
型号:74HCT00BQ
是否Rohs认证: 符合
生命周期:Active
包装说明:VQCCN,
Reach Compliance Code:compliant
HTS代码:8542.39.00.01
风险等级:5.57
系列:HCT
JESD-30 代码:R-PQCC-N14
JESD-609代码:e4
长度:3 mm
逻辑集成电路类型:NAND GATE
湿度敏感等级:1
功能数量:4
输入次数:2
端子数量:14
最高工作温度:125 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:VQCCN
封装形状:RECTANGULAR
封装形式:CHIP CARRIER, VERY THIN PROFILE
峰值回流温度(摄氏度):260
传播延迟(tpd):29 ns
座面最大高度:1 mm
最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V
表面贴装:YES
技术:CMOS
温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD
端子节距:0.5 mm
端子位置:QUAD
处于峰值回流温度下的最长时间:30
宽度:2.5 mm
Base Number Matches:1
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