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产品型号74HCT373D的概述

芯片74HCT373D的概述 74HCT373D是一款高性能的八位锁存器，属于74系列集成电路（IC）。该芯片引入了先进的CMOS技术，适用于各种数字电路中的数据存储和控制功能。74HCT373D能够在几乎所有逻辑电平下工作，并且具备较高的噪声容忍度和较低的功耗特性。它的应用尤为广泛，通常用于微处理器和微控制器系统中，以提供数据缓冲和锁存功能。该芯片具有八个输入数据端口（D0-D7）和八个相应的输出端口（Q0-Q7），并支持外部时钟信号的同步控制。当时钟信号处于高电平时，输入数据将被锁存，并在时钟信号返回低电平后保持输出稳定。芯片74HCT373D的详细参数 - 工作电压范围: 2V 至 6V - 输入高电平阈值 (VIH): 2V (以5V为例) - 输入低电平阈值 (VIL): 0.8V - 输出高电平 (VOH): 4.5V (以5V为例) - 输出低电平 (VOL): 0....

产品型号74HCT373D的Datasheet PDF文件预览

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT373

Octal D-type transparent latch;

3-state

September 1993

Product speciﬁcation

File under Integrated Circuits, IC06

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state

74HC/HCT373

input and an output enable (OE) input are common to all

latches.

FEATURES

• 3-state non-inverting outputs for bus oriented

The “373” consists of eight D-type transparent latches with

3-state true outputs. When LE is HIGH, data at the D_n

inputs enters the latches. In this condition the latches are

transparent, i.e. a latch output will change state each time

its corresponding D-input changes.

applications

• Common 3-state output enable input

• Functionally identical to the “563”, “573” and “533”

• Output capability: bus driver

• I_CCcategory: MSI

When LE is LOW the latches store the information that was

present at the D-inputs a set-up time preceding the

HIGH-to-LOW transition of LE. When OE is LOW, the

contents of the 8 latches are available at the outputs.

When OE is HIGH, the outputs go to the high impedance

OFF-state. Operation of the OE input does not affect the

state of the latches.

GENERAL DESCRIPTION

The 74HC/HCT373 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The “373” is functionally identical to the “533”, “563” and

“573”, but the “563” and “533” have inverted outputs and

the “563” and “573” have a different pin arrangement.

The 74HC/HCT373 are octal D-type transparent latches

featuring separate D-type inputs for each latch and 3-state

outputs for bus oriented applications. A latch enable (LE)

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C; t_r= t_f= 6 ns

TYPICAL

SYMBOL

_PHL/ t_PLH

PARAMETER

propagation delay

CONDITIONS

UNIT

HCT

C_L= 15 pF; V_CC= 5 V

D_nto Q_n

3.5

LE to Q_n

3.5

C_I

input capacitance

power dissipation capacitance per latch

C_PD

notes 1 and 2

Notes

1. C_PDis used to determine the dynamic power dissipation (P_Din µW):

P_D= C_PD× V_CC²× f_i+ ∑ (C_L× V_CC× f_o) where:

f_i= input frequency in MHz

f_o= output frequency in MHz

∑ (C_L× V_CC× f_o) = sum of outputs

C_L= output load capacitance in pF

V_CC= supply voltage in V

2. For HC the condition is V_I= GND to V_CC. For HCT the condition is V_I= GND to V_CC− 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

September 1993

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state

74HC/HCT373

PIN DESCRIPTION

PIN NO.

SYMBOL

NAME AND FUNCTION

3-state output enable input (active LOW)

3-state latch outputs

2, 5, 6, 9, 12, 15, 16, 19

Q₀to Q₇

D₀to D₇

GND

3, 4, 7, 8, 13, 14, 17, 18

data inputs

ground (0 V)

latch enable input (active HIGH)

positive supply voltage

V_CC

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

September 1993

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state

74HC/HCT373

FUNCTION TABLE

INPUTS

OE LE D_n

OUTPUTS

INTERNAL

OPERATING

MODES

LATCHES

Q₀to Q₇

enable and

read

(transparent

mode)

latch and

read register

latch register

and disable

outputs

Notes

Fig.4 Functional diagram.

1. H = HIGH voltage level

h = HIGH voltage level one set-up time prior to the

HIGH-to-LOW LE transition

L = LOW voltage level

I = LOW voltage level one set-up time prior to the

HIGH-to-LOW LE transition

X = don’t care

Z = high impedance OFF-state

Fig.5 Logic diagram (one latch).

Fig.6 Logic diagram.

September 1993

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state

74HC/HCT373

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: bus driver

I_CCcategory: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HC

SYMBOL

PARAMETER

UNIT

WAVEFORMS

V_CC

(V)

+25

−40 to +85 −40 to +125

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

D_nto Q_n

150

190

225

2.0 Fig.7

4.5

6.0

_PHL/ t_PLHpropagation delay

LE to Q_n

175

220

265

2.0 Fig.8

4.5

6.0

_PZH/ t_PZL3-state output enable time

OE to Q_n

150

190

225

2.0 Fig.9

4.5

6.0

_PHZ/ t_PLZ3-state output disable time

OE to Q_n

150

190

225

2.0 Fig.9

4.5

6.0

_THL/ t_TLHoutput transition time

2.0 Fig.7

4.5

6.0

t_W

t_su

t_h

LE pulse width

HIGH

100

120

2.0 Fig.8

4.5

6.0

set-up time

D_nto LE

2.0 Fig.10

4.5

6.0

hold time

D_nto LE

−8

−3

−2

2.0 Fig.10

4.5

6.0

September 1993

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state

74HC/HCT373

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: bus driver

I_CCcategory: MSI

Note to HCT types

The value of additional quiescent supply current (∆I_CC) for a unit load of 1 is given in the family specifications.

To determine ∆I_CCper input, multiply this value by the unit load coefficient shown in the table below.

INPUT

UNIT LOAD COEFFICIENT

D_n

0.30

1.50

1.00

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HCT

SYMBOL

PARAMETER

UNIT

WAVEFORMS

V_CC

(V)

+25

−40 to +85 −40 to +125

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

D_nto Q_n

4.5 Fig.7

4.5 Fig.8

4.5 Fig.9

4.5 Fig.7

4.5 Fig.8

4.5 Fig.10

t_PHL/ t_PLHpropagation delay

LE to Q_n

_PZH/ t_PZL3-state output enable time

OE to Q_n

t_PHZ/ t_PLZ3-state output disable time

OE to Q_n

t_THL/ t_TLHoutput transition time

t_W

t_su

t_h

LE pulse width

HIGH

set-up time

D_nto LE

hold time

D_nto LE

−1

September 1993

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state

74HC/HCT373

AC WAVEFORMS

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT : V_M= 1.3 V; V_I= GND to 3 V.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT : V_M= 1.3 V; V_I= GND to 3 V.

Fig.8 Waveforms showing the latch enable input

(LE) pulse width, the latch enable input to

output (Q_n) propagation delays and the

output transition times.

Fig.7 Waveforms showing the input (D_n) to output

(Q_n) propagation delays and the output

transition times.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT : V_M= 1.3 V; V_I= GND to 3 V.

Fig.9 Waveforms showing the 3-state enable and disable times.

The shaded areas indicate when the input is permitted to

change for predictable output performance.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT : V_M= 1.3 V; V_I= GND to 3 V.

Fig.10 Waveforms showing the data set-up and hold times for D_ninput to LE input.

September 1993

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state

74HC/HCT373

PACKAGE OUTLINES

See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

September 1993

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