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产品型号74HCT393D的概述

芯片74HCT393D的概述 74HCT393D是一款高性能的双4位二进制计数器，属于74HCT系列，这个系列的芯片在许多数字电路中被广泛应用。74HCT393D的设计旨在提供快速、可靠的计数功能，一般用于频率分频、时间计数、事件计数等多种场合。该芯片不仅具备实用性，还因其灵活性而被广泛应用于数字逻辑设计中。 74HCT393D采用CMOS技术，可以在低电压下工作，提供了较高的性能。同时，由于其内部使用了高输入阻抗晶体管，具备较小的功耗特性，长时间运行时不会造成发热。其工作电压范围为2V到6V，适用于各种电子系统，尤其是在大多数TTL逻辑电路中兼容性良好。芯片74HCT393D的详细参数 1. 逻辑电平：74HCT393D的逻辑高电平通常在4.5V以上，而逻辑低电平则为0.8V以下，确保了数字电路的稳定。 2. 工作电压：该芯片工作电压范围在2V到6V，支持不同的应用环境。 ...

产品型号74HCT393D的Datasheet PDF文件预览

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT393

Dual 4-bit binary ripple counter

December 1990

Product speciﬁcation

File under Integrated Circuits, IC06

Philips Semiconductors

Product speciﬁcation

Dual 4-bit binary ripple counter

74HC/HCT393

The 74HC/HCT393 are 4-bit binary ripple counters with

separate clocks (1CP and 2 CP) and master reset (1MR

and 2MR) inputs to each counter. The operation of each

half of the “393” is the same as the “93” except no external

clock connections are required.

FEATURES

• Two 4-bit binary counters with individual clocks

• Divide-by any binary module up to 28 in one package

• Two master resets to clear each 4-bit counter

The counters are triggered by a HIGH-to-LOW transition of

the clock inputs. The counter outputs are internally

connected to provide clock inputs to succeeding stages.

The outputs of the ripple counter do not change

synchronously and should not be used for high-speed

address decoding.

individually

• Output capability: standard

• I_CCcategory: MSI

GENERAL DESCRIPTION

The master resets are active-HIGH asynchronous inputs

to each 4-bit counter identified by the “1” and “2” in the pin

description.

A HIGH level on the nMR input overrides the clock and

sets the outputs LOW.

The 74HC/HCT393 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C; t_r= t_f= 6 ns

TYPICAL

SYMBOL

PARAMETER

propagation delay

CONDITIONS

UNIT

HCT

t_PHL/ t_PLH

C_L= 15 pF; V_CC= 5 V

nCP to nQ₀

nQ to nQ_n+1

nMR to nQ_n

3.5

f_max

C_I

maximum clock frequency

input capacitance

MHz

C_PD

power dissipation capacitance per counter

notes 1 and 2

Notes

1. C_PDis used to determine the dynamic power dissipation (P_Din µW):

P_D= C_PD× V_CC²× f_i+ ∑ (C_L× V_CC²× f_o) where:

f_i= input frequency in MHz

f_o= output frequency in MHz

∑ (C_L× V_CC²× f_o) = sum of outputs

C_L= output load capacitance in pF

V_CC= supply voltage in V

2. For HC the condition is V_I= GND to V_CC

For HCT the condition is V_I= GND to V_CC− 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

Philips Semiconductors

Product speciﬁcation

Dual 4-bit binary ripple counter

74HC/HCT393

PIN DESCRIPTION

PIN NO.

SYMBOL

1CP, 2CP

1MR, 2MR

1Q₀to 1Q₃, 2Q₀to 2Q₃

GND

NAME AND FUNCTION

1, 13

clock inputs (HIGH-to-LOW, edge-triggered)

asynchronous master reset inputs (active HIGH)

ﬂip-ﬂop outputs

2, 12

3, 4, 5, 6, 11, 10, 9, 8

ground (0 V)

V_CC

positive supply voltage

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

December 1990

Philips Semiconductors

Product speciﬁcation

Dual 4-bit binary ripple counter

74HC/HCT393

Fig.4 Functional diagram.

Fig.5 State diagram.

COUNT SEQUENCE FOR 1 COUNTER

OUTPUTS

COUNT

Q₀

Q₁

Q₂

Q₃

Notes

Fig.6 Logic diagram (one counter).

1. H = HIGH voltage level

L = LOW voltage level

December 1990

Philips Semiconductors

Product speciﬁcation

Dual 4-bit binary ripple counter

74HC/HCT393

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standard

I_CCcategory: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HC

SYMBOL PARAMETER

UNIT

WAVEFORMS

V_CC

(V)

+25

−40 to +85 −40 to +125

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

nCP to nQ₀

125

155

190

2.0 Fig.7

4.5

6.0

_PHL/ t_PLHpropagation delay

nQ_nto nQ_n+1

2.0 Fig.7

4.5

6.0

t_PHL

propagation delay

nMR to nQ_n

140

175

210

2.0 Fig.8

4.5

6.0

_THL/ t_TLHoutput transition time

110

2.0 Fig.7

4.5

6.0

t_W

clock pulse width

HIGH or LOW

100

120

2.0 Fig.7

4.5

6.0

t_W

master reset pulse

width; HIGH

100

120

2.0 Fig.8

4.5

6.0

t_rem

removal time

nMR to nCP

2.0 Fig.8

4.5

6.0

f_max

maximum clock pulse

frequency

107

MHz 2.0 Fig.7

4.5

6.0

December 1990

Philips Semiconductors

Product speciﬁcation

Dual 4-bit binary ripple counter

74HC/HCT393

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standard

I_CCcategory: MSI

Note to HCT types

The value of additional quiescent supply current (∆I_CC) for a unit load of 1 is given in the family specifications.

To determine ∆I_CCper input, multiply this value by the unit load coefficient shown in the table below.

INPUT

UNIT LOAD COEFFICIENT

1CP

2CP

1MR

2MR

0.4

1.0

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HCT

SYMBOL PARAMETER

UNIT

WAVEFORMS

V_CC

(V)

+25

−40 to +85 −40 to +125

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

nCP to nQ₀

4.5 Fig.7

4.5 Fig.8

4.5 Fig.7

4.5 Fig.8

_PHL/ t_PLHpropagation delay

nQ_nto nQ_n+1

t_PHL

propagation delay

nMR to nQ_n

_THL/ t_TLHoutput transition time

t_W

clock pulse width

HIGH or LOW

t_W

master reset pulse

width; HIGH

t_rem

f_max

removal time

nMR to nCP

maximum clock pulse

frequency

MHz 4.5 Fig.7

December 1990

Philips Semiconductors

Product speciﬁcation

Dual 4-bit binary ripple counter

74HC/HCT393

AC WAVEFORMS

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.7 Waveforms showing the clock (nCP) to output (1Q_n, 2Q_n) propagation delays, the clock pulse width, the

output transition times and the maximum clock frequency.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.8 Waveforms showing the master reset (nMR) pulse width, the master reset to output (Q_n) propagation

delays and the master reset to clock (nCP) removal time.

PACKAGE OUTLINES

See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

December 1990

74HCT393D相关文章

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74HCT393D产品参数

型号:	74HCT393D
是否Rohs认证：	不符合
生命周期：	Active
包装说明：	DIP, DIP14,.3
Reach Compliance Code：	compliant
风险等级：	5.42
Is Samacsys：	N
计数方向：	UP
JESD-30 代码：	R-XDIP-T14
JESD-609代码：	e0
负载/预设输入：	NO
逻辑集成电路类型：	BINARY COUNTER
工作模式：	ASYNCHRONOUS
功能数量：	2
端子数量：	14
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	CERAMIC
封装代码：	DIP
封装等效代码：	DIP14,.3
封装形状：	RECTANGULAR
封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V
认证状态：	Not Qualified
子类别：	Counters
标称供电电压 (Vsup)：	5 V
表面贴装：	NO
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

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产品型号74HCT393D的概述

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