74LCX04MTC原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

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产品型号74LCX04MTC的概述

74LCX04MTC芯片概述 74LCX04MTC是一种广泛使用的逻辑门芯片，具体为六个反相器。它属于74LCX系列，具有低功耗、高速和宽电压范围等特点。该芯片被广泛应用于数字电路设计、通讯系统以及各种嵌入式系统，能够实现信号的反转与逻辑转化。尤其是在现代高速数字电路设计中，由于其兼容CMOS和TTL逻辑，74LCX04MTC在数字信号处理中占据了重要的地位。芯片详细参数 74LCX04MTC的关键参数包括以下几个方面： 1. 供电电压：该芯片在2.0V至5.5V的范围内工作，允许低电压操作，适应现代电路设计对电源的严格要求。 2. 输入电平：对于TTL输入，74LCX04MTC的高电平(input high)为0.7Vcc，而低电平(input low)为0.3Vcc，确保在广泛的工作环境下依然能够保持准确的信号判别。 3. 输出电平：该芯片输出电流能力高达24mA，能保证信号在负...

产品型号74LCX04MTC的Datasheet PDF文件预览

March 1995

Revised February 2005

74LCX04

Low Voltage Hex Inverter with 5V Tolerant Inputs

General Description

The LCX04 contains six inverters. The inputs tolerate volt-

ages up to 7V allowing the interface of 5V systems to 3V

systems.

Features

■ 5V tolerant inputs

■ 2.3V–3.6V V_CCspecifications provided

■ 5.2 ns t_PDmax (V_CC3.3V), 10 A I_CCmax

■ Power down high impedance inputs and outputs

The 74LCX04 is fabricated with advanced CMOS technol-

ogy to achieve high speed operation while maintaining

CMOS low power dissipation.

■

24 mA output drive (V_CC3.0V)

■ Implements patented noise/EMI reduction circuitry

■ Latch-up performance exceeds JEDEC 78 conditions

■ ESD performance:

Human body model 2000V

Machine model 200V

■ Leadless Pb-Free DQFN package

Ordering Code:

Package

Order Number

Package Description

Number

74LCX04M

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74LCX04MX_NL

(Note 2)

Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74LCX04SJ

M14D

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LCX04BQX

(Note 1)

MLP014A Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC

MO-241, 2.5 x 3.0mm

74LCX04MTC

MTC14

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74LCX04MTCX_NL

(Note 2)

Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Note 1: DQFN package available in Tape and Reel only.

Note 2: “_NL” package available in Tape and Reel only.

DS012410

www.fairchildsemi.com

Logic Symbol

Connection Diagrams

IEEE/IEC

Pin Assignments for SOIC, SOP, and TSSOP

Pad Assignments for DQFN

Pin Descriptions

Pin Names

Description

Inputs

Outputs

A_n

O_n

(Top View)

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Absolute Maximum Ratings(Note 3)

Symbol

V_CC

V_I

Parameter

Supply Voltage

Value

Conditions

Units

0.5 to 7.0

DC Input Voltage

V_O

DC Output Voltage

0.5 to V_CC0.5 Output in HIGH or LOW State (Note 4)

I_IK

DC Input Diode Current

DC Output Diode Current

V_IGND

V_OGND

V_OV_CC

I_OK

I_O

DC Output Source/Sink Current

DC Supply Current per Supply Pin

DC Ground Current per Ground Pin

Storage Temperature

I_CC

100

I_GND

T_STG

100

65 to 150

Recommended Operating Conditions (Note 5)

Symbol

Parameter

Min

2.0

1.5

Max

3.6

5.5

V_CC

Units

V_CC

Supply Voltage

Operating

Data Retention

V_I

Input Voltage

Output Voltage

Output Current

V_O

HIGH or LOW State

V_CC3.0V 3.6V

V_CC2.7V 3.0V

V_CC2.3V 2.7V

_OH/I_OL

T_A

t/ V

Free-Air Operating Temperature

Input Edge Rate, V_IN0.8V–2.0V, V_CC3.0V

ns/V

Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated

at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-

mended Operating Conditions” table will define the conditions for actual device operation.

Note 4: I Absolute Maximum Rating must be observed.

Note 5: Unused inputs must be held HIGH or LOW. They may not float.

DC Electrical Characteristics

40 C to 85 C

Min Max

Symbol

Parameter

Conditions

Units

(V)

2.3 2.7

2.7 3.6

2.3 2.7

2.7 3.6

2.3 3.6

2.3

HIGH Level Input Voltage

1.7

2.0

LOW Level Input Voltage

HIGH Level Output Voltage

0.7

0.8

100

0.2

8 mA

1.8

2.2

2.4

2.2

12 mA

18 mA

24 mA

2.7

3.0

LOW Level Output Voltage

100

2.3 3.6

2.3

0.2

0.6

0.4

0.55

5.0

8 mA

12 mA

16 mA

24 mA

2.7

3.0

Input Leakage Current

5.5V

2.3 3.6

Power-Off Leakage Current

Quiescent Supply Current

V or V

OFF

or GND

5.5V

2.3 3.6

3.6V

Increase in I per Input

0.6V

500

www.fairchildsemi.com

AC Electrical Characteristics

40 C to 85 C, R

500

3.3V 0.3V

50 pF

2.7V

2.5V 0.2V

C 30 pF

Symbol

Parameter

Units

50 pF

Min

1.5

Max

Min

Max

6.0

Min

1.5

Max

Propagation Delay Time

5.2

1.0

1.5

6.2

PHL

6.0

PLH

Output to Output Skew

(Note 6)

OSHL

OSLH

Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t

) or LOW-to-HIGH (T

OSLH

OSHL

Dynamic Switching Characteristics

25 C

Symbol

Parameter

Conditions

Units

(V)

3.3

2.5

3.3

2.5

Typical

0.8

Quiet Output Dynamic Peak V

50 pF, V

30 pF, V

50 pF, V

30 pF, V

3.3V, V

2.5V, V

3.3V, V

2.5V, V

OLP

0.6

Quiet Output Dynamic Valley V

0.8

OLV

0.6

Capacitance

Symbol

Parameter

Conditions

Typical

Units

Input Capacitance

Output Capacitance

Power Dissipation Capacitance

Open, V 0V or V

3.3V, V 0V or V

OUT

3.3V, V 0V or V , f 10 MHz

www.fairchildsemi.com

AC Loading and Waveforms Generic for LCX Family

FIGURE 1. AC Test Circuit

(C_Lincludes probe and jig capacitance)

Test

Switch

t_PLH, t_PHL

t_PZL, t_PLZ

Open

6V at V_CC3.3 0.3V

V_CCx 2 at V_CC2.5 0.2V

t_PZH, t_PHZ

GND

3-STATE Output Low Enable and

Waveform for Inverting and Non-Inverting Functions

Disable Times for Logic

Setup Time, Hold TIme and Recovery TIme for Logic

Propagation Delay, Pulse Width and t_recWaveforms

3-STATE Output High Enable and

Disable TImes for Logic

t_riseand t_fall

FIGURE 2. Waveforms

(Input Pulse Characteristics; f =1MHz, t_r= t_f= 3ns)

V_CC

Symbol

V_mi

3.3V 0.3V

1.5V

2.7V

2.5V 0.2V

V_CC/2

1.5V

V_mo

V_x

1.5V

V_OL0.3V

V_OH0.3V

V_OL0.3V

V_OH0.3V

V_OL0.15V

V_OH0.15V

V_y

www.fairchildsemi.com

Schematic Diagram Generic for LCX Family

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Tape and Reel Specification

Tape Format for DQFN

Package

Tape

Section

Number

Cavities

125 (typ)

3000

Cavity

Status

Empty

Filled

Cover Tape

Status

Designator

Leader (Start End)

Carrier

Sealed

BQX

Sealed

Trailer (Hub End)

75 (typ)

Empty

Sealed

TAPE DIMENSIONS inches (millimeters)

REEL DIMENSIONS inches (millimeters)

Tape Size

13.0

0.059

(1.50)

0.512

(13.00)

0.795

(20.20)

2.165

0.488

(12.4)

0.724

(18.4)

12 mm

(330.0)

(55.00)

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M14A

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm

Package Number MLP014A

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC14

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

74LCX04MTC相关文章

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74LCX04MTC产品参数

型号:	74LCX04MTC
是否Rohs认证：	不符合
生命周期：	Transferred
IHS 制造商：	NATIONAL SEMICONDUCTOR CORP
包装说明：	4.40 MM, PLASTIC, TSSOP-14
Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01
风险等级：	5.57
Is Samacsys：	N
系列：	LVC/LCX/Z
JESD-30 代码：	R-PDSO-G14
JESD-609代码：	e0
长度：	5 mm
负载电容（CL）：	50 pF
逻辑集成电路类型：	INVERTER
最大I（ol）：	0.024 A
功能数量：	6
输入次数：	1
端子数量：	14
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP14,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：	3.3 V
Prop。Delay @ Nom-Sup：	5.2 ns
传播延迟（tpd）：	5.2 ns
认证状态：	Not Qualified
施密特触发器：	NO
座面最大高度：	1.1 mm
子类别：	Gates
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	2 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
宽度：	4.4 mm
Base Number Matches：	1

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