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产品型号74LVC1G02GW的概述

芯片74LVC1G02GW的概述 74LVC1G02GW是一款低电压、高速的单通道非门（NAND gate），它属于LVC（低电压CMOS）系列，广泛应用于数字电路设计中，以高效能和低功耗著称。此芯片设计旨在满足现代电子设备的性能要求，尤其是在更小的功耗和更快的信号处理速度方面。74LVC1G02GW采用CMOS技术，具有较大的噪声容限和较高的输入阻抗，这使其在各种应用中表现出色。 74LVC1G02GW可以在1.65V至5.5V的宽电压范围内工作，因此非常适合便携式和电池驱动的设备。其出色的速度特性使其在高频应用中表现良好，通常适用于开关电源、高速数字信号处理等领域。此型号的非门设计简化了逻辑运算，在多种电路中都能找到合适的应用场景。芯片74LVC1G02GW的详细参数以下是74LVC1G02GW的一些关键参数： - 电压范围：1.65V至5.5V - 工作温度范围：-40°C至...

产品型号74LVC1G02GW的Datasheet PDF文件预览

INTEGRATED CIRCUITS

DATA SHEET

74LVC1G02

Single 2-input NOR gate

Product speciﬁcation

2004 Sep 07

Supersedes data of 2002 Oct 02

Philips Semiconductors

Product speciﬁcation

Single 2-input NOR gate

74LVC1G02

FEATURES

DESCRIPTION

• Wide supply voltage range from 1.65 V to 5.5 V

• High noise immunity

The 74LVC1G02 is a high-performance, low-power,

low-voltage, Si-gate CMOS device, superior to most

advanced CMOS compatible TTL families.

• Complies with JEDEC standard:

– JESD8-7 (1.65 V to 1.95 V)

Input can be driven from either 3.3 V or 5 V devices.

These features allow the use of these devices in a mixed

3.3 V and 5 V environment.

– JESD8-5 (2.3 V to 2.7 V)

– JESD8B/JESD36 (2.7 V to 3.6 V).

• ±24 mA output drive (V_CC= 3.0 V)

• CMOS low power consumption

• Latch-up performance exceeds 250 mA

• Direct interface with TTL levels

• Inputs accept voltages up to 5 V

• Multiple package options

Schmitt trigger action at all inputs makes the circuit tolerant

for slower input rise and fall time.

This device is fully specified for partial power-down

applications using I_off. The I_offcircuitry disables the output,

preventing the damaging backflow current through the

device when it is powered down.

The 74LVC1G02 provides the single 2-input NOR

function.

• ESD protection:

HBM EIA/JESD22-A114-B exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

• Specified from −40 °C to +85 °C and −40 °C to +125 °C.

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C; t_r= t_f≤ 2.5 ns.

SYMBOL

PARAMETER

propagation delay

CONDITIONS

TYPICAL

UNIT

t_PHL/t_PLH

V_CC= 1.8 V; C_L= 30 pF; R_L= 1 kΩ

3.2

inputs A, B to output Y

V_CC= 2.5 V; C_L= 30 pF; R_L= 500 Ω 2.2

V_CC= 2.7 V; C_L= 50 pF; R_L= 500 Ω 2.5

V_CC= 3.3 V; C_L= 50 pF; R_L= 500 Ω 2.1

V_CC= 5.0 V; C_L= 50 pF; R_L= 500 Ω 1.7

C_I

input capacitance

C_PD

power dissipation capacitance per buffer V_CC= 3.3 V; notes 1 and 2

Notes

1. C_PDis used to determine the dynamic power dissipation (P_Din µW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in Volts;

N = total load switching outputs;

Σ(C_L× V_CC²× f_o) = sum of the outputs.

2. The condition is V_I= GND to V_CC

2004 Sep 07

Philips Semiconductors

Product speciﬁcation

Single 2-input NOR gate

74LVC1G02

FUNCTION TABLE

See note 1.

INPUT

OUTPUT

Note

1. H = HIGH voltage level;

L = LOW voltage level.

ORDERING INFORMATION

TYPE NUMBER

PACKAGE

TEMPERATURE

RANGE

PINS

PACKAGE MATERIAL

CODE

MARKING

74LVC1G02GW

74LVC1G02GV

74LVC1G02GM

−40 °C to +125 °C

SC-88A

SC-74A

XSON6

plastic

SOT353

SOT753

SOT886

V02

PINNING

PIN (TSSOP5 AND VSSOP5)

PIN (XSON6)

SYMBOL

DESCRIPTION

data input B

data input A

ground (0 V)

data output Y

not connected

supply voltage

GND

n.c.

V_CC

n.c.

GND

001aab611

001aab610

Transparent top view

Fig.1 Pin configuration TSSOP5 and VSSOP5.

Fig.2 Pin configuration XSON6.

2004 Sep 07

Philips Semiconductors

Product speciﬁcation

Single 2-input NOR gate

74LVC1G02

handbook, halfpage

≥1

MNA165

MNA103

Fig.3 Logic symbol.

Fig.4 IEE/IEC logic symbol.

handbook, halfpage

MNA166

Fig.5 Logic diagram.

2004 Sep 07

Philips Semiconductors

Product speciﬁcation

Single 2-input NOR gate

74LVC1G02

RECOMMENDED OPERATING CONDITIONS

SYMBOL

V_CC

PARAMETER

supply voltage

CONDITIONS

MIN.

1.65

MAX.

5.5

UNIT

V_I

input voltage

5.5

V_CC

5.5

+125

V_O

output voltage

active mode

V_CC= 0 V; Power-down mode

T_amb

t_r, t_f

operating ambient temperature

input rise and fall times

−40

°C

V_CC= 1.65 V to 2.7 V

V_CC= 2.7 V to 5.5 V

ns/V

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V_CCsupply voltage −0.5 +6.5

I_IK

input diode current

input voltage

V_I< 0 V

note 1

−

−50

V_I

−0.5

−

+6.5

±50

I_OK

V_O

output diode current

output voltage

V_O> V_CCor V_O< 0 V

active mode; notes 1 and 2

−0.5

V_CC+ 0.5

+6.5

±50

Power-down mode; notes 1 and 2 −0.5

I_O

output source and sink current

V_CCor GND current

V_O= 0 V to V_CC

−

°C

I_CC, I_GND

T_stg

−

±100

+150

250

storage temperature

power dissipation

−65

−

P_D

T_amb= −40 °C to +125 °C

Notes

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. When V_CC= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.

2004 Sep 07

Philips Semiconductors

Product speciﬁcation

Single 2-input NOR gate

74LVC1G02

DC CHARACTERISTICS

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

TEST CONDITIONS

SYMBOL

PARAMETER

MIN.

TYP.⁽¹⁾

MAX.

UNIT

OTHER

V_CC(V)

T_amb= −40 °C to +85 °C

V_IH

HIGH-level input

voltage

1.65 to 1.95 0.65 × V_CC

−

2.3 to 2.7

2.7 to 3.6

4.5 to 5.5

1.65 to 1.95

2.3 to 2.7

2.7 to 3.6

4.5 to 5.5

1.7

−

2.0

0.7 × V_CC

V_IL

LOW-level input

voltage

−

0.35 × V_CC

0.7

0.8

0.3 × V_CC

V_OL

LOW-level output

voltage

V_I= V_IHor V_IL

I_O= 100 µA

I_O= 4 mA

1.65 to 5.5

1.65

2.3

−

0.1

0.45

0.3

I_O= 8 mA

I_O= 12 mA

I_O= 24 mA

I_O= 32 mA

V_I= V_IHor V_IL

I_O= −100 µA

I_O= −4 mA

I_O= −8 mA

I_O= −12 mA

I_O= −24 mA

I_O= −32 mA

2.7

0.4

3.0

0.55

4.5

V_OH

HIGH-level output

voltage

1.65 to 5.5

1.65

2.3

_CC− 0.1

−

1.2

1.9

2.2

2.3

3.8

−

2.7

−

3.0

−

4.5

−

I_LI

input leakage current V_I= 5.5 V or GND 5.5

±0.1

±5

±10

µA

I_off

power OFF leakage

current

V_Ior V_O= 5.5 V

−

I_CC

quiescent supply

current

V_I= V_CCor GND; 5.5

I_O= 0 A

−

0.1

µA

∆I_CC

additional quiescent

V_I= V_CC− 0.6 V;

2.3 to 5.5

500

supply current per pin I_O= 0 A

2004 Sep 07

Philips Semiconductors

Product speciﬁcation

Single 2-input NOR gate

74LVC1G02

TEST CONDITIONS

SYMBOL

PARAMETER

MIN.

TYP.⁽¹⁾

MAX.

UNIT

OTHER

V_CC(V)

T_amb= −40 °C to +125 °C

V_IH

HIGH-level input

voltage

1.65 to 1.95 0.65 × V_CC

−

2.3 to 2.7

2.7 to 3.6

4.5 to 5.5

1.65 to 1.95

2.3 to 2.7

2.7 to 3.6

4.5 to 5.5

1.7

−

2.0

0.7 × V_CC

V_IL

LOW-level input

voltage

−

0.35 × V_CC

0.7

0.8

0.3 × V_CC

V_OL

LOW-level output

voltage

V_I= V_IHor V_IL

I_O= 100 µA

I_O= 4 mA

1.65 to 5.5

1.65

2.3

−

0.1

0.70

0.45

0.60

0.80

I_O= 8 mA

I_O= 12 mA

I_O= 24 mA

I_O= 32 mA

V_I= V_IHor V_IL

I_O= −100 µA

I_O= −4 mA

I_O= −8 mA

I_O= −12 mA

I_O= −24 mA

I_O= −32 mA

2.7

3.0

4.5

V_OH

HIGH-level output

voltage

1.65 to 5.5

1.65

2.3

_CC− 0.1

−

0.95

1.7

1.9

2.0

3.4

−

2.7

−

3.0

−

4.5

−

I_LI

input leakage current V_I= 5.5 V or GND 5.5

±0.1

±100

±200

µA

I_off

power OFF leakage

current

V_Ior V_O= 5.5 V

−

I_CC

quiescent supply

current

V_I= V_CCor GND; 5.5

I_O= 0 A

−

0.1

200

µA

∆I_CC

additional quiescent

V_I= V_CC− 0.6 V;

2.3 to 5.5

5000

supply current per pin I_O= 0 A

Note

1. All typical values are measured at V_CC= 3.3 V and T_amb= 25 °C.

2004 Sep 07

Philips Semiconductors

Product speciﬁcation

Single 2-input NOR gate

74LVC1G02

AC CHARACTERISTICS

GND = 0 V; t_r= t_f≤ 2.0 ns.

TEST CONDITIONS

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

WAVEFORMS

V_CC(V)

T_amb= −40 °C to +85 °C

t_PHL/t_PLH

propagation delay

A, B to Y

see Figs 6 and 7

1.65 to 1.95

2.3 to 2.7

2.7

1.0

3.2

8.0

0.5

2.2

2.5

2.1

1.7

5.5

4.5

4.0

3.0 to 3.6

4.5 to 5.5

T_amb= −40 °C to +125 °C

t_PHL/t_PLH

propagation delay

A, B to Y

see Figs 6 and 7

1.65 to 1.95

2.3 to 2.7

2.7

1.0

0.5

−

10.5

7.0

6.0

5.5

3.0 to 3.6

4.5 to 5.5

AC WAVEFORMS

handbook, halfpage

A, B input

GND

PHL

PLH

Y output

MNA612

INPUT

V_CC

V_M

V_I

t_r= t_f

1.65 V to 1.95 V 0.5 × V_CC

V_CC

≤ 2.0 ns

≤ 2.5 ns

2.3 V to 2.7 V

2.7 V

0.5 × V_CC

1.5 V

V_CC

2.7 V

V_CC

3.0 V to 3.6 V

4.5 V to 5.5 V

1.5 V

0.5 × V_CC

V_OLand V_OHare typical output voltage drop that occur with the output load.

Fig.6 Input A, B to output Y propagation delay times.

2004 Sep 07

Philips Semiconductors

Product speciﬁcation

Single 2-input NOR gate

74LVC1G02

handbook, full pagewidth

EXT

PULSE

GENERATOR

D.U.T.

MNA616

V_EXT

V_CC

V_I

C_L

R_L

t_PLH/t_PHL

t_PZH/t_PHZ

t_PZL/t_PLZ

1.65 V to 1.95 V V_CC

30 pF

50 pF

1 kΩ

open

GND

2 × V_CC

6 V

2.3 V to 2.7 V

2.7 V

V_CC

500 Ω

2.7 V

V_CC

3.0 V to 3.6 V

4.5 V to 5.5 V

6 V

2 × V_CC

Definitions for test circuit:

R_L= Load resistor.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to the output impedance Z_oof the pulse generator.

Fig.7 Load circuitry for switching times.

2004 Sep 07

Philips Semiconductors

Product speciﬁcation

Single 2-input NOR gate

74LVC1G02

PACKAGE OUTLINES

Plastic surface mounted package; 5 leads

SOT353

M B

detail X

2 mm

scale

DIMENSIONS (mm are the original dimensions)

(2)

UNIT

max

0.30

0.20

1.1

0.8

0.25

0.10

2.2

1.8

1.35

1.15

2.2

2.0

0.45

0.15

0.25

0.15

0.1

1.3

0.65

0.2

0.1

REFERENCES

JEDEC

EUROPEAN

PROJECTION

OUTLINE

VERSION

ISSUE DATE

IEC

EIAJ

SC-88A

97-02-28

SOT353

2004 Sep 07

Philips Semiconductors

Product speciﬁcation

Single 2-input NOR gate

74LVC1G02

Plastic surface mounted package; 5 leads

SOT753

detail X

M B

2 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT

0.100

0.013

0.40

0.25

1.1

0.9

0.26

0.10

3.1

2.7

1.7

1.3

3.0

2.5

0.6

0.2

0.33

0.23

0.95

0.2

0.1

REFERENCES

JEDEC JEITA

EUROPEAN

PROJECTION

OUTLINE

VERSION

ISSUE DATE

IEC

SOT753

SC-74A

02-04-16

2004 Sep 07

Philips Semiconductors

Product speciﬁcation

Single 2-input NOR gate

74LVC1G02

XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm

SOT886

4×

(2)

6×

(2)

terminal 1

index area

2 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

UNIT

max max

0.25

0.17

1.5

1.4

1.05

0.95

0.35 0.40

0.27 0.32

0.5 0.04

0.6

0.5

Notes

1. Including plating thickness.

2. Can be visible in some manufacturing processes.

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

04-07-15

04-07-22

SOT886

MO-252

2004 Sep 07

Philips Semiconductors

Product speciﬁcation

Single 2-input NOR gate

74LVC1G02

DATA SHEET STATUS

DATA SHEET

STATUS⁽¹⁾

PRODUCT

STATUS⁽²⁾⁽³⁾

LEVEL

DEFINITION

Objective data

Development This data sheet contains data from the objective speciﬁcation for product

development. Philips Semiconductors reserves the right to change the

speciﬁcation in any manner without notice.

Preliminary data Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the speciﬁcation without

notice, in order to improve the design and supply the best possible

product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips

Semiconductors reserves the right to make changes at any time in order

to improve the design, manufacturing and supply. Relevant changes will

be communicated via a Customer Product/Process Change Notiﬁcation

(CPCN).

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

DEFINITIONS

DISCLAIMERS

Short-form specification

The data in a short-form

Life support applications

These products are not

specification is extracted from a full data sheet with the

same type number and title. For detailed information see

the relevant data sheet or data handbook.

designed for use in life support appliances, devices, or

systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips

Semiconductors customers using or selling these products

for use in such applications do so at their own risk and

agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Limiting values definition Limiting values given are in

accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device.

These are stress ratings only and operation of the device

at these or at any other conditions above those given in the

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may

affect device reliability.

Right to make changes

Philips Semiconductors

reserves the right to make changes in the products -

including circuits, standard cells, and/or software -

described or contained herein in order to improve design

and/or performance. When the product is in full production

(status ‘Production’), relevant changes will be

Application information

Applications that are

communicated via a Customer Product/Process Change

Notification (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these

products, conveys no licence or title under any patent,

makes no representations or warranties that these

products are free from patent, copyright, or mask work

right infringement, unless otherwise specified.

described herein for any of these products are for

illustrative purposes only. Philips Semiconductors make

no representation or warranty that such applications will be

suitable for the specified use without further testing or

modification.

2004 Sep 07

Philips Semiconductors – a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales ofﬁces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

SCA76

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

R20/05/pp14

Date of release: 2004 Sep 07

Document order number: 9397 750 13753

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74LVC1G02GW产品参数

型号:	74LVC1G02GW
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	NEXPERIA
包装说明：	TSSOP-5
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	0.84
Samacsys Confidence：
Samacsys Status：	Released
Samacsys PartID：	342915
Samacsys Pin Count：	5
Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	Other
Samacsys Footprint Name：	SOT65P210X110-5N
Samacsys Released Date：	2017-01-12 09:39:31
Is Samacsys：	N
系列：	LVC/LCX/Z
JESD-30 代码：	R-PDSO-G5
JESD-609代码：	e3
长度：	2.05 mm
逻辑集成电路类型：	NOR GATE
湿度敏感等级：	1
功能数量：	1
输入次数：	2
端子数量：	5
最高工作温度：	125 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
传播延迟（tpd）：	10.5 ns
认证状态：	Not Qualified
座面最大高度：	1.1 mm
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	1.65 V
标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES
技术：	CMOS
温度等级：	AUTOMOTIVE
端子面层：	Tin (Sn)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
宽度：	1.25 mm
Base Number Matches：	1

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产品型号74LVC1G02GW的概述

产品型号74LVC1G02GW的Datasheet PDF文件预览

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