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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

  • 74LVC1G34GW
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  • 深圳市宗天技术开发有限公司

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  • 深圳市芯脉实业有限公司

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  • 深圳市芯脉实业有限公司

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  • 深圳市拓森弘电子有限公司

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  • 数量5300 
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  • 深圳市芯福林电子有限公司

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  • 深圳市晶美隆科技有限公司

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  • 北京元坤伟业科技有限公司

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  • 深圳市积美福电子科技有限公司

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  • 数量1636 
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产品型号74LVC1G34GW的概述

芯片74LVC1G34GW的概述 74LVC1G34GW是一款领先的逻辑电路芯片,属于74LVC系列。这款单个输入和输出的非反相缓冲器能够提供高达5V的逻辑输入电压,并兼容多种逻辑电平,适用于TTL及CMOS电路。这款芯片因其低功耗、高速和优异的电气特性,已广泛应用于多种电子产品中,如汽车电子、消费电子和工业控制系统等。 74LVC1G34GW采用的是单通道配置,输入可以是1位信号,输出信号与输入保持一致,其电路设计使得在处理不同电平时,输出信号即可进行稳定转换,因而在大多数应用场景中呈现出很好的兼容性和灵活性。此外,74LVC1G34GW支持三态输出控制,允许在多个设备连接时实现有效的数据交换,增强了系统的可扩展性。 芯片74LVC1G34GW的详细参数 - 逻辑功能: 非反相缓冲器 - 工作电压范围: 1.65V至5.5V - 输入电压范围: 0V至5.5V - 工作温度范围: -...

产品型号74LVC1G34GW的Datasheet PDF文件预览

74LVC1G34  
Single buffer  
Rev. 02 — 21 May 2007  
Product data sheet  
1. General description  
The 74LVC1G34 provides a low-power, low-voltage single buffer.  
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of  
this device in a mixed 3.3 V and 5 V environment.  
This device is fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing the damaging backflow current through the device  
when it is powered down.  
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and  
fall times.  
2. Features  
Wide supply voltage range from 1.65 V to 5.5 V  
5 V tolerant inputs for interfacing with 5 V logic  
High noise immunity  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8-B/JESD36 (2.7 V to 3.6 V).  
±24 mA output drive (VCC = 3.0 V)  
ESD protection:  
HBM JESD22-A114E exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
CMOS low power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Multiple package options  
Specified from 40 °C to +85 °C and 40 °C to +125 °C  
74LVC1G34  
NXP Semiconductors  
Single buffer  
3. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74LVC1G34GW  
40 °C to +125 °C  
TSSOP5  
plastic thin shrink small outline package; 5 leads;  
body width 1.25 mm  
SOT353-1  
74LVC1G34GV  
74LVC1G34GM  
40 °C to +125 °C  
40 °C to +125 °C  
SC-74A  
XSON6  
plastic surface-mounted package; 5 leads  
SOT753  
plastic extremely thin small outline package; no leads; SOT886  
6 terminals; body 1 × 1.45 × 0.5 mm  
74LVC1G34GF  
40 °C to +125 °C  
XSON6  
plastic extremely thin small outline package; no leads; SOT891  
6 terminals; body 1 × 1 × 0.5 mm  
4. Marking  
Table 2.  
Marking  
Type number  
74LVC1G34GW  
74LVC1G34GV  
74LVC1G34GM  
74LVC1G34GF  
Marking code  
YN  
YN  
YN  
YN  
5. Functional diagram  
2
A
Y
4
2
4
A
Y
001aac538  
001aac537  
001aac536  
Fig 1. Logic symbol  
Fig 2. IEC logic symbol  
Fig 3. Logic diagram  
74LVC1G34_2  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 02 — 21 May 2007  
2 of 15  
74LVC1G34  
NXP Semiconductors  
Single buffer  
6. Pinning information  
6.1 Pinning  
74LVC1G34  
74LVC1G34  
n.c.  
A
1
2
3
6
5
4
V
CC  
74LVC1G34  
1
2
3
5
4
n.c.  
A
V
Y
n.c.  
A
1
2
3
6
5
4
V
CC  
CC  
n.c.  
Y
n.c.  
Y
GND  
GND  
GND  
001aag504  
001aag505  
Transparent top view  
Transparent top view  
001aag503  
Fig 4. Pin configuration SOT353-1  
and SOT753  
Fig 5. Pin configuration SOT886  
Fig 6. Pin configuration SOT891  
6.2 Pin description  
Table 3.  
Symbol  
Pin description  
Pin  
Description  
SOT353-1/SOT753  
SOT886/SOT891  
n.c.  
A
1
2
3
4
-
1
2
3
4
5
6
not connected  
data input  
GND  
Y
ground (0 V)  
data output  
n.c.  
VCC  
not connected  
supply voltage  
5
7. Functional description  
Table 4.  
Function table[1]  
Input  
Output  
A
L
Y
L
H
H
[1] H = HIGH voltage level;  
L = LOW voltage level.  
74LVC1G34_2  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 02 — 21 May 2007  
3 of 15  
74LVC1G34  
NXP Semiconductors  
Single buffer  
8. Limiting values  
Table 5.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).  
Symbol  
VCC  
IIK  
Parameter  
Conditions  
Min  
0.5  
50  
0.5  
-
Max  
+6.5  
-
Unit  
V
supply voltage  
input clamping current  
input voltage  
VI < 0 V  
mA  
V
[1]  
VI  
+6.5  
±50  
VCC + 0.5  
+6.5  
±50  
100  
-
IOK  
output clamping current  
output voltage  
VO > VCC or VO < 0 V  
Active mode  
mA  
V
[1][2]  
[1][2]  
VO  
0.5  
0.5  
-
Power-down mode  
VO = 0 V to VCC  
V
IO  
output current  
mA  
mA  
mA  
mW  
°C  
ICC  
IGND  
Ptot  
Tstg  
supply current  
-
ground current  
100  
-
[3]  
total power dissipation  
storage temperature  
Tamb = 40 °C to +125 °C  
250  
+150  
65  
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.  
[3] For TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.  
For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.  
9. Recommended operating conditions  
Table 6.  
Symbol  
VCC  
Recommended operating conditions  
Parameter  
Conditions  
Min  
Typ  
Max  
5.5  
Unit  
V
supply voltage  
input voltage  
output voltage  
1.65  
-
-
-
-
-
-
-
VI  
0
5.5  
V
VO  
Active mode  
0
VCC  
5.5  
VO  
VO  
°C  
VCC = 0 V; Power-down mode  
0
Tamb  
ambient temperature  
40  
+125  
20  
t/V  
input transition rise and fall rate VCC = 1.65 V to 2.7 V  
VCC = 2.7 V to 5.5 V  
-
-
ns/V  
ns/V  
10  
74LVC1G34_2  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 02 — 21 May 2007  
4 of 15  
74LVC1G34  
NXP Semiconductors  
Single buffer  
10. Static characteristics  
Table 7.  
Static characteristics  
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Tamb = 40 °C to +85 °C[1]  
VIH  
HIGH-level input voltage  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
0.65 × VCC  
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7  
-
2.0  
-
0.7 × VCC  
-
VIL  
LOW-level input voltage  
-
-
-
-
0.35 × VCC  
0.7  
0.8  
0.3 × VCC  
VOH  
HIGH-level output voltage VI = VIH or VIL  
IO = 100 µA; VCC = 1.65 V to 5.5 V  
V
CC 0.1  
-
-
-
-
-
-
-
V
V
V
V
V
V
IO = 4 mA; VCC = 1.65 V  
IO = 8 mA; VCC = 2.3 V  
IO = 12 mA; VCC = 2.7 V  
IO = 24 mA; VCC = 3.0 V  
IO = 32 mA; VCC = 4.5 V  
VI = VIH or VIL  
1.2  
1.9  
2.2  
2.3  
3.8  
1.54  
2.15  
2.50  
2.62  
4.11  
VOL  
LOW-level output voltage  
IO = 100 µA; VCC = 1.65 V to 5.5 V  
IO = 4 mA; VCC = 1.65 V  
IO = 8 mA; VCC = 2.3 V  
-
-
-
-
-
-
-
-
-
-
0.10  
0.45  
0.30  
0.40  
0.55  
0.55  
±5  
V
0.07  
0.12  
0.17  
0.33  
0.39  
±0.1  
±0.1  
0.1  
V
V
IO = 12 mA; VCC = 2.7 V  
IO = 24 mA; VCC = 3.0 V  
IO = 32 mA; VCC = 4.5 V  
VCC = 0 V to 5.5 V; VI = 5.5 V or GND  
V
V
V
[2]  
[2]  
II  
input leakage current  
µA  
µA  
µA  
IOFF  
ICC  
power-off leakage current VCC = 0 V; VI or VO = 5.5 V  
±10  
10  
supply current  
VCC = 1.65 V to 5.5 V; IO = 0 A;  
VI = 5.5 V or GND  
ICC  
additional supply current  
input capacitance  
VCC = 2.3 V to 5.5 V; VI = VCC 0.6 V;  
IO = 0 A  
-
-
5
4
500  
-
µA  
CI  
VCC = 3.3 V; VI = GND to VCC  
pF  
Tamb = 40 °C to +125 °C  
VIH  
HIGH-level input voltage  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
0.65 × VCC  
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7  
-
2.0  
-
0.7 × VCC  
-
VIL  
LOW-level input voltage  
-
-
-
-
0.35 × VCC  
0.7  
0.8  
0.3 × VCC  
74LVC1G34_2  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 02 — 21 May 2007  
5 of 15  
74LVC1G34  
NXP Semiconductors  
Single buffer  
Table 7.  
Static characteristics …continued  
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
VOH HIGH-level output voltage VI = VIH or VIL  
IO = 100 µA; VCC = 1.65 V to 5.5 V  
Conditions  
Min  
Typ  
Max  
Unit  
VCC 0.1  
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
IO = 4 mA; VCC = 1.65 V  
IO = 8 mA; VCC = 2.3 V  
IO = 12 mA; VCC = 2.7 V  
IO = 24 mA; VCC = 3.0 V  
IO = 32 mA; VCC = 4.5 V  
VI = VIH or VIL  
0.95  
1.7  
1.9  
2.0  
3.4  
VOL  
LOW-level output voltage  
IO = 100 µA; VCC = 1.65 V to 5.5 V  
IO = 4 mA; VCC = 1.65 V  
IO = 8 mA; VCC = 2.3 V  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.10  
0.70  
0.45  
0.60  
0.80  
0.80  
±100  
±200  
200  
V
V
V
IO = 12 mA; VCC = 2.7 V  
IO = 24 mA; VCC = 3.0 V  
IO = 32 mA; VCC = 4.5 V  
VCC = 0 V to 5.5 V; VI = 5.5 V or GND  
V
V
V
II  
input leakage current  
µA  
µA  
µA  
IOFF  
ICC  
power-off leakage current VCC = 0 V; VI or VO = 5.5 V  
supply current  
VCC = 1.65 V to 5.5 V; IO = 0 A;  
VI = 5.5 V or GND  
ICC  
additional supply current  
VCC = 2.3 V to 5.5 V; VI = VCC 0.6 V;  
-
-
5000  
µA  
IO = 0 A  
[1] All typical values are measured at Tamb = 25 °C.  
[2] These typical values are measured at VCC = 3.3 V.  
74LVC1G34_2  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 02 — 21 May 2007  
6 of 15  
74LVC1G34  
NXP Semiconductors  
Single buffer  
11. Dynamic characteristics  
Table 8.  
Dynamic characteristics  
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.  
Symbol Parameter Conditions 40 °C to +85 °C  
40 °C to +125 °C Unit  
Min  
Typ[1]  
Max  
Min  
Max  
[2]  
tpd  
propagation delay A to Y; see Figure 7  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
1.0  
0.5  
0.5  
0.5  
0.5  
-
4.0  
2.6  
2.3  
2.0  
1.6  
15  
8.6  
4.4  
4.5  
4.1  
3.2  
-
1.0  
0.5  
0.5  
0.5  
0.5  
-
11.0  
5.6  
5.6  
5.2  
4.1  
-
ns  
ns  
ns  
ns  
ns  
pF  
VCC = 2.7 V  
VCC = 3.0 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
[3]  
CPD  
power dissipation VI = GND to VCC; VCC = 3.3 V  
capacitance  
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V, and 5.0 V respectively.  
[2] tpd is the same as tPLH and tPHL  
.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).  
PD = CPD × VCC2 × fi × N + (CL × VCC2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in V;  
N = number of inputs switching;  
(CL × VCC2 × fo) = sum of outputs.  
12. Waveforms  
V
I
V
A input  
M
GND  
t
t
PHL  
PLH  
V
OH  
V
Y output  
M
V
mnb153  
OL  
Measurement points are given in Table 9.  
VOL and VOH are typical output voltage drops that occur with the output load.  
Fig 7. The data input (A) to output (Y) propagation delays  
74LVC1G34_2  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 02 — 21 May 2007  
7 of 15  
74LVC1G34  
NXP Semiconductors  
Single buffer  
Table 9.  
Measurement points  
Supply voltage  
VCC  
Input  
Output  
VM  
VM  
1.65 V to 1.95 V  
2.3 V to 2.7 V  
2.7 V  
0.5 × VCC  
0.5 × VCC  
1.5 V  
0.5 × VCC  
0.5 × VCC  
1.5 V  
3.0 V to 3.6 V  
4.5 V to 5.5 V  
1.5 V  
1.5 V  
0.5 × VCC  
0.5 × VCC  
V
EXT  
V
CC  
R
L
L
V
V
O
I
PULSE  
GENERATOR  
DUT  
R
T
C
L
R
mna616  
Test data is given in Table 10.  
Definitions for test circuit:  
RL = Load resistance.  
CL = Load capacitance including jig and probe capacitance.  
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.  
VEXT = External voltage for measuring switching times.  
Fig 8. Load circuitry for switching times  
Table 10. Test data  
Supply voltage  
VCC  
Input  
VI  
Load  
CL  
VEXT  
tr = tf  
RL  
tPLH, tPHL  
open  
1.65 V to 1.95 V  
2.3 V to 2.7 V  
2.7 V  
VCC  
VCC  
2.7 V  
2.7 V  
VCC  
2.0 ns  
2.0 ns  
2.5 ns  
2.5 ns  
2.5 ns  
30 pF  
30 pF  
50 pF  
50 pF  
50 pF  
1 kΩ  
500 Ω  
500 Ω  
500 Ω  
500 Ω  
open  
open  
3.0 V to 3.6 V  
4.5 V to 5.5 V  
open  
open  
74LVC1G34_2  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 02 — 21 May 2007  
8 of 15  
74LVC1G34  
NXP Semiconductors  
Single buffer  
13. Package outline  
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm  
SOT353-1  
D
E
A
X
c
y
H
v
M
A
E
Z
5
4
A
2
A
(A )  
3
A
1
θ
L
L
p
1
3
e
w M  
b
p
detail X  
e
1
0
1.5  
3 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
A
A
A
b
c
D
E
e
e
1
H
L
L
p
UNIT  
v
w
y
Z
θ
1
2
3
p
E
max.  
0.1  
0
1.0  
0.8  
0.30  
0.15  
0.25  
0.08  
2.25  
1.85  
1.35  
1.15  
2.25  
2.0  
0.46  
0.21  
0.60  
0.15  
7°  
0°  
mm  
1.1  
0.65  
1.3  
0.15  
0.425  
0.3  
0.1  
0.1  
Note  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
00-09-01  
03-02-19  
SOT353-1  
MO-203  
SC-88A  
Fig 9. Package outline SOT353-1 (TSSOP5)  
74LVC1G34_2  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 02 — 21 May 2007  
9 of 15  
74LVC1G34  
NXP Semiconductors  
Single buffer  
Plastic surface-mounted package; 5 leads  
SOT753  
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
c
L
p
1
2
3
detail X  
e
b
p
w
M B  
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
UNIT  
A
A
b
c
D
E
e
H
L
Q
v
w
y
p
1
p
E
0.100  
0.013  
0.40  
0.25  
1.1  
0.9  
0.26  
0.10  
3.1  
2.7  
1.7  
1.3  
3.0  
2.5  
0.6  
0.2  
0.33  
0.23  
mm  
0.95  
0.2  
0.2  
0.1  
REFERENCES  
JEDEC JEITA  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
02-04-16  
06-03-16  
SOT753  
SC-74A  
Fig 10. Package outline SOT753 (SC-74A)  
74LVC1G34_2  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 02 — 21 May 2007  
10 of 15  
74LVC1G34  
NXP Semiconductors  
Single buffer  
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm  
SOT886  
b
1
2
3
4×  
(2)  
L
L
1
e
6
5
4
e
1
e
1
6×  
(2)  
A
A
1
D
E
terminal 1  
index area  
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
A
A
1
UNIT  
b
D
E
e
e
L
L
1
1
max max  
0.25  
0.17  
1.5  
1.4  
1.05  
0.95  
0.35 0.40  
0.27 0.32  
mm  
0.5 0.04  
0.6  
0.5  
Notes  
1. Including plating thickness.  
2. Can be visible in some manufacturing processes.  
REFERENCES  
JEDEC JEITA  
OUTLINE  
VERSION  
EUROPEAN  
PROJECTION  
ISSUE DATE  
IEC  
04-07-15  
04-07-22  
SOT886  
MO-252  
Fig 11. Package outline SOT886 (XSON6)  
74LVC1G34_2  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 02 — 21 May 2007  
11 of 15  
74LVC1G34  
NXP Semiconductors  
Single buffer  
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm  
SOT891  
b
1
2
3
4×  
(1)  
L
L
1
e
6
5
4
e
1
e
1
6×  
(1)  
A
A
1
D
E
terminal 1  
index area  
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
A
1
UNIT  
b
D
E
e
e
L
L
1
1
max max  
0.20 1.05 1.05  
0.12 0.95 0.95  
0.35 0.40  
0.27 0.32  
mm  
0.5 0.04  
0.55 0.35  
Note  
1. Can be visible in some manufacturing processes.  
REFERENCES  
JEDEC JEITA  
OUTLINE  
VERSION  
EUROPEAN  
PROJECTION  
ISSUE DATE  
IEC  
05-04-06  
07-05-15  
SOT891  
Fig 12. Package outline SOT891 (XSON6)  
74LVC1G34_2  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 02 — 21 May 2007  
12 of 15  
74LVC1G34  
NXP Semiconductors  
Single buffer  
14. Abbreviations  
Table 11. Abbreviations  
Acronym  
CMOS  
DUT  
Description  
Complementary Metal Oxide Semiconductor  
Device Under Test  
ESD  
ElectroStatic Discharge  
Human Body Model  
HBM  
MM  
Machine Model  
TTL  
Transistor-Transistor Logic  
15. Revision history  
Table 12. Revision history  
Document ID  
74LVC1G34_2  
Modifications:  
Release date  
20070521  
Data sheet status  
Change notice  
Supersedes  
Product data sheet  
-
74LVC1G34_1  
The format of this data sheet has been redesigned to comply with the new identity guidelines  
of NXP Semiconductors.  
Legal texts have been adapted to the new company name where appropriate.  
Added type number 74LVC1G34GF (XSON6/SOT891 package)  
Section 10 “Static characteristics”:  
Changed: Conditions for input leakage and supply current.  
74LVC1G34_1  
20051107  
Product data sheet  
-
-
74LVC1G34_2  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 02 — 21 May 2007  
13 of 15  
74LVC1G34  
NXP Semiconductors  
Single buffer  
16. Legal information  
16.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
malfunction of a NXP Semiconductors product can reasonably be expected to  
16.2 Definitions  
result in personal injury, death or severe property or environmental damage.  
NXP Semiconductors accepts no liability for inclusion and/or use of NXP  
Semiconductors products in such equipment or applications and therefore  
such inclusion and/or use is at the customer’s own risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) may cause permanent  
damage to the device. Limiting values are stress ratings only and operation of  
the device at these or any other conditions above those given in the  
Characteristics sections of this document is not implied. Exposure to limiting  
values for extended periods may affect device reliability.  
Terms and conditions of sale — NXP Semiconductors products are sold  
subject to the general terms and conditions of commercial sale, as published  
at http://www.nxp.com/profile/terms, including those pertaining to warranty,  
intellectual property rights infringement and limitation of liability, unless  
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of  
any inconsistency or conflict between information in this document and such  
terms and conditions, the latter will prevail.  
16.3 Disclaimers  
General — Information in this document is believed to be accurate and  
reliable. However, NXP Semiconductors does not give any representations or  
warranties, expressed or implied, as to the accuracy or completeness of such  
information and shall have no liability for the consequences of use of such  
information.  
No offer to sell or license — Nothing in this document may be interpreted  
or construed as an offer to sell products that is open for acceptance or the  
grant, conveyance or implication of any license under any copyrights, patents  
or other industrial or intellectual property rights.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
16.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in medical, military, aircraft,  
space or life support equipment, nor in applications where failure or  
17. Contact information  
For additional information, please visit: http://www.nxp.com  
For sales office addresses, send an email to: salesaddresses@nxp.com  
74LVC1G34_2  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 02 — 21 May 2007  
14 of 15  
74LVC1G34  
NXP Semiconductors  
Single buffer  
18. Contents  
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2  
6
6.1  
6.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3  
7
Functional description . . . . . . . . . . . . . . . . . . . 3  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Recommended operating conditions. . . . . . . . 4  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5  
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7  
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13  
8
9
10  
11  
12  
13  
14  
15  
16  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
16.1  
16.2  
16.3  
16.4  
17  
18  
Contact information. . . . . . . . . . . . . . . . . . . . . 14  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2007.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 21 May 2007  
Document identifier: 74LVC1G34_2  
配单直通车
74LVC1G34GW产品参数
型号:74LVC1G34GW
是否Rohs认证: 符合
生命周期:Active
包装说明:TSSOP,
Reach Compliance Code:compliant
HTS代码:8542.39.00.01
风险等级:5.4
系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G5
JESD-609代码:e3
长度:2.05 mm
逻辑集成电路类型:BUFFER
湿度敏感等级:1
功能数量:1
输入次数:1
端子数量:5
最高工作温度:125 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260
传播延迟(tpd):11 ns
认证状态:Not Qualified
座面最大高度:1.1 mm
最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):3.3 V
表面贴装:YES
技术:CMOS
温度等级:AUTOMOTIVE
端子面层:Tin (Sn)
端子形式:GULL WING
端子节距:0.65 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:30
宽度:1.25 mm
Base Number Matches:1
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