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产品型号74LVC1G384GW-Q100的Datasheet PDF文件预览

74LVC1G384-Q100  
Bilateral switch  
Rev. 1 — 19 February 2013  
Product data sheet  
1. General description  
The 74LVC1G384-Q100 provides one single pole, single throw analog switch function. It  
has two input/output terminals (Y and Z) and an active LOW enable input pin (E). When  
pin E is HIGH, the analog switch is turned off.  
Schmitt trigger action at the enable input makes the circuit tolerant of slower input rise and  
fall times across the entire VCC range from 1.65 V to 5.5 V.  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
Wide supply voltage range from 1.65 V to 5.5 V  
Very low ON resistance:  
7.5 (typical) at VCC = 2.7 V  
6.5 (typical) at VCC = 3.3 V  
6 (typical) at VCC = 5 V  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  
Switch current capability of 32 mA  
High noise immunity  
CMOS low power consumption  
TTL interface compatibility at 3.3 V  
Latch-up performance meets requirements of JESD 78 Class I  
Enable input accepts voltages up to 5.5 V  
Inputs accept voltages up to 5 V  
Multiple package options  
 
 
74LVC1G384-Q100  
NXP Semiconductors  
Bilateral switch  
3. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Temperature  
range  
Name  
Description  
Version  
74LVC1G384GW-Q100 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads;  
SOT353-1  
SOT753  
body width 1.25 mm  
74LVC1G384GV-Q100 40 C to +125 C SC-74A plastic surface-mounted package; 5 leads  
4. Marking  
Table 2.  
Marking  
Type number  
Marking code[1]  
74LVC1G384GW-Q100  
74LVC1G384GV-Q100  
YL  
YL  
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.  
5. Functional diagram  
1
E
1
2
1
4 #  
Z
Y
X1  
001aaa373  
001aag476  
Fig 1. Logic symbol  
Fig 2. IEC logic symbol  
Z
Y
E
V
CC  
001aaa372  
Fig 3. Logic diagram  
74LVC1G384_100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 1 — 19 February 2013  
2 of 21  
 
 
 
 
74LVC1G384-Q100  
NXP Semiconductors  
Bilateral switch  
6. Pinning information  
6.1 Pinning  
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢁꢉꢊꢅꢋꢋ  
ꢆꢆ  
ꢉꢊꢋ  
ꢀꢀꢀꢁꢂꢂꢃꢄꢅꢆ  
Fig 4. Pin configuration SOT353-1 and SOT753  
6.2 Pin description  
Table 3.  
Pin description  
Symbol  
Pin  
1
Description  
Y
independent input or output  
independent output or input  
ground (0 V)  
Z
2
GND  
E
3
4
enable input (active LOW)  
supply voltage  
VCC  
5
7. Functional description  
Table 4.  
Function table[1]  
Input E  
Switch  
L
ON-state  
H
OFF-state  
[1] H = HIGH voltage level; L = LOW voltage level.  
74LVC1G384_100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 1 — 19 February 2013  
3 of 21  
 
 
 
 
 
74LVC1G384-Q100  
NXP Semiconductors  
Bilateral switch  
8. Limiting values  
Table 5.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).  
Symbol  
VCC  
VI  
Parameter  
Conditions  
Min  
0.5  
0.5  
50  
-
Max  
+6.5  
+6.5  
-
Unit  
V
supply voltage  
[1]  
[2]  
input voltage  
V
IIK  
input clamping current  
switch clamping current  
switch voltage  
VI < 0.5 V or VI > VCC + 0.5 V  
VI < 0.5 V or VI > VCC + 0.5 V  
enable and disable mode  
mA  
mA  
V
ISK  
50  
VCC + 0.5  
50  
100  
-
VSW  
ISW  
0.5  
-
switch current  
VSW > 0.5 V or VSW < VCC + 0.5 V  
mA  
mA  
mA  
C  
ICC  
supply current  
-
IGND  
Tstg  
Ptot  
ground current  
100  
65  
-
storage temperature  
total power dissipation  
+150  
250  
[3]  
Tamb = 40 C to +125 C  
mW  
[1] The minimum input voltage rating may be exceeded if the input current rating is observed.  
[2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed.  
[3] For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.  
9. Recommended operating conditions  
Table 6.  
Symbol  
VCC  
Recommended operating conditions  
Parameter  
Conditions  
Min  
Typ  
Max  
5.5  
Unit  
V
supply voltage  
input voltage  
1.65  
-
-
-
-
-
-
VI  
0
5.5  
V
[1]  
VSW  
switch voltage  
ambient temperature  
0
VCC  
+125  
20  
V
Tamb  
40  
C  
t/V  
input transition rise and  
fall rate  
VCC = 1.65 V to 2.7 V  
VCC = 2.7 V to 5.5 V  
-
-
ns/V  
ns/V  
10  
[1] To avoid sinking GND current from terminal Z when switch current flows in terminal Y, the voltage drop across the bidirectional switch  
must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current flows from terminal Y. In this case, there is no limit for  
the voltage drop across the switch.  
74LVC1G384_100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 1 — 19 February 2013  
4 of 21  
 
 
 
 
 
 
74LVC1G384-Q100  
NXP Semiconductors  
Bilateral switch  
10. Static characteristics  
Table 7.  
Static characteristics  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
40 C to +85 C  
40 C to +125 C Unit  
Min  
Typ[1]  
Max  
Min  
Max  
VIH  
HIGH-level  
input voltage  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
0.65VCC  
-
-
0.65VCC  
-
V
V
V
V
V
V
V
V
A  
1.7  
-
-
1.7  
-
-
2.0  
-
-
-
2.0  
0.7VCC  
-
0.7VCC  
-
VIL  
LOW-level  
input voltage  
-
-
-
-
-
-
0.35VCC  
0.7  
-
-
-
-
-
0.35VCC  
0.7  
-
-
-
0.8  
0.8  
0.3VCC  
5  
0.3VCC  
100  
[2]  
[2]  
II  
input leakage pin E; VI = 5.5 V or GND;  
current  
0.1  
VCC = 0 V to 5.5 V  
IS(OFF)  
OFF-state  
leakage  
current  
VCC = 5.5 V; see Figure 5  
-
-
-
0.1  
0.1  
0.1  
5  
5  
10  
-
-
-
200  
200  
200  
A  
A  
A  
[2]  
[2]  
[2]  
IS(ON)  
ON-state  
leakage  
current  
VCC = 5.5 V; see Figure 6  
ICC  
supply current VI = 5.5 V or GND;  
VSW = GND or VCC; VCC = 1.65 V  
to 5.5 V  
ICC  
additional  
pin E; VI = VCC 0.6 V;  
-
-
-
-
5
500  
-
-
-
-
5000  
A  
pF  
pF  
pF  
supply current VSW = GND or VCC; VCC = 5.5 V  
CI  
input  
capacitance  
2.0  
5.0  
9.5  
-
-
-
-
-
-
CS(OFF) OFF-state  
capacitance  
CS(ON)  
ON-state  
capacitance  
[1] All typical values are measured at Tamb = 25 C.  
[2] These typical values are measured at VCC = 3.3 V.  
74LVC1G384_100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 1 — 19 February 2013  
5 of 21  
 
 
 
74LVC1G384-Q100  
NXP Semiconductors  
Bilateral switch  
10.1 Test circuits  
V
V
CC  
CC  
E
Z
E
Z
V
V
IL  
IH  
Y
Y
I
I
S
S
GND  
GND  
V
V
V
V
O
I
O
I
001aag479  
001aag480  
VI = VCC or GND and VO = GND or VCC  
.
VI = VCC or GND and VO = open circuit.  
Fig 5. Test circuit for measuring OFF-state leakage  
current  
Fig 6. Test circuit for measuring ON-state leakage  
current  
10.2 ON resistance  
Table 8.  
ON resistance  
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 8 to Figure 13.  
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit  
Min Typ[1] Max  
Min  
Max  
RON(peak) ON resistance (peak) VI = GND to VCC; see Figure 7  
ISW = 4 mA;  
-
34.0  
130  
-
195  
VCC = 1.65 V to 1.95 V  
I
SW = 8 mA; VCC = 2.3 V to 2.7 V  
-
-
-
-
12.0  
10.4  
7.8  
30  
25  
20  
15  
-
-
-
-
45  
38  
30  
23  
ISW = 12 mA; VCC = 2.7 V  
ISW = 24 mA; VCC = 3 V to 3.6 V  
ISW = 32 mA; VCC = 4.5 V to 5.5 V  
VI = GND; see Figure 7  
6.2  
RON(rail)  
ON resistance (rail)  
ISW = 4 mA;  
-
8.2  
18  
-
27  
VCC = 1.65 V to 1.95 V  
ISW = 8 mA; VCC = 2.3 V to 2.7 V  
ISW = 12 mA; VCC = 2.7 V  
ISW = 24 mA; VCC = 3 V to 3.6 V  
ISW = 32 mA; VCC = 4.5 V to 5.5 V  
VI = VCC; see Figure 7  
-
-
-
-
7.1  
6.9  
6.5  
5.8  
16  
14  
12  
10  
-
-
-
-
-
-
24  
21  
18  
15  
ISW = 4 mA;  
-
10.4  
30  
45  
VCC = 1.65 V to 1.95 V  
ISW = 8 mA; VCC = 2.3 V to 2.7 V  
ISW = 12 mA; VCC = 2.7 V  
-
-
-
-
7.6  
7.0  
6.1  
4.9  
20  
18  
15  
10  
-
-
-
-
30  
27  
23  
15  
ISW = 24 mA; VCC = 3 V to 3.6 V  
ISW = 32 mA; VCC = 4.5 V to 5.5 V  
74LVC1G384_100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 1 — 19 February 2013  
6 of 21  
 
 
74LVC1G384-Q100  
NXP Semiconductors  
Bilateral switch  
Table 8.  
ON resistance …continued  
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 8 to Figure 13.  
Symbol Parameter  
Conditions  
40 C to +85 C 40 C to +125 C Unit  
Min Typ[1] Max  
Min  
Max  
[2]  
RON(flat)  
ON resistance  
(flatness)  
VI = GND to VCC  
ISW = 4 mA;  
-
26.0  
-
-
-
VCC = 1.65 V to 1.95 V  
ISW = 8 mA; VCC = 2.3 V to 2.7 V  
ISW = 12 mA; VCC = 2.7 V  
-
-
-
-
5.0  
3.5  
2.0  
1.5  
-
-
-
-
-
-
-
-
-
-
-
-
ISW = 24 mA; VCC = 3 V to 3.6 V  
ISW = 32 mA; VCC = 4.5 V to 5.5 V  
[1] Typical values are measured at Tamb = 25 C and nominal VCC  
.
[2] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and  
temperature.  
10.3 ON resistance test circuit and graphs  
mna673  
40  
R
ON  
(Ω)  
30  
V
SW  
(1)  
20  
10  
0
V
CC  
E
Y
(2)  
(3)  
V
IL  
Z
(4)  
(5)  
4
GND  
V
I
I
SW  
0
1
2
3
5
V (V)  
I
001aag481  
RON = VSW / ISW  
.
(1) VCC = 1.8 V.  
(2) VCC = 2.5 V.  
(3) VCC = 2.7 V.  
(4)  
VCC = 3.3 V.  
(5) VCC = 5.0 V.  
Fig 7. Test circuit for measuring ON resistance  
Fig 8. Typical ON resistance as a function of input  
voltage; Tamb = 25 C  
74LVC1G384_100  
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Bilateral switch  
001aaa712  
001aaa708  
55  
15  
R
ON  
R
ON  
(Ω)  
(Ω)  
45  
13  
35  
25  
15  
5
11  
9
(4)  
(3)  
(2)  
(1)  
(1)  
(2)  
(3)  
(4)  
7
5
0
0.4  
0.8  
1.2  
1.6  
2.0  
0
0.5  
1.0  
1.5  
2.0  
2.5  
V (V)  
I
V (V)  
I
(1) Tamb = 125 C.  
(2) amb = 85 C.  
(1) Tamb = 125 C.  
(2) amb = 85 C.  
T
T
(3) Tamb = 25 C.  
(4) Tamb = 40 C.  
(3) Tamb = 25 C.  
(4) Tamb = 40 C.  
Fig 9. ON resistance as a function of input voltage;  
VCC = 1.8 V  
Fig 10. ON resistance as a function of input voltage;  
VCC = 2.5 V  
001aaa709  
001aaa710  
13  
10  
R
(Ω)  
ON  
R
(Ω)  
ON  
11  
8
6
4
(1)  
(1)  
(2)  
9
7
5
(2)  
(3)  
(3)  
(4)  
(4)  
0
0.5  
1.0  
1.5  
2.0  
2.5 3.0  
V (V)  
I
0
1
2
3
4
V (V)  
I
(1) Tamb = 125 C.  
(2) amb = 85 C.  
(1) Tamb = 125 C.  
(2) amb = 85 C.  
T
T
(3) Tamb = 25 C.  
(4) Tamb = 40 C.  
(3) Tamb = 25 C.  
(4) Tamb = 40 C.  
Fig 11. ON resistance as a function of input voltage;  
VCC = 2.7 V  
Fig 12. ON resistance as a function of input voltage;  
VCC = 3.3 V  
74LVC1G384_100  
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Bilateral switch  
001aaa711  
7
6
5
4
3
R
ON  
(Ω)  
(1)  
(2)  
(3)  
(4)  
0
1
2
3
4
5
V (V)  
I
(1) Tamb = 125 C.  
(2)  
Tamb = 85 C.  
(3) Tamb = 25 C.  
(4) Tamb = 40 C.  
Fig 13. ON resistance as a function of input voltage; VCC = 5.0 V  
11. Dynamic characteristics  
Table 9.  
Dynamic characteristics  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 16.  
Symbol Parameter  
Conditions  
40 C to +85 C  
40 C to +125 C Unit  
Min Typ[1] Max  
Min  
Max  
[2][3]  
tpd  
propagation delay Y to Z or Z to Y; see Figure 14  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
-
-
-
-
-
0.8  
0.4  
0.4  
0.3  
0.2  
2.0  
1.2  
1.0  
0.8  
0.6  
-
-
-
-
-
3.0  
2.0  
1.5  
1.5  
1.0  
ns  
ns  
ns  
ns  
ns  
VCC = 2.7 V  
VCC = 3.0 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
[4]  
ten  
enable time  
E to Y or Z; see Figure 15  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V  
1.0  
1.0  
1.0  
1.0  
1.0  
10.0 12.0  
1.0  
1.0  
1.0  
1.0  
1.0  
15.5  
8.5  
8.0  
6.5  
5.5  
ns  
ns  
ns  
ns  
ns  
5.7  
5.4  
4.8  
3.3  
6.5  
6.0  
5.0  
4.2  
VCC = 3.0 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
74LVC1G384_100  
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Bilateral switch  
Table 9.  
Dynamic characteristics …continued  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 16.  
Symbol Parameter  
Conditions  
40 C to +85 C  
40 C to +125 C Unit  
Min Typ[1] Max  
Min  
Max  
[5]  
tdis  
disable time  
E to Y or Z; see Figure 15  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V  
1.0  
1.0  
1.0  
1.0  
1.0  
7.4  
4.1  
4.9  
5.4  
3.6  
10.0  
6.9  
7.5  
6.5  
5.0  
1.0  
1.0  
1.0  
1.0  
1.0  
13.0  
9.0  
9.5  
8.5  
6.5  
ns  
ns  
ns  
ns  
ns  
VCC = 3.0 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
[6]  
CPD  
power dissipation CL = 50 pF; fi = 10 MHz;  
capacitance  
VI = GND to VCC  
VCC = 2.5 V  
-
-
-
13.7  
15.2  
18.3  
-
-
-
-
-
-
-
-
-
pF  
pF  
pF  
VCC = 3.3 V  
VCC = 5.0 V  
[1] Typical values are measured at Tamb = 25 C and nominal VCC  
.
[2] tpd is the same as tPLH and tPHL  
.
[3] propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when  
driven by an ideal voltage source (zero output impedance).  
[4]  
ten is the same as tPZH and tPZL.  
[5] tdis is the same as tPLZ and tPHZ  
.
[6] CPD is used to determine the dynamic power dissipation (PD in W).  
PD = CPD VCC2 fi N + {(CL + CS(ON)) VCC2 fo} where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
CS(ON) = maximum ON-state switch capacitance in pF;  
VCC = supply voltage in V;  
N = number of inputs switching;  
{(CL + CS(ON)) VCC2 fo} = sum of the outputs.  
11.1 Waveforms and test circuit  
V
I
V
Y or Z input  
M
GND  
t
t
PLH  
PHL  
V
OH  
V
Z or Y output  
M
V
OL  
mna667  
Measurement points are given in Table 10.  
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.  
Fig 14. Input (Y or Z) to output (Z or Y) propagation delays  
74LVC1G384_100  
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Bilateral switch  
V
I
E
V
M
GND  
t
t
PZL  
PLZ  
V
CC  
output  
LOW-to-OFF  
OFF-to-LOW  
V
M
Y or Z  
V
X
V
OL  
t
t
PHZ  
PZH  
V
OH  
V
Y
output  
HIGH-to-OFF  
OFF-to-HIGH  
V
Y or Z  
M
GND  
switch  
enabled  
switch  
enabled  
switch  
disabled  
001aaa375  
Measurement points are given in Table 10.  
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.  
Fig 15. Enable and disable times  
Table 10. Measurement points  
Supply voltage  
VCC  
Input  
Output  
VM  
VM  
VX  
VY  
1.65 V to 1.95 V  
2.3 V to 2.7 V  
2.7 V  
0.5VCC  
0.5VCC  
1.5 V  
1.5 V  
0.5VCC  
0.5VCC  
0.5VCC  
1.5 V  
VOL + 0.15 V  
VOL + 0.15 V  
VOL + 0.3 V  
VOL + 0.3 V  
VOL + 0.3 V  
VOH 0.15 V  
VOH 0.15 V  
VOH 0.3 V  
VOH 0.3 V  
VOH 0.3 V  
3.0 V to 3.6 V  
4.5 V to 5.5 V  
1.5 V  
0.5VCC  
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Bilateral switch  
V
EXT  
V
CC  
R
L
L
V
V
O
I
G
DUT  
R
T
C
L
R
mna616  
Test data is given in Table 11.  
Definitions for test circuit:  
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.  
CL = Load capacitance including jig and probe capacitance.  
RL = Load resistance.  
VEXT = External voltage for measuring switching times.  
Fig 16. Test circuit for measuring switching times  
Table 11. Test data  
Supply voltage  
VCC  
Input  
VI  
Load  
CL  
VEXT  
tr, tf  
RL  
tPLH, tPHL  
open  
tPZH, tPHZ  
GND  
tPZL, tPLZ  
2VCC  
2VCC  
6 V  
1.65 V to 1.95 V  
2.3 V to 2.7 V  
2.7 V  
VCC  
VCC  
2.7 V  
2.7 V  
VCC  
2.0 ns  
2.0 ns  
2.5 ns  
2.5 ns  
2.5 ns  
30 pF  
30 pF  
50 pF  
50 pF  
50 pF  
1 k  
500   
500   
500   
500   
open  
GND  
open  
GND  
3.0 V to 3.6 V  
4.5 V to 5.5 V  
open  
GND  
6 V  
open  
GND  
2VCC  
11.2 Additional dynamic characteristics  
Table 12. Additional dynamic characteristics  
At recommended operating conditions; typical values measured at Tamb = 25 C.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
THD  
total harmonic distortion  
RL = 10 k; CL = 50 pF; fi = 1 kHz;  
see Figure 17  
VCC = 1.65 V  
VCC = 2.3 V  
VCC = 3.0 V  
VCC = 4.5 V  
-
-
-
-
0.032  
0.008  
0.006  
0.001  
-
-
-
-
%
%
%
%
RL = 10 k; CL = 50 pF; fi = 10 kHz;  
see Figure 17  
VCC = 1.65 V  
VCC = 2.3 V  
VCC = 3.0 V  
VCC = 4.5 V  
-
-
-
-
0.068  
0.009  
0.008  
0.006  
-
-
-
-
%
%
%
%
74LVC1G384_100  
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NXP Semiconductors  
Bilateral switch  
Table 12. Additional dynamic characteristics …continued  
At recommended operating conditions; typical values measured at Tamb = 25 C.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
f(3dB)  
3 dB frequency response RL = 600 ; CL = 50 pF;  
see Figure 18  
VCC = 1.65 V  
VCC = 2.3 V  
VCC = 3.0 V  
VCC = 4.5 V  
-
-
-
-
135  
145  
150  
155  
-
-
-
-
MHz  
MHz  
MHz  
MHz  
RL = 50 ; CL = 5 pF; see Figure 18  
VCC = 1.65 V  
VCC = 2.3 V  
-
-
-
-
> 500  
> 500  
> 500  
> 500  
-
-
-
-
MHz  
MHz  
MHz  
MHz  
VCC = 3.0 V  
VCC = 4.5 V  
RL = 50 ; CL = 10 pF; see Figure 18  
VCC = 1.65 V  
-
-
-
-
200  
350  
410  
440  
-
-
-
-
MHz  
MHz  
MHz  
MHz  
VCC = 2.3 V  
VCC = 3.0 V  
VCC = 4.5 V  
iso  
isolation (OFF-state)  
RL = 600 ; CL = 50 pF; fi = 1 MHz;  
see Figure 19  
VCC = 1.65 V  
VCC = 2.3 V  
VCC = 3.0 V  
VCC = 4.5 V  
-
-
-
-
46  
46  
46  
46  
-
-
-
-
dB  
dB  
dB  
dB  
RL = 50 ; CL = 5 pF; fi = 1 MHz;  
see Figure 19  
VCC = 1.65 V  
VCC = 2.3 V  
-
-
-
-
37  
37  
37  
37  
-
-
-
-
dB  
dB  
dB  
dB  
VCC = 3.0 V  
VCC = 4.5 V  
Vct  
crosstalk voltage  
between digital input and switch;  
RL = 600 ; CL = 50 pF; fi = 1 MHz;  
tr = tf = 2 ns; see Figure 20  
VCC = 1.65 V  
VCC = 2.3 V  
VCC = 3.0 V  
VCC = 4.5 V  
-
-
-
-
69  
-
-
-
-
mV  
mV  
mV  
mV  
87  
156  
302  
74LVC1G384_100  
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Product data sheet  
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NXP Semiconductors  
Bilateral switch  
Table 12. Additional dynamic characteristics …continued  
At recommended operating conditions; typical values measured at Tamb = 25 C.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Qinj  
charge injection  
CL = 0.1 nF; Vgen = 0 V; Rgen = 0 ;  
fi = 1 MHz; RL = 1 M; see  
Section 11  
VCC = 1.8 V  
VCC = 2.5 V  
VCC = 3.3 V  
VCC = 4.5 V  
VCC = 5.5 V  
-
-
-
-
-
3.3  
4.1  
5.0  
6.4  
7.5  
-
-
-
-
-
pC  
pC  
pC  
pC  
pC  
11.3 Test circuits  
V
0.5V  
CC  
CC  
E
V
IL  
R
L
10 μF  
Y/Z  
Z/Y  
V
O
f
600 Ω  
C
L
D
i
001aag482  
Test conditions:  
VCC = 1.65 V: VI = 1.4 V (p-p).  
VCC = 2.3 V: VI = 2 V (p-p).  
V
CC = 3 V: VI = 2.5 V (p-p).  
VCC = 4.5 V: VI = 4 V (p-p).  
Fig 17. Test circuit for measuring total harmonic distortion  
V
0.5V  
CC  
CC  
E
V
IL  
R
L
0.1 pF  
Y/Z  
Z/Y  
V
O
f
50 Ω  
C
L
dB  
i
001aag483  
To obtain 0 dBm level at input, adjust fi voltage. Increase fi frequency until dB meter reads 3 dB.  
Fig 18. Test circuit for measuring the frequency response when switch is in ON-state  
74LVC1G384_100  
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NXP Semiconductors  
Bilateral switch  
0.5V  
V
0.5V  
CC  
CC  
CC  
E
R
L
V
R
L
IH  
0.1 pF  
Y/Z  
Z/Y  
V
O
f
50 Ω  
C
L
dB  
i
001aag484  
To obtain 0 dBm level at input, adjust fi voltage.  
Fig 19. Test circuit for measuring isolation (OFF-state)  
V
CC  
E
Y/Z  
Z/Y  
V
O
G
logic  
input  
R
L
C
L
50 Ω  
600 Ω  
0.5V  
0.5V  
001aag485  
CC  
CC  
Fig 20. Test circuit for measuring crosstalk between digital inputs and switch  
V
CC  
E
R
gen  
Y/Z  
Z/Y  
V
O
G
logic  
input  
R
L
C
L
V
gen  
001aag486  
logic  
input  
(E) off  
on  
off  
V
O
ΔV  
O
001aaa368  
Qinj = VO CL.  
VO = output voltage variation.  
gen = generator resistance.  
Vgen = generator voltage.  
R
Fig 21. Test circuit for measuring charge injection  
74LVC1G384_100  
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74LVC1G384-Q100  
NXP Semiconductors  
Bilateral switch  
12. Package outline  
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm  
SOT353-1  
D
E
A
X
c
y
H
v
M
A
E
Z
5
4
A
2
A
(A )  
3
A
1
θ
L
L
p
1
3
e
w M  
b
p
detail X  
e
1
0
1.5  
3 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
A
A
A
b
c
D
E
e
e
1
H
L
L
p
UNIT  
v
w
y
Z
θ
1
2
3
p
E
max.  
0.1  
0
1.0  
0.8  
0.30  
0.15  
0.25  
0.08  
2.25  
1.85  
1.35  
1.15  
2.25  
2.0  
0.46  
0.21  
0.60  
0.15  
7°  
0°  
mm  
1.1  
0.65  
1.3  
0.15  
0.425  
0.3  
0.1  
0.1  
Note  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
00-09-01  
03-02-19  
SOT353-1  
MO-203  
SC-88A  
Fig 22. Package outline SOT353-1 (TSSOP5)  
74LVC1G384_100  
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Product data sheet  
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74LVC1G384-Q100  
NXP Semiconductors  
Bilateral switch  
Plastic surface-mounted package; 5 leads  
SOT753  
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
c
L
1
2
3
p
detail X  
e
b
p
w
M B  
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
UNIT  
A
A
b
c
D
E
e
H
L
Q
v
w
y
p
1
p
E
0.100  
0.013  
0.40  
0.25  
1.1  
0.9  
0.26  
0.10  
3.1  
2.7  
1.7  
1.3  
3.0  
2.5  
0.6  
0.2  
0.33  
0.23  
mm  
0.95  
0.2  
0.2  
0.1  
REFERENCES  
JEDEC JEITA  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
02-04-16  
06-03-16  
SOT753  
SC-74A  
Fig 23. Package outline SOT753 (SC-74A)  
74LVC1G384_100  
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Product data sheet  
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Bilateral switch  
13. Abbreviations  
Table 13. Abbreviations  
Acronym  
CMOS  
DUT  
Description  
Complementary Metal Oxide Semiconductor  
Device Under Test  
ESD  
ElectroStatic Discharge  
Human Body Model  
HBM  
MM  
Machine Model  
MIL  
Military  
TTL  
Transistor-Transistor Logic  
14. Revision history  
Table 14. Revision history  
Document ID  
Release date  
Data sheet status  
Change notice  
Supersedes  
74LVC1G384_Q100 v.1 20130219  
Product data sheet  
-
-
74LVC1G384_100  
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Bilateral switch  
15. Legal information  
15.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
Suitability for use in automotive applications — This NXP  
15.2 Definitions  
Semiconductors product has been qualified for use in automotive  
applications. Unless otherwise agreed in writing, the product is not designed,  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors and its suppliers accept no liability for  
inclusion and/or use of NXP Semiconductors products in such equipment or  
applications and therefore such inclusion and/or use is at the customer's own  
risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
15.3 Disclaimers  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information. NXP Semiconductors takes no  
responsibility for the content in this document if provided by an information  
source outside of NXP Semiconductors.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
74LVC1G384_100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 1 — 19 February 2013  
19 of 21  
 
 
 
 
74LVC1G384-Q100  
NXP Semiconductors  
Bilateral switch  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Translations — A non-English (translated) version of a document is for  
reference only. The English version shall prevail in case of any discrepancy  
between the translated and English versions.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from competent authorities.  
15.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
16. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
74LVC1G384_100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 1 — 19 February 2013  
20 of 21  
 
 
74LVC1G384-Q100  
NXP Semiconductors  
Bilateral switch  
17. Contents  
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2  
6
6.1  
6.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3  
7
8
9
Functional description . . . . . . . . . . . . . . . . . . . 3  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Recommended operating conditions. . . . . . . . 4  
10  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5  
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 6  
ON resistance test circuit and graphs. . . . . . . . 7  
10.1  
10.2  
10.3  
11  
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9  
Waveforms and test circuit . . . . . . . . . . . . . . . 10  
Additional dynamic characteristics . . . . . . . . . 12  
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
11.1  
11.2  
11.3  
12  
13  
14  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18  
15  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
15.1  
15.2  
15.3  
15.4  
16  
17  
Contact information. . . . . . . . . . . . . . . . . . . . . 20  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2013.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 19 February 2013  
Document identifier: 74LVC1G384_100  
 
配单直通车
74LVC1G384GW-Q100产品参数
型号:74LVC1G384GW-Q100
生命周期:Transferred
包装说明:,
Reach Compliance Code:unknown
HTS代码:8542.39.00.01
风险等级:5.63
模拟集成电路 - 其他类型:SPST
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