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74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

Rev. 9 — 5 August 2010

Product data sheet

1. General description

The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D)

inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q

outputs.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing damaging backflow current through the device

when it is powered down.

The set and reset are asynchronous active LOW inputs and operate independently of the

clock input. Information on the data input is transferred to the Q output on the

LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time

prior to the LOW-to-HIGH clock transition for predictable operation.

Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and

fall times.

2. Features and benefits

Wide supply voltage range from 1.65 V to 5.5 V

5 V tolerant inputs for interfacing with 5 V logic

High noise immunity

Complies with JEDEC standard:

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8-B/JESD36 (2.7 V to 3.6 V)

ESD protection:

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

±24 mA output drive (V_CC= 3.0 V)

CMOS low power consumption

Latch-up performance exceeds 250 mA

Direct interface with TTL levels

Inputs accept voltages up to 5 V

Multiple package options

Specified from −40 °C to +85 °C and −40 °C to +125 °C

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVC1G74DP

74LVC1G74DC

74LVC1G74GT

74LVC1G74GF

74LVC1G74GD

74LVC1G74GM

74LVC1G74GN

74LVC1G74GS

−40 °C to +125 °C

TSSOP8 plastic thin shrink small outline package; 8 leads; body SOT505-2

width 3 mm; lead length 0.5 mm

VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1

body width 2.3 mm

XSON8

plastic extremely thin small outline package; no leads; 8 SOT833-1

terminals; body 1 × 1.95 × 0.5 mm

XSON8

extremely thin small outline package; no leads;

SOT1089

8 terminals; body 1.35 × 1 × 0.5 mm

XSON8U plastic extremely thin small outline package; no leads; SOT996-2

8 terminals; UTLP based; body 3 × 2 × 0.5 mm

XQFN8U plastic extremely thin quad flat package; no leads;

SOT902-1

SOT1116

SOT1203

8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm

XSON8

extremely thin small outline package; no leads;

8 terminals; body 1.2 × 1.0 × 0.35 mm

extremely thin small outline package; no leads;

8 terminals; body 1.35 × 1.0 × 0.35 mm

4. Marking

Table 2.

Marking codes

Type number

74LVC1G74DP

74LVC1G74DC

74LVC1G74GT

74LVC1G74GF

74LVC1G74GD

74LVC1G74GM

74LVC1G74GN

74LVC1G74GS

Marking code^[1]

V74

Y4

V74

Y4

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

74LVC1G74

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Product data sheet

Rev. 9 — 5 August 2010

2 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

5. Functional diagram

SD

Q

D

Q

CP

S

CP

FF

C1

1D

R

RD

001aah757

001aah758

Fig 1. Logic symbol

Fig 2. IEC logic symbol

Q

C

Q

C

D

RD

SD

CP

mna421

C

Fig 3. Logic diagram

74LVC1G74

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Product data sheet

Rev. 9 — 5 August 2010

3 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

6. Pinning information

6.1 Pinning

74LVC1G74

CP

D

1

2

3

4

8

7

6

5

V

CC

SD

RD

Q

74LVC1G74

Q

1

2

3

4

8

7

6

5

CP

D

V

CC

SD

RD

Q

GND

Q

GND

001aab658

Transparent top view

001aab659

Fig 4. Pin configuration SOT505-2 and SOT765-1

Fig 5. Pin configuration SOT833-1, SOT1089,

SOT1116 and SOT1203

74LVC1G74

terminal 1

index area

SD

1

7

6

5

CP

D

CP

D

1

2

3

4

8

7

6

5

V

CC

RD

Q

2

3

SD

RD

Q

74LVC1G74

Q

GND

001aaf641

001aah948

Transparent top view

Fig 6. Pin configuration SOT996-2

Fig 7. Pin configuration SOT902-1

74LVC1G74

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Product data sheet

Rev. 9 — 5 August 2010

4 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

6.2 Pin description

Table 3.

Symbol

Pin description

Description

SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT902-1

SOT996-2, SOT1116 and SOT1203

CP

D

1

2

3

4

5

6

7

8

7

6

5

4

3

2

1

8

clock input (LOW-to-HIGH, edge-triggered)

data input

Q

complement output

GND

Q

ground (0 V)

true output

RD

SD

V_CC

asynchronous reset-direct input (active LOW)

asynchronous set-direct input (active LOW)

supply voltage

7. Functional description

Table 4.

Function table for asynchronous operation^[1]

Input

SD

L

Output

RD

H

CP

X

D

X

Q

H

L

Q

L

H

L

X

H

L

X

H

[1] H = HIGH voltage level;

L = LOW voltage level;

X = don’t care.

Table 5.

Input

SD

Function table for synchronous operation^[1]

Output

RD

H

CP

↑

D

L

Q_n+1

L

Q_n+1

H

↑

H

L

[1] H = HIGH voltage level;

L = LOW voltage level;

↑ = LOW-to-HIGH CP transition;

Q_n+1= state after the next LOW-to-HIGH CP transition.

74LVC1G74

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Product data sheet

Rev. 9 — 5 August 2010

5 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

8. Limiting values

Table 6.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

−0.5

−50

−0.5

-

Max

+6.5

-

Unit

V

supply voltage

input clamping current

input voltage

V_I< 0 V

mA

V

[1]

V_I

+6.5

±50

V_CC+ 0.5

+6.5

±50

100

-

I_OK

output clamping current

output voltage

V_O> V_CCor V_O< 0 V

Active mode

mA

V

[1]

V_O

−0.5

-

[1][2]

Power-down mode

V_O= 0 V to V_CC

V

I_O

output current

mA

mW

°C

I_CC

I_GND

P_tot

T_stg

supply current

-

ground current

−100

-

[3]

total power dissipation

storage temperature

T_amb= −40 °C to +125 °C

300

+150

−65

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] When V_CC= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.

[3] For TSSOP8 packages: above 55 °C the value of P_totderates linearly with 2.5 mW/K.

For VSSOP8 packages: above 110 °C the value of P_totderates linearly with 8.0 mW/K.

For XSON8, XSON8U and XQFN8U packages: above 118 °C the value of P_totderates linearly with 7.8 mW/K.

9. Recommended operating conditions

Table 7.

Symbol

V_CC

Operating conditions

Parameter

Conditions

Min

Max

5.5

Unit

supply voltage

input voltage

1.65

V

V_I

0

5.5

V

V_O

output voltage

Active mode

0

V_CC

5.5

V

Power-down mode; V_CC= 0 V

0

V

T_amb

ambient temperature

−40

+125

20

°C

ns/V

Δt/ΔV

input transition rise and fall rate

V_CC= 1.65 V to 2.7 V

V_CC= 2.7 V to 5.5 V

-

10

74LVC1G74

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Product data sheet

Rev. 9 — 5 August 2010

6 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

10. Static characteristics

Table 8.

Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Typ^[1]

Max

Unit

T_amb= −40 °C to +85 °C

V_IH

HIGH-level input voltage V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

0.65 × V_CC

-

V

1.7

-

V_CC= 2.7 V to 3.6 V

2.0

-

V_CC= 4.5 V to 5.5 V

0.7 × V_CC

-

V_IL

LOW-level input voltage

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_CC= 4.5 V to 5.5 V

-

0.35 × V_CC

0.7

0.8

0.3 × V_CC

V_OH

HIGH-level output voltage V_I= V_IHor V_IL

I_O= −100 μA; V_CC= 1.65 V to 5.5 V

V_CC− 0.1

1.2

-

V

I_O= −4 mA; V_CC= 1.65 V

I_O= −8 mA; V_CC= 2.3 V

I_O= −12 mA; V_CC= 2.7 V

I_O= −24 mA; V_CC= 3.0 V

I_O= −32 mA; V_CC= 4.5 V

1.54

2.15

2.50

2.62

4.11

1.9

2.2

2.3

3.8

V_OL

LOW-level output voltage V_I= V_IHor V_IL

I_O= 100 μA; V_CC= 1.65 V to 5.5 V

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

-

0.10

0.45

0.30

0.40

0.55

±5

V

0.07

0.12

0.17

0.33

0.39

±0.1

V

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

I_O= 32 mA; V_CC= 4.5 V

V

I_I

input leakage current

V_I= 5.5 V or GND;

V_CC= 0 V to 5.5 V

μA

I_OFF

I_CC

power-off leakage current V_Ior V_O= 5.5 V; V_CC= 0 V

supply current V_I= 5.5 V or GND;

_CC= 1.65 V to 5.5 V; I_O= 0 A

-

±0.1

±10

μA

0.1

10

V

ΔI_CC

additional supply current per pin; V_I= V_CC− 0.6 V; I_O= 0 A;

-

5

500

-

μA

V_CC= 2.3 V to 5.5 V

C_I

input capacitance

4.0

pF

74LVC1G74

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Product data sheet

Rev. 9 — 5 August 2010

7 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

Table 8.

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Typ^[1]

Max

Unit

T_amb= −40 °C to +125 °C

V_IH

HIGH-level input voltage V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

0.65 × V_CC

-

V

1.7

-

V_CC= 2.7 V to 3.6 V

2.0

-

V_CC= 4.5 V to 5.5 V

0.7 × V_CC

-

V_IL

LOW-level input voltage

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_CC= 4.5 V to 5.5 V

-

0.35 × V_CC

0.7

0.8

0.3 × V_CC

V_OH

HIGH-level output voltage V_I= V_IHor V_IL

I_O= −100 μA; V_CC= 1.65 V to 5.5 V

V_CC− 0.1

0.95

1.7

-

V

I_O= −4 mA; V_CC= 1.65 V

I_O= −8 mA; V_CC= 2.3 V

I_O= −12 mA; V_CC= 2.7 V

I_O= −24 mA; V_CC= 3.0 V

I_O= −32 mA; V_CC= 4.5 V

1.9

2.0

3.4

V_OL

LOW-level output voltage V_I= V_IHor V_IL

I_O= 100 μA; V_CC= 1.65 V to 5.5 V

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

-

0.10

0.70

0.45

0.60

0.80

±20

V

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

I_O= 32 mA; V_CC= 4.5 V

V

I_I

input leakage current

V_I= 5.5 V or GND;

V_CC= 0 V to 5.5 V

μA

I_OFF

I_CC

power-off leakage current V_Ior V_O= 5.5 V; V_CC= 0 V

-

±20

μA

supply current

V_I= 5.5 V or GND;

40

V_CC= 1.65 V to 5.5 V; I_O= 0 A

ΔI_CC

additional supply current per pin; V_I= V_CC− 0.6 V; I_O= 0 A;

-

5000

μA

V_CC= 2.3 V to 5.5 V

[1] All typical values are measured at T_amb= 25 °C.

74LVC1G74

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Product data sheet

Rev. 9 — 5 August 2010

8 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

11. Dynamic characteristics

Table 9.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.

Symbol Parameter Conditions −40 °C to +85 °C

−40 °C to +125 °C

Unit

Min

Typ^[1]

Max

Min

Max

[2]

t_pd

propagation delay CP to Q, Q; see Figure 8

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.5

1.0

6.0

3.5

2.5

13.4

7.1

5.9

4.1

1.5

1.0

13.4

7.1

5.9

4.1

ns

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

SD to Q, Q; see Figure 9

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.5

1.0

6.0

3.5

3.0

2.5

12.9

7.0

5.9

4.1

1.5

1.0

12.9

7.0

5.9

4.1

ns

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

RD to Q, Q; see Figure 9

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

1.5

1.0

5.0

3.5

3.0

2.5

12.9

7.0

5.9

4.1

1.5

1.0

12.9

7.0

5.9

4.1

ns

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

t_W

pulse width

CP HIGH or LOW;

see Figure 8

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

6.2

2.7

2.0

-

6.2

2.7

2.0

-

ns

-

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

1.3

-

SD and RD LOW;

see Figure 9

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

6.2

2.7

2.0

-

6.2

2.7

2.0

-

ns

-

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

1.6

-

74LVC1G74

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Product data sheet

Rev. 9 — 5 August 2010

9 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

Table 9.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.

Symbol Parameter

Conditions

−40 °C to +85 °C

−40 °C to +125 °C

Unit

Min

Typ^[1]

Max

Min

Max

t_rec

recovery time

set-up time

hold time

SD or RD; see Figure 9

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.9

1.4

-

1.9

1.4

-

ns

-

1.3

-

−3.0

-

1.3

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

D to CP; see Figure 8

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

+1.2

1.0

+1.2

1.0

t_su

2.9

1.7

1.3

1.1

-

2.9

1.7

1.3

1.1

-

ns

-

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

D to CP; see Figure 8

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

0.5

-

t_h

1.5

1.0

-

1.5

1.0

-

ns

-

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

CP; see Figure 8

0.6

-

f_max

maximum

frequency

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

80

175

200

-

80

175

200

-

MHz

pF

-

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

280

-

[3]

C_PD

power dissipation V_I= GND to V_CC

capacitance V_CC= 3.3 V

;

15

[1] Typical values are measured at T_amb= 25 °C and V_CC= 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.

[2] t_pdis the same as t_PLHand t_PHL.

[3] C_PDis used to determine the dynamic power dissipation (P_Din μW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

Σ(C_L× V_CC²× f_o) = sum of outputs.

74LVC1G74

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Product data sheet

Rev. 9 — 5 August 2010

10 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

12. Waveforms

t

W

V

I

V

CP input

M

GND

1/f

max

V

I

V

D input

M

GND

t

h

t

su

t

PLH

PHL

V

OH

V

Q output

M

V

OL

V

OH

V

M

V

OL

t

PHL

PLH

mnb141

Measurement points are given in Table 10.

The shaded areas indicate when the input is permitted to change for predictable output performance.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 8. The clock input (CP) to output (Q, Q) propagation delays, the clock pulse width, the D to CP set-up, the

CP to D hold times and the maximum frequency

Table 10. Measurement points

Supply voltage

V_CC

Input

Output

V_M

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

0.5 × V_CC

1.5 V

0.5 × V_CC

1.5 V

3.0 V to 3.6 V

4.5 V to 5.5 V

1.5 V

0.5 × V_CC

74LVC1G74

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Product data sheet

Rev. 9 — 5 August 2010

11 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

V

I

V

M

CP input

GND

t

rec

V

I

V

M

SD input

RD input

GND

t

W

V

I

V

M

GND

t

PHL

PLH

V

OH

Q output

V

M

V

OL

V

OH

M

V

OL

t

PLH

PHL

mnb142

Measurement points are given in Table 10.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 9. The set (SD) and reset (RD) input to output (Q, Q) propagation delays, the set and reset pulse widths and

the RD to CP recovery time

74LVC1G74

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Product data sheet

Rev. 9 — 5 August 2010

12 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

V

EXT

V

CC

R

L

V

O

I

G

DUT

R

C

R

T

L

mna616

Test data is given in Table 11.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to the output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig 10. Test circuit for measuring switching times

Table 11. Test data

Supply voltage

V_CC

Input

V_I

Load

C_L

V_EXT

t_r, t_f

R_L

t_PLH, t_PHL

open

t_PZH, t_PHZ

GND

t_PZL, t_PLZ

2V_CC

6 V

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

V_CC

2.7 V

V_CC

≤ 2.0 ns

≤ 2.5 ns

30 pF

50 pF

1 kΩ

500 Ω

open

GND

open

GND

3.0 V to 3.6 V

4.5 V to 5.5 V

open

GND

6 V

open

GND

2V_CC

74LVC1G74

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Product data sheet

Rev. 9 — 5 August 2010

13 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

13. Package outline

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm

SOT505-2

D

E

A

X

c

H

v

M

y

A

E

Z

5

8

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

detail X

1

4

e

w

M

b

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

A

b

c

D

E

e

H

E

L

p

UNIT

v

w

y

Z

θ

1

2

3

p

max.

0.15

0.00

0.95

0.75

0.38

0.22

0.18

0.08

3.1

2.9

3.1

2.9

4.1

3.9

0.47

0.33

0.70

0.35

8°

0°

mm

1.1

0.65

0.25

0.5

0.2

0.13

0.1

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-01-16

SOT505-2

- - -

Fig 11. Package outline SOT505-2 (TSSOP8)

74LVC1G74

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9 — 5 August 2010

14 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm

SOT765-1

D

E

A

X

c

y

H

v

M

A

E

Z

5

8

Q

A

2

A

1

(A )

3

pin 1 index

θ

L

p

L

detail X

1

4

e

w

M

b

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

A

b

c

D

E

e

H

L

p

Q

UNIT

v

w

y

Z

θ

1

2

3

p

E

max.

0.15

0.00

0.85

0.60

0.27

0.17

0.23

0.08

2.1

1.9

2.4

2.2

3.2

3.0

0.40

0.15

0.21

0.19

0.4

0.1

8°

0°

mm

1

0.5

0.12

0.4

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-06-07

SOT765-1

MO-187

Fig 12. Package outline SOT765-1 (VSSOP8)

74LVC1G74

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9 — 5 August 2010

15 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm

SOT833-1

b

1

2

3

4

4×

(2)

L

1

e

8

7

6

5

e

1

e

1

e

1

8×

A

(2)

A

1

D

E

terminal 1

index area

0

1

2 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

1

UNIT

b

D

E

e

1

L

1

max max

0.25

0.17

2.0

1.9

1.05

0.95

0.35 0.40

0.27 0.32

mm

0.5 0.04

0.6

0.5

Notes

1. Including plating thickness.

2. Can be visible in some manufacturing processes.

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

- - -

07-11-14

07-12-07

SOT833-1

- - -

MO-252

Fig 13. Package outline SOT833-1 (XSON8)

74LVC1G74

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Product data sheet

Rev. 9 — 5 August 2010

16 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

XSON8: extremely thin small outline package; no leads;

8 terminals; body 1.35 x 1 x 0.5 mm

SOT1089

E

terminal 1

index area

D

A

1

detail X

(2)

(4×)

e

L

(2)

(8×)

b

4

5

e

1

8

terminal 1

index area

L

1

X

0

0.5

1 mm

scale

Dimensions

Unit

(1)

A

1

b

D

E

e

1

L

1

max 0.5 0.04 0.20 1.40 1.05

0.35 0.40

0.15 1.35 1.00 0.55 0.35 0.30 0.35

0.12 1.30 0.95 0.27 0.32

mm nom

min

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

sot1089_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

10-04-09

10-04-12

SOT1089

MO-252

Fig 14. Package outline SOT1089 (XSON8)

74LVC1G74

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9 — 5 August 2010

17 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

XSON8U: plastic extremely thin small outline package; no leads;

8 terminals; UTLP based; body 3 x 2 x 0.5 mm

SOT996-2

D

B

A

E

A

1

detail X

terminal 1

index area

e

1

C

M

v

w

C A

C

B

b

e

L

1

y

1

y

C

1

4

L

2

L

8

5

X

0

1

2 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1

b

D

E

e

1

L

v

w

y

1

2

max

0.05 0.35

0.00 0.15

2.1

1.9

3.1

2.9

0.5

0.3

0.15

0.05

0.6

0.4

mm

0.5

1.5

0.1

0.05 0.05

0.1

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

- - -

JEDEC

JEITA

07-12-18

07-12-21

SOT996-2

- - -

Fig 15. Package outline SOT996-2 (XSON8U)

74LVC1G74

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9 — 5 August 2010

18 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

XQFN8U: plastic extremely thin quad flat package; no leads;

8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm

SOT902-1

D

B

A

terminal 1

index area

E

A

1

detail X

e

L

1

e

C

y

C

1

y

L

M

∅ v

∅ w

C A

C

B

4

5

6

7

3

2

metal area

not for soldering

e

1

b

e

1

terminal 1

index area

8

X

0

1

2 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1

b

D

E

e

1

L

v

w

y

1

max

0.05 0.25 1.65 1.65

0.00 0.15 1.55 1.55

0.35 0.15

0.25 0.05

mm

0.5

0.55

0.5

0.1

0.05 0.05 0.05

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

MO-255

JEITA

05-11-25

07-11-14

SOT902-1

- - -

Fig 16. Package outline SOT902-1 (XQFN8U)

74LVC1G74

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9 — 5 August 2010

19 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

XSON8: extremely thin small outline package; no leads;

8 terminals; body 1.2 x 1.0 x 0.35 mm

SOT1116

b

4

(2)

1

2

3

(4×)

L

1

e

8

7

6

5

e

1

e

1

e

1

(2)

(8×)

A

1

A

D

E

terminal 1

index area

0

0.5

scale

1 mm

Dimensions

Unit

(1)

A

1

b

D

E

e

1

L

1

max 0.35 0.04 0.20 1.25 1.05

0.35 0.40

0.15 1.20 1.00 0.55 0.3 0.30 0.35

0.12 1.15 0.95 0.27 0.32

mm nom

min

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

sot1116_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

10-04-02

10-04-07

SOT1116

Fig 17. Package outline SOT1116 (XSON8)

74LVC1G74

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9 — 5 August 2010

20 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

XSON8: extremely thin small outline package; no leads;

8 terminals; body 1.35 x 1.0 x 0.35 mm

SOT1203

b

4

(2)

(4×)

1

2

3

L

1

e

8

7

6

5

e

1

e

1

e

1

(2)

(8×)

A

1

A

D

E

terminal 1

index area

0

L

0.5

scale

1 mm

Dimensions

Unit

(1)

A

1

b

D

E

e

1

L

1

max 0.35 0.04 0.20 1.40 1.05

0.35 0.40

0.15 1.35 1.00 0.55 0.35 0.30 0.35

0.12 1.30 0.95 0.27 0.32

mm nom

min

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

sot1203_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

10-04-02

10-04-06

SOT1203

Fig 18. Package outline SOT1203 (XSON8)

74LVC1G74

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9 — 5 August 2010

21 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

14. Abbreviations

Table 12. Abbreviations

Acronym

CMOS

HBM

ESD

Description

Complementary Metal-Oxide Semiconductor

Human Body Model

ElectroStatic Discharge

Machine Model

MM

DUT

Device Under Test

TTL

Transistor-Transistor Logic

15. Revision history

Table 13. Revision history

Document ID

74LVC1G74 v.9

Modifications:

Release date

20100805

Data sheet status

Change notice

Supersedes

Product data sheet

-

74LVC1G74 v.8

• Added type number 74LVC1G74GN (SOT1116/XSON8 package).

• Added type number 74LVC1G74GS (SOT1203/XSON8 package).

74LVC1G74 v.8

74LVC1G74 v.7

74LVC1G74 v.6

74LVC1G74 v.5

74LVC1G74 v.4

74LVC1G74 v.3

74LVC1G74 v.2

74LVC1G74 v.1

20091203

20080626

20080219

20070809

20061207

20050201

20040909

20040202

Product data sheet

Product specification

-

74LVC1G74 v.7

74LVC1G74 v.6

74LVC1G74 v.5

74LVC1G74 v.4

74LVC1G74 v.3

74LVC1G74 v.2

74LVC1G74 v.1

-

74LVC1G74

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9 — 5 August 2010

22 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

suitable for use in medical, military, aircraft, space or life support equipment,

16.2 Definitions

nor in applications where failure or malfunction of an NXP Semiconductors

product can reasonably be expected to result in personal injury, death or

severe property or environmental damage. NXP Semiconductors accepts no

liability for inclusion and/or use of NXP Semiconductors products in such

equipment or applications and therefore such inclusion and/or use is at the

customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. The product is not designed, authorized or warranted to be

74LVC1G74

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9 — 5 August 2010

23 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

74LVC1G74

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9 — 5 August 2010

24 of 25

74LVC1G74

NXP Semiconductors

Single D-type flip-flop with set and reset; positive edge trigger

18. Contents

1

2

3

4

5

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7

Functional description . . . . . . . . . . . . . . . . . . . 5

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6

Recommended operating conditions. . . . . . . . 6

Static characteristics. . . . . . . . . . . . . . . . . . . . . 7

Dynamic characteristics . . . . . . . . . . . . . . . . . . 9

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 22

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22

8

9

10

11

12

13

14

15

16

Legal information. . . . . . . . . . . . . . . . . . . . . . . 23

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24

16.1

16.2

16.3

16.4

17

18

Contact information. . . . . . . . . . . . . . . . . . . . . 24

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 5 August 2010

Document identifier: 74LVC1G74

型号:	74LVC1G74GS
是否Rohs认证：	符合
生命周期：	Transferred
零件包装代码：	SON
包装说明：	1.35 X 1 MM, 0.35 MM HEIGHT, SOT1203, SON-8
针数：	8
Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01
风险等级：	5.57
系列：	LVC/LCX/Z
JESD-30 代码：	R-PDSO-N8
JESD-609代码：	e3
长度：	1.35 mm
逻辑集成电路类型：	D FLIP-FLOP
湿度敏感等级：	1
位数：	1
功能数量：	1
端子数量：	8
最高工作温度：	125 °C
最低工作温度：	-40 °C
输出极性：	COMPLEMENTARY
封装主体材料：	PLASTIC/EPOXY
封装代码：	VSON
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260
传播延迟（tpd）：	13.4 ns
认证状态：	Not Qualified
座面最大高度：	0.35 mm
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	1.65 V
标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES
技术：	CMOS
温度等级：	AUTOMOTIVE
端子面层：	TIN
端子形式：	NO LEAD
端子节距：	0.35 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
触发器类型：	POSITIVE EDGE
宽度：	1 mm
最小 fmax：	200 MHz
Base Number Matches：	1

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