74OL6010各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

HIGH-SPEED

LOGIC-TO-LOGIC OPTOCOUPLERS

TTL BUFFER

74OL6000

74OL6001

74OL6010

74OL6011

TTL INVERTER

CMOS BUFFER

CMOS INVERTER

LSTTL TO

PACKAGE

SYMBOL

BUFFER

6

1

INVERTER

1

DESCRIPTION

OPTOLOGIC™ is the ﬁrst family of truly logic compatible optically coupled logic interface gates.

The family consists of four device types offering LSTTL to TTL and LSTTL to CMOS interfacing. Each of these interfacing functions

is available as a buffer (A=B), or as an inverter (A=B).

The LSTTL input compatibility is provided by an input integrated circuit, with industry standard logic levels. This input ampliﬁer IC

switches a temperature compensated current source driving a high speed 850 nm AlGaAs LED emitter. This novel integration

scheme eliminates CTR degradation over time and temperature.

The emitter is optically coupled to an integrated photodetector/high-gain, high-speed output ampliﬁer IC. The superior 15kV/µS

common-mode noise rejection is ensured through the use of an optically transparent noise shield.

The TTL compatible output has a totem-pole with a fan-out of 10. The CMOS compatible output has an open collector Schottky-

clamped transistor that interfaces to any CMOS logic between 4.5 and 15 volts.The 74OL6010/11 may also by used to drive power

MOSFETS or transistors up to 15 volts.

The Optologic coupler family typically offers propagation of delays of 60 ns and can support 15 MBaud data communication.

The two input chips and the output chip are assembled in a 6-pin DIP high insulation voltage plastic package. It provides a with-

stand test voltage of 5300 VRMS (1 minute).

FEATURES

APPLICATIONS

•

Industry ﬁrst LSTTL to TTL and LSTTL to CMOS complete

logic-to-logic optocoupler

Incorporates LED drive circuitry — use as logic gate

Very high speed

•

Transmission line interface — receiver and driver

Excellent as bridged receiver in fast LAN highways

Bus interface

Logic family interface with ground loop noise elimination

High speed AC/DC voltage sensing

Driver for power semiconductor devices

Level shifting

•

Choice of buffer or inverter

Choice of TTL or CMOS compatible output up to 15 volts

Fan-out of 10 TTL loads, fan-in 1 LSTTL load

Internal noise shield — very high CMR of 15 kV/µS

UL recognized (File #E90700)

Replaces fast pulse transformers

Same noise immunity as LSTTL/TTL.

Page 1 of 15

3/19/03

HIGH-SPEED

LOGIC-TO-LOGIC OPTOCOUPLERS

TTL BUFFER

74OL6000

74OL6001

74OL6010

74OL6011

TTL INVERTER

CMOS BUFFER

CMOS INVERTER

LSTTL TO

Vcc

150 Ω TYP.

Vcc

R_L

22 kΩ TYP.

INPUT

OUTPUT

GND

LSTTL INPUT CIRCUIT

OUTPUT

GND

CMOS OUTPUT CIRCUIT

GND

TTL OUTPUT CIRCUIT

All Inputs

74OL6000/01 Output

74OL6010/11 Output

PIN CONFIGURATION

1-V

(Input V

)

6-V

(Output V

)

CCI

CC

CCO

CC

2-V (Data In)

5-V (Data Out)

O

IN

3-GND, (Input GND) 4-GND (Output GND)

O

DEVICE CONFIGURATION

Logic Compatibility

Part Number

Logic Function

Output Conﬁguration

Input

Output

74OL 6000

74OL 6001

74OL 6010

74OL 6011

LSTTL

TTL

BUFFER

INVERTER

BUFFER

TOTEM POLE

CMOS

OPEN COLLECTOR

INVERTER

Page 2 of 15

3/19/03

HIGH-SPEED

LOGIC-TO-LOGIC OPTOCOUPLERS

TTL BUFFER

74OL6000

74OL6001

74OL6010

74OL6011

TTL INVERTER

CMOS BUFFER

CMOS INVERTER

LSTTL TO

SCHEMATIC

74OL6000

74OL6001

74OL6010

74OL6011

NOISE

SHIELD

1

2

3

1

2

3

1

2

3

1

2

3

6

5

4

6

5

4

6

5

4

6

5

4

LSTLL to TTL Buffer

LSTLL to TTL Inverter

LSTLL to CMOS Buffer

LSTLL to CMOS Inverter

Page 3 of 15

3/19/03

HIGH-SPEED

LOGIC-TO-LOGIC OPTOCOUPLERS

TTL BUFFER

74OL6000

74OL6001

74OL6010

74OL6011

TTL INVERTER

CMOS BUFFER

CMOS INVERTER

LSTTL TO

ELECTRICAL CHARACTERISTICS (T = 0°C to 70°C Unless otherwise speciﬁed)

A

Test Conditions

Parameter

Symbol Min Typ* Max Units

Notes

74OL6000 74OL6001

74OL6000/01

TTL OUTPUT 74OL6000/01

Input Supply Voltage

V

4.5 5.0

2.0

5.5

V

1

CCI

Output Supply Voltage

High-Level Input Voltage

Low-Level Input Voltage

Input Clamp Voltage

V

CCO

V

IH

V

0.8

-1.2

40.0

V

IL

V

= 4.5 V, I = -18 mA

1

IK

CCI

I

High-Level Input Current

Low-Level Input Current

Input Supply Current (high)

Input Supply Current (low)

I

1.0

µA

= 5.5 V, V = 4.5 V

IH

CCI

I

-200.0 -400.0 µA

10.0 14.0 mA

V

= 5.5 V, V = 0.4 V

IL

CCI IL

I

V

= 5.5 V, V = V

CCIH

CCI IN IH

I

V

= 5.5 V, V = V

CCIL

CCI IN IL

V

= 4.5 V, V

= 4.5 V,

CCI

CCO

High-Level Output Voltage

Low-Level Output Voltage

High-Level Output Current

V

2.4 3.0

V

= 2.0 V

= 0.8V

V

IN

= 0.8 V

= 2.0V

1

OH

IN

I

= -400 mA

OH

= 4.5 V, V

= 4.5 V,

= 5.5 V,

CCO

0.6

0.5

I

= 16 mA

OL

V

0.3

V

OL

IN

= 4.5 V, V

CCO

I

= 4 mA

OL

= 4.5 V, V

CCO

I

-8.0 -10.0 mA

mA

V

= V

V

= V

IL

OH

IN

IH

IN

V

= 2.4 V

OH

= 4.5 V, V

CCO

Low-Level Output Current

Short-Circuit Output Current

Output Supply Current (high)

I

16.0

V

= 0.8 V

V

= 2.0V

1

OL

IN

V

= 0.6 V

OL

I

-5.0 -25.0 -40.0 mA

V

= V

V

= V

= 5.5 V, V

CCO

OS

IN

IH

IN

IL

V

= 5.5 V, V = V

,

CCI

O

OH

I

9.0

8.0

15.0 mA

12.0 mA

V

CCOH

V

= 5.5 V

CCO

V

= 5.5 V, V = V

,

CCI

O

OL

Output Supply Current (low)

I

V

= V

V

= V

1

CCOL

IN

IL

IN

IH

V

= 5.5 V

CCO

*All typical values are at T =25°C

A

SWITCHING CHARACTERISTCS (T = 25°C Unless otherwise speciﬁed)

A

Parameter

Symbol Min Typ Max Units

Test Conditions

Fig. Notes

TTL OUTPUT 74OL6000/01

Propagation Delay Time For Output Low Level

Propagation Delay Time For Output High Level

Output Rise Time For Output High Level

Output Fall Time For Output Low Level

t

60

70

45

5

100

ns

n

15, 17

1

PHL

t

V

= 5 V, V

CCO

= 5 V 15, 17

15, 17

PLH

CCI

t

r

t

ns

15, 17

f

Page 4 of 15

3/19/03

HIGH-SPEED

LOGIC-TO-LOGIC OPTOCOUPLERS

TTL BUFFER

74OL6000

74OL6001

74OL6010

74OL6011

TTL INVERTER

CMOS BUFFER

CMOS INVERTER

LSTTL TO

ELECTRICAL CHARACTERISTICS (T = 0°C to 70°C Unless otherwise speciﬁed)

A

Test Conditions

Parameter

Symbol Min Typ* Max Units

Notes

74OL6010 74OL6011

74OL6010/11

CMOS OUTPUT 74OL6010/11

Input Supply Voltage

V

4.5

2.0

5.0

5.5

V

1

1,3

1

CCI

Output Supply Voltage

High-Level Input Voltage

Low-Level Input Voltage

Input Clamp Voltage

V

15.0

CCO

V

IH

V

0.8

-1.2

40.0

V

1

IL

V

= 4.5 V, I = -18 mA

1

IK

CCI

I

High-Level Input Current

Low-Level Input Current

Input Supply Current (high)

Input Supply Current (low)

I

1.0

µA

= 5.5 V, V = 4.5 V

IH

I

-200.0 -400.0 µA

10.0 14.0 mA

V

= 5.5 V, V = -0.4 V

IL

I

V

= 5.5 V, V = V

CCIH

CCI IN IH

I

V

= 5.5 V, V = V

CCIL

CCI IN IL

V

= 4.5 V, V

= 4.5 V,

CCI

CCO

0.6

I

= 16 mA

OL

Low-Level Output Voltage

V

0.4

V

= 0.8V V = 2.0V

1

OL

IN

= 4.5 V, V

= 4.5 V,

CCI

CCO

0.5

I

= 4 mA

OL

V

= 4.5 V, V = 15 V,

OH

CCI

V

High-Level Output Current

Low-Level Output Current

I

1.0 100.0 µA

mA

V

= V

V

= V

IL

1

OH

IN

IH

IN

= 4.5 - 15 V

CCO

V

= 4.5 V, V = 0.6V,

OL

CCI

V

I

16.0

V

= 0.8 V V = 2.0V

IN

OL

IN

= 4.5 - 15 V

CCO

V

= 5.5 V, V = V

,

CCI

O

OH

9.0

11.0 18.0

8.0 12.0

11.0 18.0

12.0

V

= 4.5 V

CCO

Output Supply Current (high)

Output Supply Current (low)

I

mA

V

= V

V

= V

1

CCOH

IN

IH

IN

IL

V

= 5.5 V, V = V

,

CCI

O

OL

V

= 15 V

CCO

V

= 5.5 V, V = V

O

V

= 4.5 V

CCO

I

V

= V

V

= V

CCOL

IN

IL

IN

IH

V

= 5.5 V, V = V

O

V

= 15 V

CCO

*All typical values are at T =25°C

A

SWITCHING CHARACTERISTCS (T = 25°C Unless otherwise speciﬁed)

A

Parameter

Symbol Min Typ Max Units

Test Conditions

Fig.

Notes

TTL OUTPUT 74OL6010/11

Propagation Delay Time For Output Low Level

Propagation Delay Time For Output High Level

Output Rise Time For Output High Level

Output Fail Time For Output Low Level

t

60 120

ns

15, 18

1

PHL

V

= 5 V,

CCI

t

100 180

PLH

V

= 5 V, R = 470 Ω

CCO

L

t

50

5

r

t

f

Page 5 of 15

3/19/03

HIGH-SPEED

LOGIC-TO-LOGIC OPTOCOUPLERS

TTL BUFFER

74OL6000

74OL6001

74OL6010

74OL6011

TTL INVERTER

CMOS BUFFER

CMOS INVERTER

LSTTL TO

ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise speciﬁed)

A

Parameter

Symbol

Device

Value

Units

TOTAL DEVICE

Storage Temperature

Operating Temperature

Lead Solder Temperature

Power Dissipation

EMITTER

T

All

-55 to +125

0 to +70

°C

STG

T

OPR

T

260 for 10 sec

350

°C

SOL

P

mW

D

Input Supply Voltage

Input Voltage

V

All

7

V

CCI

V

IN

DETECTOR

Average Output Current

I

All

40

7

mA

V

O (avg)

74OL6000/01

74OL6010/11

74OL6000/01

74OL6010/11

Output Supply Voltage

Output Voltage

V

CCO

18

7

V

O

18

ELECTRICAL CHARACERISTICS (T = 0°C to 70°C Unless otherwise speciﬁed)

A

Parameter

Symbol Min

Typ

Max Units

Test Conditions

Fig. Notes

74OL6000/01/10/11

Common Mode Transient Immunity at

Logic High Level Output

CM

5000 15000

-5000 -15000

V/µS

16, 19

H

V

= 5 V, V

= 5 V,

CCI

CCO

V

= 50 Vp-p

Common Mode Transient Immunity at

Logic Low Level Output

CM

L

Common Mode Coupling Capacitance

Capacitance (input-output)

C

0.005

0.7

pF

CM

C

VI-O = 0, f = 1 MHz

T = 25°C,

2

I-O

A

Withstand Insulation Test Voltage

Insulation Resistance

V

5300

10

VRMS

ISO

t = 1 min, I ≤ 1mA

I-O

R

Ω

V

= 500 VDC

ISO

I-O

Page 6 of 15

3/19/03

HIGH-SPEED

LOGIC-TO-LOGIC OPTOCOUPLERS

TTL BUFFER

74OL6000

74OL6001

74OL6010

74OL6011

TTL INVERTER

CMOS BUFFER

CMOS INVERTER

LSTTL TO

Figure 1. Input Current vs. Ambient Temperature

100

Figure 2. Input Supply Current vs. Ambient Temperature

15

14

13

I_IH

0

12

I_CCIH- 74OL6000-6010

I_CCIL- 74OL6001-6011

11

V_CCI= 5.5V

V_IH= 4.5V

V_IL= 0.4V

-100

-200

-300

10

9

I_IL

8

I_CCIH- 74OL6001-6011

I_CCIL- 74OL6000-6010

7

6

V_CCI= 5.5V

5

-40

-20

0

20

40

60

80

100

-40

-20

0

20

40

60

80

100

T_A- AMBIENT TEMPERATURE (˚C)

Figure 3. Output Supply Current vs. Ambient Temperature

Figure 4. Output Current vs. Ambient Temperature

60

15

50

I_OL

12

40

V_CCI= 4.5V

V_CCO= 4.5V

30

I_CCOH

9

V_OL= 0.6V

V_OH= 2.4V

I_CCOL

I_CCOH

I_CCOL

20

10

0

6

I_CCOH

I_CCOL

74OL6010/6011

V_CCI= 5.5V

V_CCO= 15V

I_OH

-10

-20

-30

3

0

(74OL6000/6001)

74OL6010/6011

V_CCI= 5.5V

74OL6000/6001

V_CCI= 5.5V

V_CCO= 5.5V

-40

-20

0

20

40

60

80 100

-40

-20

0

20

40

60

80

100

T_A- AMBIENT TEMPERATURE (˚C)

Figure 5. High-Level Output Voltage vs. Ambient Temperature

Figure 6. Low-Level Output Voltage vs. Ambient Temperature

0.5

5

V_CCI= 4.5V

V_CCO= 4.5V

I_OH= -400µA

4

3

2

0.4

@ I_OL

= 16mA

= 4mA

0.3

0.2

0.1

@ I_OL

1

0

V

CCI

= 4.5V

^CCO= 4.5V

-40

-20

0

20

40

60

80

100

-40

-20

0

20

40

60

80

100

T_A- AMBIENT TEMPERATURE (˚C)

Page 7 of 15

3/19/03

HIGH-SPEED

LOGIC-TO-LOGIC OPTOCOUPLERS

TTL BUFFER

74OL6000

74OL6001

74OL6010

74OL6011

TTL INVERTER

CMOS BUFFER

CMOS INVERTER

LSTTL TO

Figure 7. 74OL6010/11 Leakage Current vs. Ambient Temperature

Figure 8. 74OL6000/01 Switching Times vs. Ambient Temperature

5

V_CCI= 5.0V

V_CCO= 5.0V

P.W = 200ns

V_CCIN= 4.5V

_CCO= 15V

V_OUT= 15V

4

3

2

1

V

PERIOD = 1µS

200

t_PLH

t_PHL

t_r

100

50

10

5

t_f

0

-40

1

-40

-20

0

20

40

60

80

100

-20

0

20

40

60

80 100

T

_A- AMBIENT TEMPERATURE (˚C)

T

_A- AMBIENT TEMPERATURE (˚C)

Figure 9. 74OL6010/11 Switching Times vs. Ambient Temperature

Figure 10. Common Mode Rejection vs. Common Mode Voltage

11

V_CCO= 5V

V_CCO= 15V

V_CCI= 5V

R_L= 470Ω

10

9

P.W = 200ns

PERIOD = 1µS

t_PLH

t_r

t_PHL

t_r

200

100

50

8

V_CCO= 5V

V_OH= 2V

V_OL= 0.8V

7

6

5

R_L= 470Ω (74OL6010/6011)

4

3

10

5

t_f

2

1

-40

-20

0

20

40

60

80 100

0

500

1000

15000

2000

2500

T

_A- AMBIENT TEMPERATURE (˚C)

V_CM- COMMON MODE TRANSIENT

Figure 11. Supply Current vs. Supply Voltage

Figure 12. Power Dissipation vs. Ambient Temperature

MAXIMUM ALLOWABLE POWER

12

DISSIPATION @ TA = 25˚C

I_CCO

I_CC

10

8

300

200

100

0

@TA = 55˚C

6

V_CCO

RANGE FOR 74OL6000/6001

V

^CCI= 5.5V

@T

A

= 70˚C

= 85˚C

4

2

@T

V^CCI= 4.5V

0

4

5

6

7

8

9

10 11 12 13 14 15

4

5

6

7

8

9

10 11 12 13 14 15

V

_CCO- OUTPUT SUPPLY VOLTAGE (V)

V_CC- SUPPLY VOLTAGE (V)

Page 8 of 15

3/19/03

HIGH-SPEED

LOGIC-TO-LOGIC OPTOCOUPLERS

TTL BUFFER

74OL6000

74OL6001

74OL6010

74OL6011

TTL INVERTER

CMOS BUFFER

CMOS INVERTER

LSTTL TO

Figure 13. Input Threshold Voltage vs. Ambient Temperature

Figure 14. Input Current vs. Input Voltage

1.6

100

1.5

0

1.4

1.3

1.2

-100

-200

1.1

V_CCI= 5.0V

V_CCO= 5.0V

1.0

0.0

V_CCI= 4.5V

-300

0

1

2

3

4

5

6

-40

-20

0

20

40

60

80

100

T_A- AMBIENT TEMPERATURE (°C)

V_IN- INPUT VOLTAGE (V)

Figure 15. Switching Time Test Circuit

Figure 16. Common Mode Rejection Test Circuit

V_CCO

+5 V

V_CCI

+5 V

V_CCO

+5 V

1

2

3

6

5

6

1

2

3

6

5

4

.1µF

1kΩ

.1µF

470Ω (74OL6010/11)

.1µF

470Ω (74OL6010/11)

H/L

L/H

PULSE

GEN

PW =200ns

PERIOD = 1

tr = 5ns

Zo = 50Ω

µS

V_O

C_L*

*CL = 15pF STRAY CAPACITANCE

INCLUDING PROBE

+

-

V

CM

Page 9 of 15

3/19/03

HIGH-SPEED

LOGIC-TO-LOGIC OPTOCOUPLERS

TTL BUFFER

74OL6000

74OL6001

74OL6010

74OL6011

TTL INVERTER

CMOS BUFFER

CMOS INVERTER

LSTTL TO

Figure 18. Switching Parameters 74OL6010/11

Figure 17. 74OL6000/01 Switching Times vs. Ambient Temperature

INPUT, V_I

3.2V

INPUT, V_I3.2V

1.3V

t_PHL

t_PLH

t_PHL

t_PLH

90%

50%

10%

90%

1.3V

OUTPUT, V_O

(74OL6000)

OUTPUT, V_O

(74OL6010)

10%

t_r

t_f

t_r

t_f

t_r

90%

50%

90%

OUTPUT, V_O

(74OL6011)

OUTPUT, V_O

(74OL6001)

1.3V

10%

t_PHL

t_PLH

t_PHL

t_PLH

Figure 20. Suggested PCB Lay-Out

Figure 19. Common Mode Rejection Waveforms

50V

INPUT

V

CC

BUS

INPUT

GND

BUS

OUTPUT

GND

BUS

OUTPUT

V

CC

BUS

dV_CM

dt

V_CM

t_r

V_CM

0V

=

V_OH

CM_H

1

2

6

5

V_O= 2.0V (MIN.)

V_O= 0.8V (MAX.)

DATA

IN

DATA

OUT

.1µF

3

4

V_OL

CM_L

NOTE

1. The VCCO and VCCI supply voltages to the device must each be bypassed by a 0.1µF capacitor or larger. This can be either a

ceramic or solid tantalum capacitor with good high frequency characteristics. Its purpose is to stabilize the operation of the high-

gain ampliﬁers. Failure to provide the bypass will impair the DC and switching properties. The total lead length between capaci-

tor and optocoupler should not exceed 1.5mm. See Fig. 20.

2. Device considered a two-terminal device. Pins 1, 2 and 3 shorted together, and Pins 4, 5 and 6 shorted together.

3. For example, assuming a V

of 5.0V, and an ambient temperature of 70°C, the maximum allowable V

is 12.1V.

CCI

CCO

Page 10 of 15

3/19/03

HIGH-SPEED

LOGIC-TO-LOGIC OPTOCOUPLERS

TTL BUFFER

74OL6000

74OL6001

74OL6010

74OL6011

TTL INVERTER

CMOS BUFFER

CMOS INVERTER

LSTTL TO

Package Dimensions (Through Hole)

Package Dimensions (Surface Mount)

PIN 1

ID.

0.350 (8.89)

0.330 (8.38)

PIN 1

ID.

3

2

1

0.270 (6.86)

0.240 (6.10)

0.270 (6.86)

0.240 (6.10)

0.350 (8.89)

0.330 (8.38)

4

5

6

0.070 (1.78)

0.045 (1.14)

0.300 (7.62)

TYP

0.070 (1.78)

0.045 (1.14)

0.200 (5.08)

0.115 (2.92)

0.200 (5.08)

0.165 (4.18)

0.016 (0.41)

0.008 (0.20)

0.020 (0.51)

MIN

0.020 (0.51)

MIN

0.016 (0.40) MIN

0.154 (3.90)

0.100 (2.54)

0.022 (0.56)

0.016 (0.41)

0.100 (2.54)

TYP

0.315 (8.00)

MIN

0.016 (0.40)

0.008 (0.20)

0.405 (10.30)

MAX

0.300 (7.62)

TYP

0.022 (0.56)

0.016 (0.41)

0° to 15°

Lead Coplanarity : 0.004 (0.10) MAX

0.100 (2.54)

TYP

Package Dimensions (0.4” Lead Spacing)

Recommended Pad Layout for

Surface Mount Leadform

PIN 1

ID.

0.070 (1.78)

0.270 (6.86)

0.240 (6.10)

0.060 (1.52)

0.350 (8.89)

0.330 (8.38)

0.415 (10.54)

0.100 (2.54)

0.295 (7.49)

0.070 (1.78)

0.045 (1.14)

0.030 (0.76)

0.200 (5.08)

0.135 (3.43)

0.154 (3.90)

0.100 (2.54)

0.016 (0.40)

0.008 (0.20)

0.004 (0.10)

MIN

0° to 15°

0.022 (0.56)

0.016 (0.41)

0.400 (10.16)

TYP

0.100 (2.54) TYP

NOTE

All dimensions are in inches (millimeters)

Page 11 of 15

3/19/03

HIGH-SPEED

LOGIC-TO-LOGIC OPTOCOUPLERS

TTL BUFFER

74OL6000

74OL6001

74OL6010

74OL6011

TTL INVERTER

CMOS BUFFER

CMOS INVERTER

LSTTL TO

ORDERING INFORMATION

Option

Order Entry Identiﬁer

Description

S

.S

.SD

Surface Mount Lead Bend

Surface Mount; Tape and Reel

0.4" Lead Spacing

SD

W

.W

300

.300

.300W

.3S

VDE 0884

300W

3S

VDE 0884, 0.4" Lead Spacing

VDE 0884, Surface Mount

VDE 0884, Surface Mount, Tape and Reel

3SD

.3SD

MARKING INFORMATION

1

2

74OL6000

V XX YY K

6

5

3

4

Deﬁnitions

1

2

Fairchild logo

Device number

VDE mark (Note: Only appears on parts ordered with VDE

option – See order entry table)

3

4

5

6

Two digit year code, e.g., ‘03’

Two digit work week ranging from ‘01’ to ‘53’

Assembly package code

Page 12 of 15

3/19/03

HIGH-SPEED

LOGIC-TO-LOGIC OPTOCOUPLERS

TTL BUFFER

74OL6000

74OL6001

74OL6010

74OL6011

TTL INVERTER

CMOS BUFFER

CMOS INVERTER

LSTTL TO

Reﬂow Proﬁle (Black Package, No Sufﬁx)

300

250

215°C, 10–30 s

225 C peak

200

150

Time above 183°C, 60–150 sec

Ramp up = 3C/sec

100

50

0

• Peak reflow temperature: 225°C (package surface temperature)

• Time of temperature higher than 183°C for 60–150 seconds

• One time soldering reflow is recommended

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

Time (Minute)

Page 13 of 15

3/19/03

HIGH-SPEED

LOGIC-TO-LOGIC OPTOCOUPLERS

TTL BUFFER

74OL6000

74OL6001

74OL6010

74OL6011

TTL INVERTER

CMOS BUFFER

CMOS INVERTER

LSTTL TO

APPLICATION

Local area data communication systems can greately improve their noise immunity by including OPOTOLOGIC gates in the

design.

The Optologic input ampliﬁer offers the feature of very high input impedance that permits their use as bridged line receivers. The

system show above illustrates an optically isolated transmitter and multidrop receiver system. The network uses a 74OL6000 and

buffer (Figure D) to isolate the transmitter and drive the 75Ω coax cable. This application uses a 1000 ft. aerial suspension 75Ω

CATV coax cable with data taps at 250 ft. intervals. The 74OL6001s function as bridged receivers, and as many as 30 receivers

could be placed along the line with minimal signal degradation. The communication cable is terminated with a single 75Ω load at

the far end of the line.

Signal quality "Eye Pattern" is shown in Figures A, B and C with a 10MBaud NRZ Psuedo-Random Sequence (PRS).Traces 1-3 in

Figure A describes the transmitter section. Traces 4-7 in Figure B show the output of the four Optologic bridged terminations.

Traces 8-11 in Figure C illustrate "Eye Pattern" as seen at the output of a 74LS04 logic gate. The data quality is well preserved in

that only a 30% Eye closure is seen at the receiver located 1000 ft. from the transmitter.

The data communication system is completely optically isolated from all of the terminal equipments. Power for the transmitter

(V

) and receiver (V ) is taken from an isolated power supply and distributed through a drain or messenger wire.

CCO

CCI

Figure A

Figure B

Figure C

HORIZONTAL = 20 ns/DIV 42-11

VERTICAL = 2 V/DIV

HORIZONTAL = 20 ns/DIV 42-12, 02

VERTICAL = 2 V/DIV

HORIZONTAL = 20 ns/DIV 42-13/03

VERTICAL = 2 V/DIV

1000 FT.

3

1

2

PRSG

100 ns BIT

INTERVAL

75

Ω

0.1 µ

F

TERMINAION

10 Ω

1.1 KΩ

250 FT.

BUFFER

74

6000

OL

2N4252

100 µ

F

74

6001

74

6001

OL

74

6001

OL

74

6001

OL

4

8

5

9

6

7

2N4252

1.1 KΩ

LS04

10

11

2N2222

1 KΩ

ALL DIODES

1N6263

Figure D Buffer

Page 14 of 15

3/19/03

HIGH-SPEED

LOGIC-TO-LOGIC OPTOCOUPLERS

TTL BUFFER

74OL6000

74OL6001

74OL6010

74OL6011

TTL INVERTER

CMOS BUFFER

CMOS INVERTER

LSTTL TO

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO

ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME

ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;

NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES

OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR

CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body, or

(b) support or sustain life, and (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in a significant injury of the user.

2. A critical component in any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

Page 15 of 15

3/19/03

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