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产品型号74VHC161284MTDX的概述

74VHC161284MTDX的概述 74VHC161284MTDX是一款高性能的64位宽并行输入并行输出的数据寄存器，广泛应用于数据存储和数据传输领域。该芯片属于VHC系列，具备快速的操作速度和低功耗的特点。74VHC系列采用的是先进的CMOS工艺，相较于传统的TTL逻辑，提供了更高的噪声容忍度和更低的静态功耗。该芯片的主要功能包括数据的并行输入和并行输出、时序控制及寄存器的动态控制等。由于其具有很高的灵活性和适应性，因此可以广泛用于多种数字电路设计中，如计数器、数据缓冲器、状态机等。 74VHC161284MTDX的详细参数 74VHC161284MTDX的详细参数如下： - 电源电压：2V至5.5V - 工作温度范围：-40°C至+125°C - 输入高电平阈值：VIH = 0.7VCC (最低为2.5V时为1.5V) - 输入低电平阈值：VIL = 0.3VCC (最低为2....

产品型号74VHC161284MTDX的Datasheet PDF文件预览

February 1998

Revised June 2005

74VHC161284

IEEE 1284 Transceiver

General Description

Features

■ Supports IEEE 1284 Level 1 and Level 2 signaling

standards for bidirectional parallel communications

between personal computers and printing peripherals

The VHC161284 contains eight bidirectional data buffers

and eleven control/status buffers to implement

a full

IEEE 1284 compliant interface. The device supports the

IEEE 1284 standard and is intended to be used in

Extended Capabilities Port mode (ECP). The pinout allows

for easy connection from the Peripheral (A-side) to the

Host (cable side).

■ Replaces the function of two (2) 74ACT1284 devices

■ All inputs have hysteresis to provide noise margin

■ B and Y output resistance optimized to drive external

cable

Outputs on the cable side can be configured to be either

open drain or high drive ( 14 mA). The pull-up and pull-

down series termination resistance of these outputs on the

cable side is optimized to drive an external cable. In addi-

tion, all inputs (except HLH) and outputs on the cable side

contain internal pull-up resistors connected to the V_CCsup-

■ B and Y outputs in high impedance mode during power

down

■ Inputs and outputs on cable side have internal pull-up

resistors

■ Flow-through pin configuration allows easy interface

ply to provide proper termination and pull-ups for open

drain mode.

between the Peripheral and Host

Outputs on the Peripheral side are standard LOW-drive

CMOS outputs. The DIR input controls data flow on the A₁–

A₈/B₁–B₈transceiver pins.

Ordering Code:

Ordering Number Package Number

Package Description

74VHC161284MEA

74VHC161284MTD

MS48A

MTD48

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagram

DS500098

www.fairchildsemi.com

Pin Descriptions

Truth Table

Pin Names

Description

Inputs

Outputs

HIGH Drive Enable Input (Active HIGH)

Direction Control Input

Inputs or Outputs

DIR

B₁–B₈Data to A₁–A₈, and

A₉–A₁₃Data to Y₉–Y₁₃(Note 1)

C₁₄–C₁₇Data to A₁₄–A₁₇

PLH Open Drain Mode

A₁–A₈

B₁–B₈

A₉–A₁₃

Y₉–Y₁₃

A₁₄–A₁₇

Inputs or Outputs

Inputs

Outputs

B₁–B ₈Data to A₁–A₈, and

A₉–A₁₃Data to Y₉–Y₁₃

Outputs

₁₄–C₁₇

Inputs

C₁₄–C₁₇Data to A₁₄–A₁₇

A₁–A₈Data to B₁–B₈(Note 2)

A₉–A₁₃Data to Y₉–Y₁₃(Note 1)

PLH_IN

PLH

Peripheral Logic HIGH Input

Peripheral Logic HIGH Output

Host Logic HIGH Input

Host Logic HIGH Output

HLH_IN

HLH

C₁₄–C₁₇Data to A₁₄–A₁₇

PLH Open Drain Mode

A₁–A₈Data to B₁–B₈

A₉–A₁₃Data to Y₉–Y₁₃

C₁₄–C₁₇Data to A₁₄–A₁₇

Note 1: Y –Y Open Drain Outputs

Note 2: B –B Open Drain Outputs

Logic Diagram

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Absolute Maximum Ratings(Note 3)

Recommended Operating

Conditions

Supply Voltage

V_CC

0.5V to 7.0V

Supply Voltage

Input Voltage (V_I) (Note 4)

A₁–A ₁₃, PLH_IN, DIR, HD

B₁–B₈, C₁₄–C₁₇, HLH_IN

V_CC

4.5V to 5.5V

0V to V_CC

0.5V to V_CC0.5V

0.5V to 5.5V (DC)

2.0V to 7.0V *

DC Input Voltage (V_I)

Open Drain Voltage (V_O)

Operating Temperature (T_A)

0V to 5.5V

40 C to 85 C

*40 ns Transient

Output Voltage (V_O)

A₁–A₈, A₁₄–A₁₇, HLH

B₁–B ₈, Y₉–Y₁₃, PLH

0.5V to V_CC0.5V

0.5V to 5.5V (DC)

2.0V to 7.0V*

*40 ns Transient

DC Output Current (I_O)

A₁–A₈, HLH

25 mA

50 mA

84 mA

50 mA

B₁–B₈, Y₉–Y₁₃

PLH (Output LOW)

PLH (Output HIGH)

Input Diode Current (I_IK) (Note 4)

DIR, HD, A₉–A₁₃

PLH, HLH, C₁₄–C₁₇

Output Diode Current (I_OK

A₁–A₈, A₁₄–A₁₇, HLH

B₁–B₈, Y₉–Y₁₃, PLH

DC Continuous V_CCor

Ground Current

20 mA

)

50 mA

Note 3: Absolute Maximum continuos ratings are those values beyond

which damage to the device may occur. Exposure to these indicated may

adversely affect device reliability. Functional operation under absolute max-

imum rated conditions is not implied.

200 mA

Note 4: Either voltage limit or current limit is sufficient to protect inputs.

Storage Temperature

ESD (HBM) Last Passing

Voltage

65 C to 150 C

2000V

DC Electrical Characteristics

40 C to 85 C

Symbol

Parameter

Units

Conditions

(V)

3.0

Guaranteed Limits

Input Clamp Diode Voltage

1.2

18 mA

Minimum HIGH Level Input Voltage

Maximum LOW Level Input Voltage

Minimum Input Hysteresis

A , PLH , DIR, HD

4.5 5.5

5.0

0.7 V

2.0

2.3

2.6

HLH

A , PLH , DIR, HD

0.3 V

0.8

1.6

0.4

0.8

0.3

4.4

3.8

3.73

4.45

HLH

A , PLH , DIR, HD

–V

HLH

5.0

Minimum HIGH Level Output Voltage

A , HLH

4.5

50 A

4.5

8 mA

B , Y

4.5

14 mA

PLH

4.5

500 A

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DC Electrical Characteristics (Continued)

40 C to 85 C

Symbol

Parameter

Units

Conditions

(V)

4.5

5.0

5.5

0.0

5.5

Guaranteed Limits

Maximum LOW Level Output Voltage

A , HLH

0.1

0.44

0.77

0.7

8 mA

B , Y

14 mA

84 mA

PLH

Maximum Output Impedance

Minimum Output Impedance

Maximum Pull-Up Resistance

Minimum Pull-Up Resistance

Maximum Input Current in HIGH State

B –B , Y –Y

(Note 5)(Note 6)

B –B , Y –Y

B –B , Y –Y , C –C

1650

1150

1.0

B –B , Y –Y , C –C

A –A , PLH , HD, DIR, HLH

5.5V

0.0V

5.5V

0.0V

–C

100

1.0

Maximum Input Current in LOW State

A –A , PLH , HD, DIR, HLH

–C

5.0

Maximum Output Disable Current

(HIGH)

A —A

OZH

OZL

B –B

100

Maximum Output Disable Current

(LOW)

A —A

B –B

5.0

Power Down Output Leakage

Power Down Input Leakage

B –B , Y –Y , PLH

100

250

5.5V

OFF

–C , HLH

Power Down Leakage to V

Maximum Supply Current

(Note 7)

or GND

Note 5: Output impedance is measured with the output active LOW and active HIGH (HD HIGH).

Note 6: This parameter is guaranteed but not tested, characterized only.

Note 7: Power-down leakage to V

is tested by simultaneously forcing all pins on the cable-side (B –B , Y –Y , PLH, C –C and HLH to 5.5V and

1 8 9 13 14 17 IN

measuring the resulting I

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AC Electrical Characteristics

40 C to 85 C

4.5V 5.5V

Figure

Number

Symbol

Parameter

Units

Min

2.0

Max

30.0

6.0

A –A to B –B

Figure 1

Figure 2

Figure 3

Figure 1

Figure 2

Figure 3

(Note 9)

Figure 1

Figure 2

Figure 3

PHL

A –A to B –B

PLH

PHL

PLH

PHL

PLH

PHL

PLH

SKEW

PHL

PLH

PHL

PLH

PHZ

PLZ

PZH

PZL

PHZ

PLZ

pEN

B –B to A –A

A –A to Y –Y

–C to A –A

17 14

–C to A –A

17 14

LH-LH or HL-HL

PLH to PLH

2.0

30.0

18.0

25.0

PLH to PLH

HLH to HLH

Output Disable Time

DIR to A –A

Figure 7

Figure 8

Figure 9

Figure 2

Output Enable Time

DIR to A –A

Output Disable Time

DIR to B –B

Output Enable Time

HD to B –B , Y –Y

2.0

28.0

Output Disable Time

HD to B –B , Y –Y

pDis

28.0

20.0

–t

Output Enable-Output Disable

Output Slew Rate

pEn pDis

SLEW

PLH

B –B , Y –Y

0.05

0.40

120

Figure 5

Figure 4

Figure 6

(Note 10)

V/ns

PHL

t , t

and t

RISE FALL

B –B , Y –Y (Note 8)

Note 8: Open Drain

Note 9: t is measured for common edge output transitions and compares the measured propagation delay for a given path type.

SKEW

(i) A –A to B –B , A –Y to Y –Y

(ii) B –B to A –A

(iii) C –C to A –A

Note 10: This parameter is guaranteed but not tested, characterized only.

Capacitance (Note 11)

Symbol

Parameter

Input Capacitance

I/O Pin Capacitance

Typ

Units

Conditions

0.0V (HD, DIR, A —A , C —C , PLH and HLH )

3.3V

I/O

Note 11: Capacitance is measured at frequency 1 MHz.

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AC Loading and Waveforms

Pulse Generator for all pulses: Rate 1.0 MHz; Z_O50 ; t_f2.5 ns, t_r2.5 ns.

FIGURE 1. Part A to B and A to Y Propagation Delay Load and Waveforms

FIGURE 2. Port A to B and a to Y Output Waveforms

FIGURE 3. Port B to A, C to A and HLHin to HLH Propagation Delay Waveforms

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AC Loading and Waveforms (Continued)

FIGURE 4. Port A to B and A to Y HL Slew Test Load and Waveforms

FIGURE 5. Part A to b and A to Y LH Slew Test Load and Waveforms

Output Rise Time, Open Drain

Output Fall Time, Open Drain

FIGURE 6. t_RISEand t_FALLTest Load and Waveforms for Open Drain Outputs

A₁–A₈to B₁–B₈, A₉–A₁₃to Y₉–Y₁₃

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AC Loading and Waveforms (Continued)

FIGURE 7. t_PHZand t_PLZTest Load and Waveforms, DIR to A₁–A₈

FIGURE 8. t_PZHand t_PZLTest Load and Waveforms, DIR to A₁–A₈

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AC Loading and Waveforms (Continued)

FIGURE 9. t_PHZand t_PLZTest Load and Waveforms, DIR to B₁–B₈

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Physical Dimensions inches (millimeters) unless otherwise noted

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

Package Number MS48A

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD48

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

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74VHC161284MTDX产品参数

型号:	74VHC161284MTDX
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	TSSOP
包装说明：	6.10 MM, MO-153, TSSOP-48
针数：	48
Reach Compliance Code：	unknown
风险等级：	5.19
差分输出：	NO
驱动器位数：	14
输入特性：	SCHMITT TRIGGER
接口集成电路类型：	LINE TRANSCEIVER
接口标准：	IEEE 1284
JESD-30 代码：	R-PDSO-G48
JESD-609代码：	e4
长度：	12.5 mm
湿度敏感等级：	2
功能数量：	13
端子数量：	48
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
认证状态：	COMMERCIAL
最大接收延迟：	30 ns
接收器位数：	13
座面最大高度：	1.2 mm
最大供电电压：	5.5 V
最小供电电压：	4.5 V
标称供电电压：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	NICKEL PALLADIUM GOLD
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
最大传输延迟：	30 ns
宽度：	6.1 mm
Base Number Matches：	1

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