7801201RB应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244

SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244

OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SDLS144B – APRIL 1985 – REVISED FEBRUARY 2002

SN54LS’, SN54S’ . . . J OR W PACKAGE

3-State Outputs Drive Bus Lines or Buffer

Memory Address Registers

SN74LS240, SN74LS244 . . . DB, DW, N, OR NS PACKAGE

SN74LS241 . . . DW, N, OR NS PACKAGE

SN74S’ . . . DW OR N PACKAGE

PNP Inputs Reduce DC Loading

(TOP VIEW)

Hysteresis at Inputs Improves Noise

Margins

1G

1A1

2Y4

1A2

2Y3

1A3

2Y2

1A4

2Y1

GND

V

CC

2G/2G

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

†

description

1Y1

2A4

1Y2

2A3

These octal buffers and line drivers are designed

specifically to improve both the performance and

density of three-state memory address drivers,

clock drivers, and bus-oriented receivers and

transmitters. The designer has a choice of

selected combinations of inverting and

noninverting outputs, symmetrical, active-low

output-control (G) inputs, and complementary

output-control (G and G) inputs. These devices

featurehighfan-out, improvedfan-in, and400-mV

noise margin. The SN74LS’ and SN74S’ devices

can be used to drive terminated lines down to

133 Ω.

1Y3

13 2A2

12 1Y4

11

2A1

†

2G for ’LS241 and ’S241 or 2G for all other drivers.

SN54LS’, SN54S’ . . . FK PACKAGE

(TOP VIEW)

3

2

1

20 19

18

1Y1

2A4

1Y2

2A3

1Y3

1A2

2Y3

1A3

2Y2

1A4

4

5

6

7

8

17

16

15

14

9 10 11 12 13

†

2G for ’LS241 and ’S241 or 2G for all other drivers.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244

SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244

OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SDLS144B – APRIL 1985 – REVISED FEBRUARY 2002

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

T

A

SN74LS240N

SN74LS241N

SN74LS244N

SN74S240N

SN74S241N

SN74S244N

SN74LS241N

SN74LS244N

SN74S240N

SN74S241N

SN74S244N

PDIP – N

Tube

SN74LS240DW

SN74LS240DWR

SN74LS241DW

SN74LS241DWR

SN74LS244DW

SN74LS244DWR

SN74S240DW

LS240

LS241

LS244

S240

Tape and reel

Tube

Tape and reel

Tube

0°C to 70°C

Tape and reel

Tube

SOIC – DW

Tape and reel

Tube

SN74S240DWR

SN74S241DW

S241

Tape and reel

Tube

SN74S241DWR

SN74S244DW

S244

Tape and reel

SN74S244DWR

SN74LS240NSR

SN74LS241NSR

SN74LS244NSR

SN74LS240DBR

SN74LS244DBR

74LS240

74LS241

74LS244

LS240

SOP – NS

Tube

SSOP – DB

Tape and reel

LS244

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244

SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244

OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SDLS144B – APRIL 1985 – REVISED FEBRUARY 2002

ORDERING INFORMATION (CONTINUED)

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

T

A

SN54LS240J

SNJ54LS240J

SN54LS241J

SNJ54LS241J

SN54LS244J

SNJ54LS244J

SN54S240J

SNJ54LS240J

SN54LS241J

SNJ54LS241J

SN54LS244J

SNJ54LS244J

SN54S240J

CDIP – J

Tube

SNJ54S240J

SN54S241J

SNJ54S240J

SN54S241J

SNJ54S241J

SN54S244J

SNJ54S241J

SN54S244J

SNJ54S244J

SNJ54LS240W

SNJ54LS241W

SNJ54LS244W

SNJ54S240W

SNJ54S241W

SNJ54S244W

SNJ54LS240FK

SNJ54LS241FK

SNJ54LS244FK

SNJ54S240FK

SNJ54S241FK

SNJ54S244FK

SNJ54S244J

SNJ54LS240W

SNJ54LS241W

SNJ54LS244W

SNJ54S240W

SNJ54S241W

SNJ54S244W

SNJ54LS240FK

SNJ54LS241FK

SNJ54LS244FK

SNJ54S240FK

SNJ54S241FK

SNJ54S244FK

–55°C to 125°C

CFP – W

Tube

LCCC – FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244

SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244

OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SDLS144B – APRIL 1985 – REVISED FEBRUARY 2002

schematics of inputs and outputs

’S240, ’S241, ’S244

EQUIVALENT OF EACH INPUT

’LS240, ’LS241, ’LS244

EQUIVALENT OF EACH INPUT

V

CC

V

CC

Req

9 kΩ NOM

Input

G and G inputs: R = 2 kΩ NOM

eq

A inputs: R = 2.8 kΩ NOM

eq

TYPICAL OF ALL OUTPUTS

V

CC

R

Output

GND

’LS240. ’LS241, ’LS244: R = 50 Ω NOM

’S240, ‘S241, S244: R = 25 Ω NOM

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244

SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244

OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SDLS144B – APRIL 1985 – REVISED FEBRUARY 2002

logic diagram

’LS240, ’S240

’LS241, ’S241

1

1G

1

1G

18

16

14

12

2

4

1Y1

1Y2

1A1

1A2

1A3

18

16

14

12

2

4

6

8

1Y1

1Y2

1A1

1A2

1A3

6

1Y3

1Y4

1Y3

1Y4

8

1A4

2G

1A4

2G

19

9

7

5

3

9

11

13

15

17

11

13

15

17

2Y1

2A1

2A2

2A3

2A4

2Y1

2Y2

2A1

2A2

2A3

2A4

7

5

3

2Y2

2Y3

2Y4

2Y3

2Y4

’LS244, ’S244

1

1G

18

2

4

6

8

1Y1

1A1

1A2

1A3

16

14

12

1Y2

1Y3

1Y4

1A4

19

2G

9

7

5

3

11

13

15

17

2Y1

2A1

2A2

2A3

2A4

2Y2

2Y3

2Y4

Pin numbers shown are for DB, DW, J, N, NS, and W packages.

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244

SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244

OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SDLS144B – APRIL 1985 – REVISED FEBRUARY 2002

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

CC

Input voltage, V : ’LS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

I

’S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W

JA

DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W

N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W

NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Voltage values are with respect to network ground terminal.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions

SN54LS’

MIN NOM

SN74LS’

UNIT

MAX

MIN NOM

MAX

V

Supply voltage (see Note 1)

High-level input voltage

Low-level input voltage

4.5

2

5

5.5

4.75

2

5

5.25

V

CC

IH

0.7

–12

12

0.8

–15

24

V

IL

I

High-level output current

Low-level output current

Operating free-air temperature

mA

°C

OH

OL

I

T

A

–55

125

0

70

NOTE 1: Voltage values are with respect to network ground terminal.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244

SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244

OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SDLS144B – APRIL 1985 – REVISED FEBRUARY 2002

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54LS’

SN74LS’

†

PARAMETER

UNIT

TEST CONDITIONS

‡

MIN TYP

MAX

MIN TYP

MAX

V

= MIN,

= MIN

I = –18 mA

–1.5

V

IK

Hysteresis

(V – V

CC

I

0.2

2.4

2

0.4

3.4

0.2

2.4

2

0.4

3.4

CC

)

T–

T+

= MIN,

= –3 mA

V

= 2 V,

V

= MAX,

= 0.5 V,

CC

OH

IH

IL

I

V

OH

OL

V

= MIN,

= MAX

V

IL

CC

OH

IH

I

= 12 mA

= 24 mA

0.4

0.5

V

= MIN,

= MAX

V

IH

= 2 V,

OL

CC

IL

V

OL

V

= MAX,

= MAX

CC

IL

I

V

= 2 V,

V

= 2.7 V

= 0.4 V

20

µA

OZH

IH

O

V

= MAX,

= MAX

CC

IL

V

–20

OZL

IH

I

V

= MAX,

V = 7 V

0.1

20

0.1

20

mA

µA

I

CC

I

V = 2.7 V

I

IH

IL

V

IL

= 0.4 V

–0.2

–225

27

–0.2

–225

27

mA

§

–40

OS

Outputs high

Outputs low

All

17

26

27

29

32

17

26

27

29

32

’LS240

44

V

CC

= MAX,

I

’LS241, ’LS244

’LS240

46

mA

CC

Output open

50

Outputs disabled

’LS241, ’LS244

54

†

‡

§

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

All typical values are at V = 5 V, T = 25°C.

Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

CC

A

switching characteristics, V

= 5 V, T = 25°C (see Figure 1)

CC

A

’LS240

TYP

9

’LS241, ’LS244

PARAMETER

TEST CONDITIONS

MIN

UNIT

ns

MAX

14

MIN

TYP

12

MAX

t

18

30

23

20

25

PLH

PHL

PZL

PZH

PLZ

PHZ

R

= 667 Ω,

C

= 45 pF

= 5 pF

L

12

18

12

20

30

20

ns

15

23

15

10

20

10

ns

C

L

15

25

15

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244

SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244

OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SDLS144B – APRIL 1985 – REVISED FEBRUARY 2002

recommended operating conditions

SN54S’

SN74S’

UNIT

MIN NOM

MAX

MIN NOM

MAX

V

Supply voltage (see Note 1)

High-level input voltage

4.5

2

5

5.5

4.75

2

5

5.25

V

CC

IH

Low-level input voltage

0.8

–12

48

0.8

–15

64

V

IL

I

High-level output current

mA

kΩ

°C

OH

OL

I

Low-level output current

External resistance between any input and V

or ground

40

CC

T

A

Operating free-air temperature (see Note 3)

–55

125

0

70

NOTES: 1. Voltage values are with respect to network ground terminal.

3. An SN54S241J operating at free-air temperature above 116°C requires a heat sink that provides a thermal resistance from case

to free air, R , of not more that 40°C/W.

CA

θ

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54S’

SN74S’

†

PARAMETER

UNIT

TEST CONDITIONS

‡

MIN TYP

MAX

MIN TYP

MAX

V

= MIN,

= MIN

I = –18 mA

–1.2

V

IK

Hysteresis

(V – V

CC

I

0.2

0.4

3.4

0.2

2.7

2.4

2

0.4

3.4

CC

)

T–

T+

= MIN

= –1 mA

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

= 2 V,

V

= 0.8 V,

= 0.5 V,

= 0.8 V,

CC

OH

IL

I

V

= MIN,

= –3 mA

V

CC

OH

2.4

2

V

OH

V

I

V

= MIN,

= MAX

CC

OH

I

V

= MIN,

= MAX

CC

V

OL

0.55

50

0.55

50

V

I

OL

V

= MAX,

= 0.8 V

CC

IL

I

V

= 2.4 V

= 0.5 V

µA

OZH

O

V

= MAX,

= 0.8 V

CC

IL

–50

OZL

O

I

V

= MAX,

V = 5.5 V

1

50

1

50

mA

µA

I

CC

I

V

V = 2.7 V

I

IH

Any A

Any G

–400

–2

–400

–2

µA

I

V

= MAX,

= MAX

V = 0.5 V

I

IL

CC

mA

§

I

V

–50

–225

123

147

145

170

145

170

–50

–225

135

160

150

180

150

180

OS

’S240

80

95

80

95

Outputs high

Outputs low

’S241,’S244

’S240

100

120

100

120

100

120

100

120

V

CC

= MAX,

I

mA

CC

Output open

’S241, ’S244

’S240

Outputs disabled

’S241, ’S244

†

‡

§

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

All typical values are at V = 5 V, T = 25°C.

Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

CC

A

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244

SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244

OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SDLS144B – APRIL 1985 – REVISED FEBRUARY 2002

switching characteristics, V

= 5 V, T = 25°C (see Figure 2)

CC

A

’S240

TYP

4.5

10

’S241, ’S244

PARAMETER

TEST CONDITIONS

MIN

UNIT

ns

MAX

7

MIN

TYP

6

MAX

9

t

PLH

PHL

PZL

PZH

PLZ

PHZ

R

= 90 Ω,

C

= 50 pF

= 5 pF

L

7

6

9

15

10

15

9

10

8

15

12

15

9

ns

6.5

10

6

ns

C

L

6

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244

SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244

OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SDLS144B – APRIL 1985 – REVISED FEBRUARY 2002

PARAMETER MEASUREMENT INFORMATION

SERIES 54LS/74LS DEVICES

V

CC

Test

Point

R

L

Test

Point

S1

V

CC

From Output

Under Test

V

CC

(see Note B)

R

L

C

L

(see Note A)

From Output

Under Test

5 kΩ

R

L

(see Note B)

From Output

Under Test

C

Test

Point

C

L

(see Note A)

L

(see Note A)

S2

LOAD CIRCUIT

FOR 2-STATE TOTEM-POLE OUTPUTS

FOR OPEN-COLLECTOR OUTPUTS

FOR 3-STATE OUTPUTS

3 V

High-Level

Timing

Input

1.3 V

Pulse

0 V

t

h

w

t

su

3 V

0 V

Low-Level

Pulse

Data

Input

1.3 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Output

3 V

0 V

Control

(low-level

enabling)

1.3 V

3 V

0 V

Input

1.3 V

t

PLZ

PZL

t

PHL

PLH

Waveform 1

(see Notes C

and D)

≈1.5 V

In-Phase

Output

(see Note D)

1.3 V

V

OH

V

OL

+ 0.3 V

1.3 V

V

OL

t

PHZ

OL

t

PZH

t

PLH

PHL

V

OH

Waveform 2

(see Notes C

and D)

V

OH

– 0.3 V

Out-of-Phase

Output

(see Note D)

V

OH

1.3 V

≈1.5 V

OL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A.

C

includes probe and jig capacitance.

L

B. All diodes are 1N3064 or equivalent.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. S1 and S2 are closed for t

, t

, and t

; S1 is open and S2 is closed for t

PLZ PZH

; S1 is closed and S2 is open for t .

PLH PHL PHZ

PZL

E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.

F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω, t ≤ 15 ns, t ≤ 6 ns.

O

r

f

G. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244

SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244

OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SDLS144B – APRIL 1985 – REVISED FEBRUARY 2002

PARAMETER MEASUREMENT INFORMATION

SERIES 54S/74S DEVICES

V

CC

Test

Point

R

L

Test

Point

S1

V

CC

From Output

Under Test

V

CC

(see Note B)

R

L

C

L

(see Note A)

From Output

Under Test

1 kΩ

R

L

(see Note B)

From Output

Under Test

C

Test

Point

C

L

(see Note A)

L

(see Note A)

S2

LOAD CIRCUIT

FOR 2-STATE TOTEM-POLE OUTPUTS

FOR OPEN-COLLECTOR OUTPUTS

FOR 3-STATE OUTPUTS

3 V

High-Level

Timing

Input

1.5 V

Pulse

0 V

t

h

w

t

su

3 V

0 V

Low-Level

Pulse

Data

Input

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

3 V

0 V

Output

Control

(low-level

enabling)

1.5 V

3 V

0 V

Input

1.5 V

t

PLZ

PZL

t

PHL

PLH

Waveform 1

(see Notes C

and D)

≈1.5 V

In-Phase

1.5 V

V

OH

Output

(see Note D)

V

OL

+ 0.5 V

1.5 V

V

OL

V

OL

t

PZH

PHZ

t

PLH

PHL

V

OH

Waveform 2

(see Notes C

and D)

V

OH

– 0.5 V

Out-of-Phase

Output

V

OH

1.5 V

≈1.5 V

(see Note D)

OL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A.

C

includes probe and jig capacitance.

L

B. All diodes are 1N3064 or equivalent.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. S1 and S2 are closed for t

, t

, and t

; S1 is open and S2 is closed for t

PLZ PZH

; S1 is closed and S2 is open for t .

PZL

PLH PHL PHZ

E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω; t and t ≤ 7 ns for Series

O

r

f

54/74 devices and t and t ≤ 2.5 ns for Series 54S/74S devices.

r

f

F. The outputs are measured one at a time with one input transition per measurement.

Figure 2. Load Circuits and Voltage Waveforms

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244

SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244

OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SDLS144B – APRIL 1985 – REVISED FEBRUARY 2002

APPLICATION INFORMATION

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

28-Feb-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

CDIP

CFP

Drawing

5962-7801201VRA

5962-7801201VSA

7705701RA

ACTIVE

J

W

J

20

1

25

None

Call TI

Level-NC-NC-NC

CDIP

CFP

7705701SA

W

FK

J

78012012A

LCCC

CDIP

CFP

7801201RA

7801201SA

W

FK

J

JM38510/32401B2A

JM38510/32401BRA

JM38510/32401BSA

JM38510/32402B2A

JM38510/32402BRA

JM38510/32402BSA

JM38510/32403B2A

JM38510/32403BRA

JM38510/32403BSA

JM38510/32403SRA

JM38510/32403SSA

SN54LS240J

LCCC

CDIP

CFP

W

FK

J

LCCC

CDIP

CFP

W

FK

J

LCCC

CDIP

CFP

W

J

CDIP

CFP

W

J

CDIP

SOIC

SN54LS241J

J

SN54LS244J

J

SN54S240J

J

SN54S241J

J

SN54S244J

J

SN74LS240DW

DW

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

SN74LS240DWR

ACTIVE

SOIC

DW

20

2000

20

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

SN74LS240J

SN74LS240N

OBSOLETE

ACTIVE

CDIP

PDIP

J

20

None

Call TI

N

Pb-Free

(RoHS)

CU NIPDAU Level-NC-NC-NC

SN74LS240N3

OBSOLETE

ACTIVE

PDIP

SO

N

20

None

Call TI

SN74LS240NSR

NS

2000

25

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

SN74LS241DW

ACTIVE

SOIC

DW

20

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

SN74LS241DWR

2000

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

SN74LS241J

SN74LS241N

OBSOLETE

ACTIVE

CDIP

PDIP

J

20

None

Call TI

N

20

Pb-Free

(RoHS)

CU NIPDAU Level-NC-NC-NC

SN74LS241N3

OBSOLETE

ACTIVE

PDIP

SO

N

20

None

Call TI

SN74LS241NSR

NS

2000

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

28-Feb-2005

Orderable Device

SN74LS244DBR

SN74LS244DW

SN74LS244DWR

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SSOP

DB

20

2000

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

SOIC

DW

25

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

2000

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

SN74LS244J

SN74LS244N

OBSOLETE

ACTIVE

CDIP

PDIP

J

20

None

Call TI

N

20

Pb-Free

(RoHS)

CU NIPDAU Level-NC-NC-NC

SN74LS244N3

OBSOLETE

ACTIVE

PDIP

SO

N

20

None

Call TI

SN74LS244NSR

NS

2000

25

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

SN74S240DW

SN74S240DWR

SN74S240N

ACTIVE

SOIC

PDIP

DW

N

20

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

2000

20

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

Pb-Free

(RoHS)

CU NIPDAU Level-NC-NC-NC

SN74S240N3

SN74S241DW

OBSOLETE

ACTIVE

PDIP

SOIC

N

20

None

Call TI

DW

25

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

SN74S241DWR

ACTIVE

SOIC

DW

20

2000

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

SN74S241J

SN74S241N

OBSOLETE

ACTIVE

CDIP

PDIP

J

20

None

Call TI

N

20

Pb-Free

(RoHS)

CU NIPDAU Level-NC-NC-NC

SN74S241N3

SN74S244DW

OBSOLETE

ACTIVE

PDIP

SOIC

N

20

None

Call TI

DW

25

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

SN74S244DWR

ACTIVE

SOIC

DW

20

2000

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

SN74S244J

SN74S244N

OBSOLETE

ACTIVE

CDIP

PDIP

J

20

None

Call TI

N

20

Pb-Free

(RoHS)

CU NIPDAU Level-NC-NC-NC

SN74S244N3

SNJ54LS240FK

SNJ54LS240J

SNJ54LS240W

SNJ54LS241FK

SNJ54LS241J

SNJ54LS241W

SNJ54LS244FK

SNJ54LS244J

SNJ54LS244W

SNJ54S240FK

SNJ54S240J

OBSOLETE

ACTIVE

PDIP

LCCC

CDIP

CFP

N

FK

J

20

None

Call TI

1

Level-NC-NC-NC

W

FK

J

LCCC

CDIP

CFP

W

FK

J

LCCC

CDIP

CFP

W

FK

J

LCCC

CDIP

CFP

SNJ54S240W

SNJ54S241FK

W

FK

LCCC

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

28-Feb-2005

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

CDIP

CFP

Drawing

SNJ54S241J

SNJ54S241W

SNJ54S244FK

SNJ54S244J

SNJ54S244W

ACTIVE

J

W

FK

J

20

1

None

Call TI

Level-NC-NC-NC

LCCC

CDIP

CFP

W

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,

including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 3

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process

in which TI products or services are used. Information published by TI regarding third-party products or services

does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.

Use of such information may require a license from a third party under the patents or other intellectual property

of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction

of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for

such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

product or service voids all express and any implied warranties for the associated TI product or service and

is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

型号:	7801201SA
生命周期：	Obsolete
IHS 制造商：	SIGNETICS CORP
包装说明：	DFP,
Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01
风险等级：	5.77
系列：	LS
JESD-30 代码：	R-GDFP-F20
逻辑集成电路类型：	BUS DRIVER
位数：	4
功能数量：	2
端口数量：	2
端子数量：	20
最高工作温度：	125 °C
最低工作温度：	-55 °C
输出特性：	3-STATE
输出极性：	INVERTED
封装主体材料：	CERAMIC, GLASS-SEALED
封装代码：	DFP
封装形状：	RECTANGULAR
封装形式：	FLATPACK
传播延迟（tpd）：	35 ns
筛选级别：	MIL-STD-883
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	TTL
温度等级：	MILITARY
端子形式：	FLAT
端子位置：	DUAL
Base Number Matches：	1

电子百科

产品导航

产品型号7801201SA的Datasheet PDF文件预览

7801201RB相关产品

7801201RB相关文章

IC37:专业IC行业平台