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产品型号78P7200-IH的概述

芯片78P7200-IH的概述及详细参数一、概述 78P7200-IH是一款低功耗、高性能的线性稳压器，属于78系列稳压器中的一种典型代表。此芯片广泛应用于各种电子设备中，通过提供稳定的输出电压，为数字电路和模拟电路工作提供所需的电源。同时，它的内部结构设计合理，具备较强的负载与线压调节能力，广泛应用于适应多种工作环境的电子产品。该芯片的主要优势是低待机电流和宽工作温度范围，使之在不同环境和应用条件下依然保持优异性能。78P7200-IH可被广泛应用于消费类电子产品、通信设备及各类嵌入式系统中。二、详细参数 78P7200-IH在参数上表现出众，以下是其关键参数的详细介绍： 1. 输入电源电压范围：此芯片支持的输入电压范围为输入电压（Vin）在 7V至 15V 之间。 2. 输出电压：输出电压（Vout）为 5V，具有很好的稳定性与调节能力。 3. 最大输出电流：其最大输出电流...

产品型号78P7200-IH的Datasheet PDF文件预览

78P7200

DS-3/E3/STS-1 Line Interface

With Receive Equalizer

March 1998

DESCRIPTION

FEATURES

The 78P7200 is a line interface transceiver IC

intended for STS-1 (51.84 Mbit/s), DS-3 (44.736

Mbit/s) and E3 (34.368 Mbit/s) applications. The

receiver has a very wide dynamic range and is

designed to accept either HDB3 or B3ZS-encoded

Alternate-Mark Inversion (AMI) inputs; it provides

CMOS logic level clock, positive data, negative data

and low-level signal detector outputs. An on-chip

equalizer improves the intersymbol interference

tolerance on the receive path. The transmitter

converts CMOS logic level clock, positive data and

negative data input signals into AMI pulses of the

appropriate shape for transmission. A line buildout

(LBO) equalizer may be selected to shape the

outgoing pulses for shorter line lengths. The

78P7200 requires a single 5 volt supply and is

available in a surface mount package.

•

Single chip transmit and receive interface for

STS-1 (51.84 Mbit/s), E3 (34.368 Mbit/s) or DS-3

(44.736 Mbit/s) applications

•

On-chip Receive Equalizer

Unique clock recovery circuit, requires no

crystals, tuned components or external clock

•

Selectable transmit line buildout (LBO) to

accommodate shorter line lengths

Compliant with ANSI T1.102-1993, Bellcore TR-

NWT-000499 and GR-253-CORE, ITU-T G.703

and G.823_1991

Low-level input signal indication

Available in a 28 PLCC surface mount package

-40°C to +85°C operating range

•

Pin-compatible replacement for 78P236,

The 78P7200 works in either rate of STS-1, DS-3 or

E3 by simple external components modification.

78P2361 and 78P2362

BLOCK DIAGRAM

RVcc

CPD

RLF2 RLF1

CLF1

RVcc

Low-Level Signal

Detection

Clock Recovery

RFO

RCLK

DVcc

LIN+

LIN-

RPOS

RNEG

Signal

Acquisition

Data

Detection

Eq.

INPUT

DGND

TVcc

Output

Driver,

Line

Pulse

Shaper

Pulse

Generator

TCLK

LOUT+

LOUT-

TPOS

TNEG

OUTPUT

Buildout

LBO

78P7200

DS-3/E3/STS-1 Line Interface

With Receive Equalizer

The output of the variable gain amplifier is compared

to a threshold value, which is a fixed percentage of

the signal peak. In this way, even though the input

signal amplitude may fall below the minimum value

that can be regulated by the variable gain circuit, the

proper detection threshold is maintained.

FUNCTIONAL DESCRIPTION

The 78P7200 is a single chip line interface IC

designed to work with either a 51.84 Mbit/s STS-1,

44.736 Mbit/s DS-3 or 34.368 Mbit/s E3 signal. The

receiver recovers clock, positive data and negative

data from an Alternate Mark Inversion (AMI) signal.

The input signal should be B3ZS or HDB3 coded.

Outputs of the data comparators are connected to

the clock recovery circuits. The clock recovery

system employs a unique phase locked loop which

has an auxiliary frequency-sensitive acquisition loop

which becomes active only when cycle-slipping

occurs between the received signal rate and the

internal oscillator.

The transmitter accepts CMOS level logical clock,

positive data and negative data and converts them

to the AMI signal to drive a 75Ω coaxial cable.

Programmable internal Line Buildout (LBO) circuitry

eliminates the need for external LBO networks.

When the option pins are properly selected, the

shape of the transmitted signal through any cable

length of 0 to 450 feet complies with the published

templates of ANSI T1.102, ITU-T G.703, Bellcore

TR-NWT-000499 and GR-253-CORE. The 78P7200

is designed to work with a B3ZS or HDB3 coded

signal. The B3ZS or HDB3 encoding and decoding

functions are normally included in the framer ICs or

can easily be implemented in a PAL.

This system permits the loop to independently lock

to the frequency and phase of the incoming data

stream without the need for high precision and/or

adjustable oscillator or tuned circuits.

The frequency characteristic for the phase locked

loop is established by external filter components,

RLF1, RLF2 and CLF1. The values of these

components are specified such that the bandwidth of

the phase locked loop is greater than 200 kHz.

RECEIVER

The receiver input is normally transformer-coupled to

the AMI signal. The inputs to the IC are internally

referenced to RVCC. Since the input impedance of

the 78P7200 is high, the AMI line must be

terminated in 75Ω. The input signal to the 78P7200

must be limited to a maximum of three consecutive

zeros using a coding scheme such as B3ZS or

HDB3.

The jitter tolerance of the 78P7200 exceeds the

requirements of TR-NWT-000499 for Category II

equipment for DS-3 rate and exceeds the

requirements of ITU-T G.823 for E3 rate. The jitter

transfer function is maximally flat so the IC doesn't

add any significant jitter to the system.

Figure 2 shows the recovered clock (RCLK), positive

data (RPOS) and negative data (RNEG) signals

timing. The data is valid on the rising edge of the

clock. The minimum setup and hold times allow easy

interface to framer circuits. These signals are

CMOS-level outputs.

The AMI signal first enters a fixed equalizer which is

designed to overcome the intersymbol interference

caused by long cable lengths and crosstalk. This

fixed equalizer is optimized for DS-3 application and

its effect should be compensated by an external filter

circuit similar to Figure 1, for all square shaped

signals such as DS3-high or 34 Mbit/s E3. For all

new designs, the addition of the filter for DS3 and

STS-1 as well as E3 rate allows the circuit to work

with sharp pulses such as DS3-high. The signal is

then input to a variable gain differential amplifier

whose output is maintained at a constant voltage

level regardless of the input voltage level. The gain

of this amplifier is adjusted by detecting the peak of

the signal and comparing it to a fixed reference.

Should the input signal fall below a minimum value,

the LOWSIG pin goes active low. A time delay is

provided before this output is active so that transient

interruptions do not cause false indications. This

signal should be used as one of many indications to

the cable disconnect; the framer device should count

the number of zeros to declare the loss of signal.

The RPOS and RNEG signals generate random

data following a silence period. The framer device

should ignore RPOS and RNEG data if the LOWSIG

pin is active low.

78P7200

DS-3/E3/STS-1 Line Interface

With Receive Equalizer

TRANSMITTER

The 78P7200 incorporates

selectable Line

Buildout (LBO) pulse shaper in the transmitter path.

For STS-1 and DS-3 applications, the LBO pin

should be set HIGH if the cable is shorter than 225

feet and set LOW for longer cable lengths. For E3

application, LBO pin should be set LOW regardless

of cable length.

The transmitter accepts CMOS logic level clock

(TCLK), positive data (TPOS) and negative data

(TNEG) signals and generates high current drive

pulses on the LOUT+ and LOUT- pins. When

properly connected to a center tapped transformer,

an AMI pulse is generated which can drive a 75Ω

coaxial cable.

The OPT! pin is set HIGH for DS-3 and STS-1

operation. The OPT! pin should be set LOW for E3

applications.

Figure 3 shows the timing for the transmitter logic

signals. The output pulse width is internally set and

is not sensitive to input clock (TCLK) pulse width.

The OPT@ pin should be set HIGH for normal

operation. By setting the OPT@ pin to LOW it disables

the transmitter drivers and reduces the power

consumption of the circuit by approximately 125 mW.

When a recommended transformer is used and

option pins are properly set, the transmitted pulse

shape at the end of a 75Ω terminated cable of 0 to

450 feet will fit the template for DSX3 pulse

published in ANSI T1.102-1993, Bellcore

TR-NWT-000499 documents.

Recommended settings for OPT! and LBO pins

OPT!

SPEED

DS3/STS1

CABLE

< 225'

> 225'

ALL

LBO

LOW

For 51.84 Mbit/s STS-1 application the transmitted

pulse for a short cable meets the requirements of

Bellcore GR-253-CORE. For 34 Mbit/s E3

application, the transmitted pulse for a short cable

meets the requirements of ITU-T G.703 when both

LBO and OPT! pins are set LOW.

LOW

78P7200

DS-3/E3/STS-1 Line Interface

With Receive Equalizer

78P7200

DS-3/E3/STS-1 Line Interface

With Receive Equalizer

PIN DESCRIPTION

RECEIVER

NAME

TYPE

DESCRIPTION

LIN+, LIN-

RPOS

RNEG

RCLK

LOWSIG

Differential inputs, transformer-coupled from coax cable.

Unipolar receiver output, active as result of positive pulse at inputs.

Unipolar receiver output, active as result of negative pulse at inputs.

Recovered Clock from line data.

Low signal logic output indicating that input signal is less than threshold value.

TRANSMITTER

TPOS

TNEG

TCLK

LOUT+

LOUT-

LBO

Unipolar transmitter data input, active high.

Transmitter clock input, active high.

Output to transformer for positive data pulses.

Output to transformer for negative data pulses.

Transmitter line buildout control. Set low for all E3 or for DS-3/STS-1 cable of 225'

or longer. Set high for short DS-3/ STS-1 cable.

OPT!

OPT@

Transmit option 1. Set high for DS-3/STS-1 and set low for E3.

Transmit option 2. Disables output driver and reduces output bias current when

low. Set high for normal transmit operation.

EXTERNAL COMPONENT CONNECTION

RFO

Resistor connected to RGND adjusts the center frequency of receiver phase

locked loop oscillator and the transmitter pulse width and amplitude.

LF1, LF2

CPD

Resistor-capacitor loop filter network to establish bandwidth of phase locked loop.

Capacitor to RVcc that is connected to peak detector node to reduce signal-

dependent ripple on that node.

POWER

TVcc

RVcc

DVcc

TGND

RGND

DGND

NCR

5V power supply for transmit circuits.

5V power supply for receive circuits.

5V power supply for receive logic circuits.

Ground return for transmit circuits.

Ground return for receive circuits.

Ground return for receive logic circuits.

No connect, Tie to Receiver Ground (RGND).

No connect, Tie to Transmitter Ground (TGND).

No connect, Tie to Digital Ground.

NCT

NCD

78P7200

DS-3/E3/STS-1 Line Interface

With Receive Equalizer

ELECTRICAL SPECIFICATIONS

(TA = -40°C to 85°C, Vcc = 5V ±5%, unless otherwise noted.) Currents flowing into the chip are positive. Current

maximums are currents with the largest absolute value. Operation above absolute maximum ratings may

permanently damage the device.

ABSOLUTE MAXIMUM RATINGS

PARAMETER

RATING

Positive 5V supply: TVcc, RVcc, DVcc

Storage Temperature

Soldering Temperature (10 sec.)

Ambient Operating Temperature, TA

Pin Ratings: LOUT+, LOUT-

-65 to 150°C

260 °C

-40 to +85°C

Vcc -2 to Vcc +2V

-0.3 to Vcc +0.3V

LIN+, LIN-, TPOS, TNEG, TCLK, LBO, RFO, LF2, LF1,

OPT!, OPT@ Pins

RPOS, RNEG, RCLK, LOWSIG Pins

-0.3 to Vcc +0.3V or +12 mA

SUPPLY CURRENTS AND POWER

PARAMETER

CONDITIONS

MIN

NOM

MAX

UNIT

Supply Current

ICC

Outputs unloaded, normal

operation, transmit and receive

all 1's pattern

155

190

Power Dissipation

Outputs unloaded, TA = 85°C

0.93

EXTERNAL COMPONENTS (Common to STS-1/DS3/E3, nominal value)

Loop filter resistor

Loop filter capacitor

Peak detector capacitor

Input Filter

RLF1

RLF2

CLF1

CPD

R1, R2

1% tolerance

10%

6.04

100

0.22

0.022

kΩ

µF

Ω

1000

µF

µH

20% (See Note)

0.01

0.47

6.8

1:2

Input Filter

Tranformer Turns Ratio

Receiver Termination Res

T1, T2

RTR

422

Ω

Note: Optional capacitor to reduce common mode noise.

78P7200

DS-3/E3/STS-1 Line Interface

With Receive Equalizer

EXTERNAL COMPONENTS (Dependent on speed, nominal Value)

STS-1

4.53

DS-3

5.23

6.81

Loop center frequency resistor RFO 1% tolerance

Transmit termination capacitor CTT 5% (Note 2)

Transmit termination resistor RTT 1%

kΩ

Ω

301

604

Note 1: Optional capacitor to reduce common mode noise.

Note 2: CTT value depends on the PC board design. Nominal values are selected for 78P7200 Demo Board.

DIGITAL INPUTS AND OUTPUTS

(CMOS-compatible pins: LOWSIG, RPOS, RNEG, RCLK, TPOS, TNEG, TCLK, LBO, OPT!.) Currents flowing

into the chip are positive. Current maximums are currents with the largest absolute value.

PARAMETER

Input low voltage

Input high voltage

CONDITIONS

MIN

-0.3

3.5

NOM

MAX

1.5

UNIT

VIL

VIH

Vcc

+0.3

Input low current

Input high current

Output low voltage

Output high voltage

IIL

IIH

VOL

VOH

VIL = 1.5V

VIH = 3.5V

IOL = 0.1 mA

IOH = -0.1 mA

-5

0.4

µA

OPT@ CHARACTERISTICS

Input low voltage

Input high voltage

VIL

VIH

IIL = 0.4 mA

0.5

RECEIVER

All of the measurements for the receiver are made with the following conditions unless otherwise stated:

1. The input signal is transformer coupled as shown in Figure 1.

2. RFO = 5.23 kΩ for DS-3, 6.81 kΩ for E3 and 4.53 kΩ for STS-1.

Input signal voltage

Short cable (3’)

VIN

Input AC-Coupled

CPD = 0.022 µF

±0.045

±0.090

±1.2

kΩ

CPD not used

Input Resistance

RIN

Input at device's common mode

voltage

Receive data detection

threshold

VDTH

Relative to peak amplitude for

22.37/17.18/25.92 MHz

sinusoidal input

Receive data low signal

threshold

VLOW

TLOW

±20

0.5

±50

Receive data low signal

CPD = 0.022 µF

500

µs

delay

CPD not used

VIN(max) = ±250 mV

78P7200

DS-3/E3/STS-1 Line Interface

With Receive Equalizer

RECEIVER (continued)

PARAMETER

Receive clock period

CONDITIONS

MIN

NOM

22.35

19.29

29.1

12.24

9.65

MAX

UNIT

TRCF

TRC

DS-3

STS-1

DS-3

STS-1

Receive clock pulse width

14.55

4.5

Receive clock positive

transition time

TRCPT

TRCNT

Cl = 15 pF

Receive clock negative

4.5

transition time

Positive or negative TRDP/ TRDN

receive data pulse width

DS-3

STS-1

22.35

19.29

29.1

Receive data set-up timeTRDPS/ TRDNS

Receive data hold timeTRDPH/ TRDNH

DS-3

STS-1

DS-3

STS-1

11.18

9.65

14.55

11.18

9.65

13.7

14.55

Receive input jitter tolerance high

frequency (See Note)

60 - 300 kHz

DS-3

0.3

UIPP

STS-1

10 - 800 kHz

0.15

0.20

UIPP

VIN (min) = ±90 mV, short cable

10 Hz to 2.3 kHz STS-1, DS-3

Receive input jitter tolerance

low frequency (See Note)

UIPP

µA/Rad

100 Hz to 10 kHz

All 1's data pattern,

KD = 0.418/RFO

DS-3

STS-1

Clock Recovery Phase

Detector Gain

Clock Recovery Phase

Locked Oscillator Gain

14.5

Mrad/

sec. -Volt

Note: UI (Unit Interval) defined as 22.35 ns for DS-3, 29.1 ns for E3 and 19.29 ns for STS-1.

78P7200

DS-3/E3/STS-1 Line Interface

With Receive Equalizer

TRANSMITTER

All of the measurements for the transmitter are made with the following conditions unless otherwise stated:

1. Transmit pulse characteristics are obtained using a line transformer which has the characteristics, similar

to Pulse Engineering PE-65969, Mini circuit T4-1, Valor PT5045.

2. The circuit is connected as in Figure 1.

PARAMETER

Transmit clock repetition

CONDITIONS

MIN

NOM

22.35

19.29

29.1

11.18

9.65

MAX

UNIT

TTCF

TTC

DS-3

STS-1

DS-3

STS-1

Transmit clock pulse width

14.55

4.5

Transmit clock negative

transition time

TTCNT

TTCPT

Transmit clock positive

4.5

transition time

Transmit data set-up time TTPDS

DS-3

STS-1

DS-3

STS-1

3.5

11.18

9.65

14.55

11.18

9.65

14.55

11.18

9.65

TTNDS

Transmit data hold time

TTPDH

TTNDH

TTPL

3.5

10.62

Measured at

transformer,

Transmit positive line

pulse width

LBO = High DS-3

LBO = High STS-1

LBO = Low

14.5

11.18

9.65

Measured at

transformer,

Transmit negative line

pulse width

TTNL

LBO = High DS-3

LBO = High STS-1

10.62

LBO = Low

14.5

Transmit line pulse waveshape

See Note 1 for DS-3

See Note 2 for E3

See Note 3 for STS-1

Note 1: Characteristics are in accordance with ANSI T1.102 - 1993 Table 4 and Figure 4.

Note 2: Characteristics are in accordance with ITU-T G.703 - 1991 Figure 17.

Note 3: Characteristics are in accordance with ANSI T1.102 - 1993 Figure A.1.

78P7200

DS-3/E3/STS-1 Line Interface

With Receive Equalizer

RECEIVE LINE

INPUT (REF)

TRCF

TRC

TRCPT

TRCNT

REC CLOCK

RCLK

TRDPS

TRDPH

REC POS OUT

RPOS

TRDP

TRDNS

TRDNH

REC NEG OUT

TRDN

RNEG

FIGURE 2: Receive Waveforms

TTCF

TTCNT

TTC

TTCPT

TRANSMIT

CLOCK IN

TCLK

TTPDS

TTPDH

TRANSMIT

POS IN

TPOS

TTNDS

TTNDH

TRANSMIT

NEG IN

TNEG

TTPL

0.5VP

TRANSMIT

LINE OUTPUT

0.5VN

TTNL

FIGURE 3: Transmit Waveforms

78P7200

DS-3/E3/STS-1 Line Interface

With Receive Equalizer

CAUTION: Use handling procedures necessary for

a static sensitive component.

PACKAGE PIN DESIGNATIONS

(Top View)

28 27 26

RFO

RGND

RVCC

TGND

LOUT+

NCT

RPOS

RNEG

RCLK

DGND

NCD

LF2

LOUT-

LF1

12 13 14 15 16 17 18

78P7200

28-Pin PLCC

ORDERING INFORMATION

PART DESCRIPTION

78P7200, DS-3/E3/STS-1 Line Interface

Surface Mount

ORDER NUMBER

PACKAGING MARK

28-Pin PLCC

78P7200-IH

No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks

or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK

Semiconductor Corporation and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the

reader is cautioned to verify that the data sheet is current before placing orders.

TDK Semiconductor Corporation, 2642 Michelle Drive, Tustin, CA 92780-7019, (714) 508-8800, FAX: (714) 508-8877

1990 TDK Semiconductor Corporation

03/05/98- rev.B

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78P7200-IH产品参数

型号:	78P7200-IH
生命周期：	Obsolete
包装说明：	PLASTIC, LCC-28
Reach Compliance Code：	unknown
风险等级：	5.12
JESD-30 代码：	S-PQCC-J28
长度：	11.54 mm
功能数量：	1
端子数量：	28
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ
封装形状：	SQUARE
封装形式：	CHIP CARRIER
认证状态：	Not Qualified
座面最大高度：	4.572 mm
标称供电电压：	5 V
表面贴装：	YES
电信集成电路类型：	PCM TRANSCEIVER
温度等级：	INDUSTRIAL
端子形式：	J BEND
端子节距：	1.27 mm
端子位置：	QUAD
宽度：	11.54 mm
Base Number Matches：	1

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产品型号78P7200-IH的概述

产品型号78P7200-IH的Datasheet PDF文件预览

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