7KZSC0JCB476MVR05005全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

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ꢋꢌ ꢍꢍ ꢎꢏ ꢎꢁꢐ ꢌꢑ ꢃ ꢄꢒꢀ ꢐ ꢏꢑꢁꢀ ꢅꢎ ꢌ ꢓꢎ ꢏ ꢀ

ꢔ

SLLS067G − AUGUST 1990 − REVISED APRIL 2006

D, JG, OR P PACKAGE

(TOP VIEW)

D

Bidirectional Transceiver

Meets or Exceeds the Requirements of

ANSI Standard TIA/EIA−485−A and

ISO 8482:1987(E)

R

RE

DE

D

V

B

A

1

2

3

4

8

7

6

5

CC

D

High-Speed Low-Power LinBiCMOS

Circuitry

GND

Designed for High-Speed Operation in Both

Serial and Parallel Applications

D

Low Skew

FK PACKAGE

(TOP VIEW)

D

Designed for Multipoint Transmission on

Long Bus Lines in Noisy Environments

D

Very Low Disabled Supply Current . . . 200

µA Maximum

Wide Positive and Negative Input/Output

Bus Voltage Ranges

3

2

1

20 19

18

NC

RE

NC

DE

NC

4

5

6

7

8

B

17

16

15

14

NC

A

D

Thermal-Shutdown Protection

NC

D

Driver Positive-and Negative-Current

Limiting

9 10 11 12 13

D

Open-Circuit Failsafe Receiver Design

Receiver Input Sensitivity . . . 200 mV Max

Receiver Input Hysteresis . . . 50 mV Typ

Operates From a Single 5-V Supply

NC−No internal connection

Glitch-Free Power-Up and Power-Down

Protection

Function Tables

D

Available in Q-Temp Automotive

HighRel Automotive Applications

Configuration Control / Print Support

Qualification to Automotive Standards

DRIVER

INPUT

ENABLE

OUTPUTS

D

H

L

DE

H

A

H

L

B

L

H

Z

X

L

Z

description

The

SN55LBC176,

SN65LBC176,

RECEIVER

SN65LBC176Q, and SN75LBC176 differential

bus transceivers are monolithic, integrated

circuits designed for bidirectional data communi-

cation on multipoint bus-transmission lines. They

are designed for balanced transmission lines and

meet ANSI Standard TIA/EIA−485−A (RS-485)

and ISO 8482:1987(E).

DIFFERENTIAL INPUTS

ENABLE

OUTPUT

V

= V −V

RE

L

H

L

R

H

?

L

Z

H

ID

IA IB

≥ 0.2 V

V

ID

−0.2 V < V < 0.2 V

ID

V

≤ −0.2 V

X

ID

Open

H = high level, L = low level, ? = indeterminate,

X = irrelevant, Z = high impedance (off)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

LinBiCMOS and LinASIC are trademarks of Texas Instruments Incorporated.

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Copyright  2000−2006, Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢉ ꢀ ꢁꢈ ꢂ ꢃꢄꢅ ꢆ ꢇꢈ ꢉ ꢀ ꢁꢈ ꢂ ꢃꢄꢅ ꢆꢇ ꢈ ꢊ ꢉ ꢀꢁ ꢇꢂ ꢃ ꢄꢅꢆ ꢇ ꢈ

ꢋ ꢌꢍ ꢍ ꢎꢏ ꢎꢁ ꢐ ꢌ ꢑꢃ ꢄꢒ ꢀ ꢐꢏ ꢑꢁ ꢀꢅ ꢎꢌ ꢓ ꢎ ꢏꢀ

ꢔ

SLLS067G − AUGUST 1990 − REVISED APRIL 2006

description (continued)

The SN55LBC176, SN65LBC176, SN65LBC176Q, and SN75LBC176 combine a 3-state, differential line driver

and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and

receiver have active-high and active-low enables, respectively, which can externally connect together to

function as a direction control. The driver differential outputs and the receiver differential inputs connect

internally to form a differential input/output (I/O) bus port that is designed to offer minimum loading to the bus

whenever the driver is disabled or V

= 0. This port features wide positive and negative common-mode voltage

CC

ranges, making the device suitable for party-line applications. Very low device supply current can be achieved

by disabling the driver and the receiver.

These transceivers are suitable for ANSI Standard TIA/EIA−485 (RS-485) and ISO 8482 applications to the

extent that they are specified in the operating conditions and characteristics section of this data sheet. Certain

limits contained in TIA/EIA−485−A and ISO 8482:1987 (E) are not met or cannot be tested over the entire military

temperature range.

The SN55LBC176 is characterized for operation from −55°C to 125°C. The SN65LBC176 is characterized for

operation from −40°C to 85°C, and the SN65LBC176Q is characterized for operation from −40°C to 125°C.

The SN75LBC176 is characterized for operation from 0°C to 70°C.

†

logic symbol

logic diagram (positive logic)

3

2

DE

RE

EN1

EN2

4

D

2

6

7

RE

6

7

A

B

1

A

B

4

1

D

R

Bus

R

2

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and

IEC Publication 617-12.

AVAILABLE OPTIONS

T

PACKAGE

PART NUMBER

SN75LBC176D

SN75LBC176P

PART MARKING

7LB176

A

SOP

PDIP

SOP

PDIP

SOP

LCCC

CDIP

0°C to 70°C

−40°C to 85°C

−40°C to 110°C

−55°C to 125°C

75LBC176

6LB176

SN65LBC176D

SN65LBC176P

65LBC176

LB176Q

SN65LBC176QD

SN65LBC176QDR

SNJ55LBC176FK

SNJ55LBC176JG

LB176Q

SNJ55LBC176FK

SNJ55LBC176

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁꢂ ꢂ ꢃ ꢄꢅꢆ ꢇ ꢈ ꢉ ꢀꢁꢈ ꢂ ꢃ ꢄꢅꢆ ꢇ ꢈ ꢉ ꢀꢁ ꢈꢂ ꢃ ꢄꢅꢆ ꢇ ꢈ ꢊ ꢉ ꢀꢁ ꢇꢂ ꢃꢄ ꢅꢆ ꢇꢈ

ꢋꢌ ꢍꢍ ꢎꢏ ꢎꢁꢐ ꢌꢑ ꢃ ꢄꢒꢀ ꢐ ꢏꢑꢁꢀ ꢅꢎ ꢌ ꢓꢎ ꢏ ꢀ

ꢔ

SLLS067G − AUGUST 1990 − REVISED APRIL 2006

schematics of inputs and outputs

EQUIVALENT OF D, RE, and

DE INPUTS

TYPICAL OF A AND B I/O PORTS

TYPICAL OF RECEIVER OUTPUT

V

CC

V

CC

V

CC

3 kΩ

NOM

100 kΩ NOM

A Port Only

A or B

Output

Input

18 kΩ

NOM

100 kΩ NOM

B Port Only

1.1 kΩ

NOM

†

absolute maximum ratings

Supply voltage, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

CC

Voltage range at any bus terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10 V to 15 V

Input voltage, V (D, DE, R, or RE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.5 V

I

CC

Receiver output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $10 mA

O

Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values, except differential I/O bus voltage, are with respect to network ground terminal.

DISSIPATION RATING TABLE

THERMAL

MODEL

T

< 25°C

DERATING FACTOR

T

= 70°C

T

= 85°C

T = 110°C

A

PACKAGE

POWER RATING

ABOVE T = 25°C

POWER RATING POWER RATING POWER RATING

A

†

Low K

526 mW

5.0 mW/°C

8.4 mW/°C

8.0 mW/°C

8.4 mW/°C

11.0 mW/°C

301 mW

504 mW

480 mW

672 mW

880 mW

226 mW

378 mW

360 mW

546 mW

715 mW

—

D

‡

High K

882 mW

P

840 mW

—

JG

FK

1050 mW

1375 mW

210 mW

440 mW

†

‡

In accordance with the low effective thermal conductivity metric definitions of EIA/JESD 51−3.

In accordance with the high effective thermal conductivity metric definitions of EIA/JESD 51−7.

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢉ ꢀ ꢁꢈ ꢂ ꢃꢄꢅ ꢆ ꢇꢈ ꢉ ꢀ ꢁꢈ ꢂ ꢃꢄꢅ ꢆꢇ ꢈ ꢊ ꢉ ꢀꢁ ꢇꢂ ꢃ ꢄꢅꢆ ꢇ ꢈ

ꢋ ꢌꢍ ꢍ ꢎꢏ ꢎꢁ ꢐ ꢌ ꢑꢃ ꢄꢒ ꢀ ꢐꢏ ꢑꢁ ꢀꢅ ꢎꢌ ꢓ ꢎ ꢏꢀ

ꢔ

SLLS067G − AUGUST 1990 − REVISED APRIL 2006

recommended operating conditions

MIN NOM

MAX

5.25

12

UNIT

Supply voltage, V

CC

4.75

−7

2

5

V

Voltage at any bus terminal (separately or common mode), V or V

IC

I

High-level input voltage, V

IH

D, DE, and RE

V

Low-level input voltage, V

IL

0.8

12

V

Differential input voltage, V (see Note 2)

ID

−12

−60

V

Driver

mA

µA

High-level output current, I

OH

Receiver

Driver

−400

60

8

Low-level output current, I

Junction temperature, T

mA

OL

Receiver

140

125

85

°C

J

SN55LBC176

SN65LBC176

SN65LBC176Q

SN75LBC176

−55

−40

0

Operating free-air temperature, T

°C

A

125

70

NOTE 2: Differential input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁꢂ ꢂ ꢃ ꢄꢅꢆ ꢇ ꢈ ꢉ ꢀꢁꢈ ꢂ ꢃ ꢄꢅꢆ ꢇ ꢈ ꢉ ꢀꢁ ꢈꢂ ꢃ ꢄꢅꢆ ꢇ ꢈ ꢊ ꢉ ꢀꢁ ꢇꢂ ꢃꢄ ꢅꢆ ꢇꢈ

ꢋꢌ ꢍꢍ ꢎꢏ ꢎꢁꢐ ꢌꢑ ꢃ ꢄꢒꢀ ꢐ ꢏꢑꢁꢀ ꢅꢎ ꢌ ꢓꢎ ꢏ ꢀ

ꢔ

SLLS067G − AUGUST 1990 − REVISED APRIL 2006

DRIVER SECTION

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

PARAMETER

Input clamp voltage

Output voltage

TEST CONDITIONS

MIN

−1.5

0

MAX

UNIT

V

I = −18 mA

V

IK

I

= 0

6

O

| V

|

Differential output voltage

I

1.5

OD1

OD2

55LBC176,

65LBC176,

65LBC176Q

1.1

1.5

R

= 54 Ω,

See Figure 1,

See Figure 2,

L

| V

Differential output voltage

V

See Note 3

75LBC176

5

55LCB176,

65LCB176,

65LBC176Q

1.1

V

= −7 V to 12 V,

test

See Note 3

V

OD3

Differential output voltage

75LBC176

1.5

−0.2

−1

5

0.2

3

Change in magnitude of differential

output voltage

∆| V

|

V

OD

†

V

OC

Common-mode output voltage

Change in magnitude of

R

= 54 Ω or 100 Ω,

See Figure 1

L

∆| V

OC

−0.2

0.2

1

†

common-mode output voltage

V

= 12 V

= −7 V

Output disabled,

See Note 4

O

I

O

Output current

mA

−0.8

−100

−250

−150

O

I

High-level input current

Low-level input current

V = 2.4 V

I

µA

IH

V = 0.4 V

I

IL

V

O

V

O

V

O

V

O

= −7 V

= 0

I

Short-circuit output current

mA

OS

CC

= V

CC

250

1.75

1.5

= 12 V

55LBC176,

65LBC176Q

Receiver disabled

and driver enabled

65LBC176,

75LBC176

V = 0 or V

I

No load

,

CC

Supply current

55LBC176,

65LBC176Q

0.25

0.2

Receiver and driver

disabled

65LBC176,

75LBC176

†

∆ | V

low level.

| and ∆ | V

OC

| are the changes in magnitude of V

OD

and V , respectively, that occur when the input changes from a high level to a

OC

OD

NOTES: 3. This device meets the V

requirements of TIA/EIA−485−A above 0°C only.

OD

4. This applies for both power on and off; refer to TIA/EIA−485−A for exact conditions.

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢉ ꢀ ꢁꢈ ꢂ ꢃꢄꢅ ꢆ ꢇꢈ ꢉ ꢀ ꢁꢈ ꢂ ꢃꢄꢅ ꢆꢇ ꢈ ꢊ ꢉ ꢀꢁ ꢇꢂ ꢃ ꢄꢅꢆ ꢇ ꢈ

ꢋ ꢌꢍ ꢍ ꢎꢏ ꢎꢁ ꢐ ꢌ ꢑꢃ ꢄꢒ ꢀ ꢐꢏ ꢑꢁ ꢀꢅ ꢎꢌ ꢓ ꢎ ꢏꢀ

ꢔ

SLLS067G − AUGUST 1990 − REVISED APRIL 2006

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature

SN55LBC176

SN65LBC176Q

SN65LBC176

SN75LBC176

PARAMETER

TEST CONDITIONS

UNIT

†

MIN

TYP

MAX

MIN TYP

MAX

t

Differential output delay time

8

31

8

25

ns

d(OD)

t(OD)

sk(p)

PZH

PZL

R

= 54 Ω,

C

= 50 pF,

L

Differential output transition time

12

0

See Figure 3

Pulse skew (| t

− t

d(ODH) d(ODL)

|)

6

65

6

35

60

35

Output enable time to high level

Output enable time to low level

R

= 110 Ω, See Figure 4

= 110 Ω, See Figure 5

= 110 Ω, See Figure 4

= 110 Ω, See Figure 5

L

65

Output disable time from high level

Output disable time from low level

105

PHZ

PLZ

†

All typical values are at V

CC

= 5 V, T = 25°C.

A

SYMBOL EQUIVALENTS

DATA SHEET PARAMETER

RS-485

V

O

V

, V

oa ob

| V

|

V

o

OD1

OD2

| V

V (R = 54 Ω)

t

L

V (test termination

t

measurement 2)

| V

OD3

|

∆ | V

|

|| V | − | V ||

t t

OD

V

OC

| V |

os

∆ | V

|

| V − V |

os os

OC

I

None

I , I

OS

I

O

ia ib

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁꢂ ꢂ ꢃ ꢄꢅꢆ ꢇ ꢈ ꢉ ꢀꢁꢈ ꢂ ꢃ ꢄꢅꢆ ꢇ ꢈ ꢉ ꢀꢁ ꢈꢂ ꢃ ꢄꢅꢆ ꢇ ꢈ ꢊ ꢉ ꢀꢁ ꢇꢂ ꢃꢄ ꢅꢆ ꢇꢈ

ꢋꢌ ꢍꢍ ꢎꢏ ꢎꢁꢐ ꢌꢑ ꢃ ꢄꢒꢀ ꢐ ꢏꢑꢁꢀ ꢅꢎ ꢌ ꢓꢎ ꢏ ꢀ

ꢔ

SLLS067G − AUGUST 1990 − REVISED APRIL 2006

RECEIVER SECTION

electrical characteristics over recommended ranges of common-mode input voltage, supply

voltage, and operating free-air temperature (unless otherwise noted)

†

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Positive-going input threshold

voltage

V

= 2.7 V,

= 0.5 V,

I

= −0.4 mA

= 8 mA

0.2

V

IT+

O

Negative-going input threshold

voltage

‡

−0.2

I

V

IT−

O

Hysteresis voltage (V

(see Figure 4)

− V )

IT−

IT+

V

50

mV

V

hys

Enable-input clamp voltage

I = −18 mA

−1.5

2.7

IK

I

V

= 200 mV,

I

= −400 µA,

ID

See Figure 6

OH

V

High-level output voltage

V

OH

V

= −200 mV,

= 8 mA,

ID

See Figure 6

OL

Low-level output voltage

0.45

V

OL

High-impedance-state output

current

I

V

= 0.4 V to 2.4 V

−20

20

1

µA

OZ

O

V = 12 V

Other input = 0 V,

See Note 5

I

Line input current

mA

V = −7 V

I

−0.8

−100

12

I

High-level enable-input current

Low-level enable-input current

Input resistance

V

= 2.7 V

= 0.4 V

µA

kΩ

IH

IL

r

I

Receiver enabled

and driver disabled

3.9

mA

V = 0 or V

I

,

SN55LBC176,

SN65LBC176,

SN65LBC176Q

CC

I

Supply current

CC

No load

0.25

0.2

Receiver and

driver disabled

mA

SN75LBC176

†

All typical values are at V

= 5 V, T = 25°C.

A

CC

‡

The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet.

NOTE 5: This applies for both power on and power off. Refer to ANSI Standard RS-485 for exact conditions.

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature, C = 15 pF

L

SN55LBC176

SN65LBC176Q

SN65LBC176

SN75LBC176

PARAMETER

TEST CONDITIONS

UNIT

†

MIN

MAX

MIN TYP

MAX

Propagation delay time, low- to high-level

single-ended output

t

11

37

11

33

ns

PLH

V

= −1.5 V to 1.5 V,

ID

Propagation delay time, high- to low-level

single-ended output

See Figure 7

11

37

11

33

PHL

t

Pulse skew (| t

− t

PLH PHL

|)

10

35

3

6

35

30

35

30

ns

sk(p)

PZH

PZL

PHZ

PLZ

Output enable time to high level

Output enable time to low level

Output disable time from high level

Output disable time from low level

See Figure 8

†

All typical values are at V

CC

= 5 V, T = 25°C.

A

7

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ꢀ ꢁꢂ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢉ ꢀ ꢁꢈ ꢂ ꢃꢄꢅ ꢆ ꢇꢈ ꢉ ꢀ ꢁꢈ ꢂ ꢃꢄꢅ ꢆꢇ ꢈ ꢊ ꢉ ꢀꢁ ꢇꢂ ꢃ ꢄꢅꢆ ꢇ ꢈ

ꢋ ꢌꢍ ꢍ ꢎꢏ ꢎꢁ ꢐ ꢌ ꢑꢃ ꢄꢒ ꢀ ꢐꢏ ꢑꢁ ꢀꢅ ꢎꢌ ꢓ ꢎ ꢏꢀ

ꢔ

SLLS067G − AUGUST 1990 − REVISED APRIL 2006

PARAMETER MEASUREMENT INFORMATION

375 Ω

60 Ω

R

L

2

V

OD3

V

OD2

R

V

OC

V

test

2

375 Ω

Figure 1. Driver V

and V

Figure 2. Driver V

OD3

OD

OC

3 V

Input

1.5 V

C

= 50 pF

L

0 V

(see Note B)

R

= 54 Ω

L

t

d(ODH)

d(ODL)

≈ 2.5 V

Generator

(see Note A)

Output

50 Ω

90%

10%

50%

Output

3 V

≈ − 2.5 V

t

t(OD)

t

t(OD)

TEST CIRCUIT

VOLTAGE WAVEFORMS

Figure 3. Driver Test Circuit and Voltage Waveforms

Output

3 V

S1

Input

1.5 V 1.5 V

0 V or 3 V

0 V

0.5 V

t

PZH

R

= 110 Ω

C

= 50 pF

L

V

OH

(see Note B)

Generator

(see Note A)

Output

50 Ω

2.3 V

V

off

≈ 0 V

t

PHZ

TEST CIRCUIT

VOLTAGE WAVEFORMS

Figure 4. Driver Test Circuit and Voltage Waveforms

5 V

3 V

0 V

PLZ

Input

1.5 V

R

= 110 Ω

L

S1

Output

3 V or 0 V

t

PZL

t

C

= 50 pF

L

5 V

0.5 V

Generator

(see Note A)

(see Note B)

50 Ω

2.3 V

Output

V

OL

TEST CIRCUIT

VOLTAGE WAVEFORMS

Figure 5. Driver Test Circuit and Voltage Waveforms

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, t ≤ 6 ns, t ≤ 6 ns,

r

f

Z

C

= 50 Ω.

O

L

B.

includes probe and jig capacitance.

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢋꢌ ꢍꢍ ꢎꢏ ꢎꢁꢐ ꢌꢑ ꢃ ꢄꢒꢀ ꢐ ꢏꢑꢁꢀ ꢅꢎ ꢌ ꢓꢎ ꢏ ꢀ

ꢔ

SLLS067G − AUGUST 1990 − REVISED APRIL 2006

PARAMETER MEASUREMENT INFORMATION

V

ID

V

OH

+I

OL

−I

OH

V

OL

Figure 6. Receiver V

and V

OL

OH

3 V

0 V

Input

1.5 V

Output

Generator

(see Note A)

51 Ω

t

1.5 V

0 V

t

PHL

PLH

C

= 15 pF

(see Note B)

L

V

OH

Output

1.3 V

V

OL

VOLTAGE WAVEFORMS

TEST CIRCUIT

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, t ≤ 6 ns, t ≤ 6 ns,

r

f

Z

C

= 50 Ω.

O

L

B.

includes probe and jig capacitance.

Figure 7. Receiver Test Circuit and Voltage Waveforms

THERMAL CHARACTERISTICS − D PACKAGE

TEST CONDITIONS

PARAMETER

Junction−to−ambient thermal reisistance, θ

MIN

TYP

199.4

119

MAX

UNIT

Low-K board, no air flow

†

JA

High-K board, no air flow

°C/W

Junction−to−board thermal reisistance, θ

JB

High-K board, no air flow

67

Junction−to−case thermal reisistance, θ

46.6

JC

R

= 54 Ω, input to D is 10 Mbps 50% duty

L

cycle square wave, V

T = 130 °C.

J

= 5.25 V,

Average power dissipation, P

(AVG)

330

mW

CC

Thermal shutdown junction temperature, T

SD

165

°C

†

See TI application note literature number SZZA003, Package Thermal Characterization Methodologies, for an explanation of this parameter.

9

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ꢋ ꢌꢍ ꢍ ꢎꢏ ꢎꢁ ꢐ ꢌ ꢑꢃ ꢄꢒ ꢀ ꢐꢏ ꢑꢁ ꢀꢅ ꢎꢌ ꢓ ꢎ ꢏꢀ

ꢔ

SLLS067G − AUGUST 1990 − REVISED APRIL 2006

PARAMETER MEASUREMENT INFORMATION

S1

1.5 V

S2

2 kΩ

−1.5 V

5 V

C

= 15 pF

5 kΩ

L

1N916 or Equivalent

(see Note B)

Generator

(see Note A)

50 Ω

S3

TEST CIRCUIT

3 V

S1 to 1.5 V

S2 Open

3 V

S1 to −1.5 V

S2 Closed

S3 Opened

Input

1.5 V

S3 Closed

0 V

t

PZH

t

PZL

V

OH

≈ 4.5 V

1.5 V

Output

Input

Output

Input

1.5 V

0 V

V

OL

3 V

S1 to 1.5 V

S2 Closed

S3 Closed

S1 to −1.5 V

S2 Closed

S3 Closed

1.5 V

0 V

t

PHZ

t

PLZ

≈ 1.3 V

V

OH

0.5 V

Output

0.5 V

V

OL

≈ 1.3 V

VOLTAGE WAVEFORMS

Figure 8. Receiver Test Circuit and Voltage Waveforms

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, t ≤ 6 ns, t ≤ 6 ns,

r

f

Z

C

= 50 Ω.

O

L

B.

includes probe and jig capacitance.

10

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ꢋꢌ ꢍꢍ ꢎꢏ ꢎꢁꢐ ꢌꢑ ꢃ ꢄꢒꢀ ꢐ ꢏꢑꢁꢀ ꢅꢎ ꢌ ꢓꢎ ꢏ ꢀ

ꢔ

SLLS067G − AUGUST 1990 − REVISED APRIL 2006

THERMAL CHARACTERISTICS OF IC PACKAGES

Θ

_JA(Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient temperature

divided by the operating power

Θ

D

Θ

_JAis NOT a constant and is a strong function of

the PCB design (50% variation)

altitude (20% variation)

device power (5% variation)

_JAcan be used to compare the thermal performance of packages if the specific test conditions are defined and used.

Standardized testing includes specification of PCB construction, test chamber volume, sensor locations, and the thermal

characteristics of holding fixtures.

installations.

is often misused when it is used to calculate junction temperatures for other

Θ

JA

TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition thermal

performance and consists of a single trace layer 25 mm long and 2-oz thick copper. The high-k board givesbest case in−use

condition and consists of two 1-oz buried power planes with a single trace layer 25 mm long with 2-oz thick copper. A 4%

to 50% difference in Θ_JAcan be measured between these two test cards

Θ_JC(Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by the

operating power. It is measured by putting the mounted package up against a copper block cold plate to force heat to flow

from die, through the mold compound into the copper block.

Θ

_JCis a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic to predict

junction temperature as it provides pessimistic numbers if the case temperature is measured in a non-standard system and

junction temperatures are backed out. It can be used with Θ_JBin 1-dimensional thermal simulation of a package system.

Θ_JB(Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the PCB

temperature at the center of the package (closest to the die) when the PCB is clamped in a cold−plate structure. Θ_JBis only

defined for the high-k test card.

Θ

_JBprovides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal resistance

(especially for BGA’s with thermal balls) and can be used for simple 1-dimensional network analysis of package system

(see Figure 1).

Ambient Node

q

Calculated

CA

Surface Node

Calculated/Measured

q

JC

Junction

Calculated/Measured

q

JB

PC Board

Figure 1. Thermal Resistance

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢋ ꢌꢍ ꢍ ꢎꢏ ꢎꢁ ꢐ ꢌ ꢑꢃ ꢄꢒ ꢀ ꢐꢏ ꢑꢁ ꢀꢅ ꢎꢌ ꢓ ꢎ ꢏꢀ

ꢔ

SLLS067G − AUGUST 1990 − REVISED APRIL 2006

MECHANICAL INFORMATION

D (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0.050 (1,27)

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

M

14

8

0.008 (0,20) NOM

0.244 (6,20)

0.228 (5,80)

0.157 (4,00)

0.150 (3,81)

Gage Plane

0.010 (0,25)

1

7

0°−ā8°

0.044 (1,12)

A

0.016 (0,40)

Seating Plane

0.004 (0,10)

0.010 (0,25)

0.004 (0,10)

0.069 (1,75) MAX

PINS **

8

14

16

DIM

0.197

(5,00)

0.344

(8,75)

0.394

(10,00)

A MAX

0.189

(4,80)

0.337

(8,55)

0.386

(9,80)

A MIN

4040047/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).

D. Falls within JEDEC MS-012

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢋꢌ ꢍꢍ ꢎꢏ ꢎꢁꢐ ꢌꢑ ꢃ ꢄꢒꢀ ꢐ ꢏꢑꢁꢀ ꢅꢎ ꢌ ꢓꢎ ꢏ ꢀ

ꢔ

SLLS067G − AUGUST 1990 − REVISED APRIL 2006

MECHANICAL INFORMATION

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINALS SHOWN

A

B

NO. OF

TERMINALS

**

18 17 16 15 14 13 12

MIN

MAX

MIN

MAX

0.342

(8,69)

0.358

(9,09)

0.307

(7,80)

0.358

(9,09)

19

20

11

10

9

20

28

44

52

68

84

0.442

(11,23)

0.458

(11,63)

0.406

(10,31)

0.458

(11,63)

21

B SQ

22

0.640

(16,26)

0.660

(16,76)

0.495

(12,58)

0.560

(14,22)

8

A SQ

23

0.740

(18,78)

0.761

(19,32)

0.495

(12,58)

0.560

(14,22)

7

24

25

6

0.938

(23,83)

0.962

(24,43)

0.850

(21,6)

0.858

(21,8)

5

1.141

(28,99)

1.165

(29,59)

1.047

(26,6)

1.063

(27,0)

26 27 28

1

2

3

4

0.080 (2,03)

0.064 (1,63)

0.020 (0,51)

0.010 (0,25)

0.020 (0,51)

0.010 (0,25)

0.055 (1,40)

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

4040140/C 11/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold-plated.

E. Falls within JEDEC MS-004

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢋ ꢌꢍ ꢍ ꢎꢏ ꢎꢁ ꢐ ꢌ ꢑꢃ ꢄꢒ ꢀ ꢐꢏ ꢑꢁ ꢀꢅ ꢎꢌ ꢓ ꢎ ꢏꢀ

ꢔ

SLLS067G − AUGUST 1990 − REVISED APRIL 2006

MECHANICAL INFORMATION

JG (R-GDIP-T8)

CERAMIC DUAL-IN-LINE PACKAGE

0.400 (10,20)

0.355 (9,00)

8

5

0.280 (7,11)

0.245 (6,22)

1

4

0.065 (1,65)

0.045 (1,14)

0.310 (7,87)

0.290 (7,37)

0.020 (0,51) MIN

0.200 (5,08) MAX

0.130 (3,30) MIN

Seating Plane

0.063 (1,60)

0.015 (0,38)

0°−15°

0.023 (0,58)

0.015 (0,38)

0.100 (2,54)

0.014 (0,36)

0.008 (0,20)

4040107/C 08/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.

E. Falls within MIL-STD-1835 GDIP1-T8

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢭ ꢎꢅꢱꢑ ꢁꢌꢅ ꢑꢃ ꢋ ꢑꢐꢑ

MPDI001A − JANUARY 1995 − REVISED JUNE 1999

MECHANICAL INFORMATION

P (R-PDIP-T8)

PLASTIC DUAL-IN-LINE

0.400 (10,60)

0.355 (9,02)

8

5

0.260 (6,60)

0.240 (6,10)

1

4

0.070 (1,78) MAX

0.325 (8,26)

0.300 (7,62)

0.020 (0,51) MIN

0.015 (0,38)

Gage Plane

0.200 (5,08) MAX

Seating Plane

0.010 (0,25) NOM

0.125 (3,18) MIN

0.100 (2,54)

0.021 (0,53)

0.430 (10,92)

MAX

0.010 (0,25)

M

0.015 (0,38)

4040082/D 05/98

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001

For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

12-Jan-2007

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

LCCC

CDIP

SOIC

Drawing

5962-9318301Q2A

5962-9318301QPA

SN65LBC176D

ACTIVE

FK

JG

D

20

8

1

TBD

POST-PLATE N / A for Pkg Type

A42 SNPB N / A for Pkg Type

8

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN65LBC176DG4

SN65LBC176DR

SN65LBC176DRG4

SN65LBC176P

ACTIVE

SOIC

PDIP

D

P

8

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

50

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

SN65LBC176PE4

50

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

SN65LBC176QD

SN65LBC176QDR

SN75LBC176D

ACTIVE

SOIC

D

8

75

TBD

CU NIPDAU Level-1-220C-UNLIM

2500

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN75LBC176DG4

SN75LBC176DR

SN75LBC176DRG4

SN75LBC176P

ACTIVE

SOIC

PDIP

D

P

8

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

50

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

POST-PLATE N / A for Pkg Type

SN75LBC176PE4

50

Pb-Free

(RoHS)

SNJ55LBC176FK

SNJ55LBC176JG

ACTIVE

LCCC

CDIP

FK

JG

20

8

1

TBD

A42 SNPB

N / A for Pkg Type

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

12-Jan-2007

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MCER001A – JANUARY 1995 – REVISED JANUARY 1997

JG (R-GDIP-T8)

CERAMIC DUAL-IN-LINE

0.400 (10,16)

0.355 (9,00)

8

5

0.280 (7,11)

0.245 (6,22)

1

4

0.065 (1,65)

0.045 (1,14)

0.310 (7,87)

0.290 (7,37)

0.063 (1,60)

0.015 (0,38)

0.020 (0,51) MIN

0.200 (5,08) MAX

0.130 (3,30) MIN

Seating Plane

0.023 (0,58)

0.015 (0,38)

0°–15°

0.100 (2,54)

0.014 (0,36)

0.008 (0,20)

4040107/C 08/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification.

E. Falls within MIL STD 1835 GDIP1-T8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A

B

NO. OF

TERMINALS

**

18 17 16 15 14 13 12

MIN

MAX

MIN

MAX

0.342

(8,69)

0.358

(9,09)

0.307

(7,80)

0.358

(9,09)

19

20

11

10

9

20

28

44

52

68

84

0.442

(11,23)

0.458

(11,63)

0.406

(10,31)

0.458

(11,63)

21

B SQ

22

0.640

(16,26)

0.660

(16,76)

0.495

(12,58)

0.560

(14,22)

8

A SQ

23

0.739

(18,78)

0.761

(19,32)

0.495

(12,58)

0.560

(14,22)

7

24

25

6

0.938

(23,83)

0.962

(24,43)

0.850

(21,6)

0.858

(21,8)

5

1.141

(28,99)

1.165

(29,59)

1.047

(26,6)

1.063

(27,0)

26 27 28

1

2

3

4

0.080 (2,03)

0.064 (1,63)

0.020 (0,51)

0.010 (0,25)

0.020 (0,51)

0.010 (0,25)

0.055 (1,40)

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

4040140/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold plated.

E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MPDI001A – JANUARY 1995 – REVISED JUNE 1999

P (R-PDIP-T8)

PLASTIC DUAL-IN-LINE

0.400 (10,60)

0.355 (9,02)

8

5

0.260 (6,60)

0.240 (6,10)

1

4

0.070 (1,78) MAX

0.325 (8,26)

0.300 (7,62)

0.020 (0,51) MIN

0.015 (0,38)

Gage Plane

0.200 (5,08) MAX

Seating Plane

0.010 (0,25) NOM

0.125 (3,18) MIN

0.100 (2,54)

0.021 (0,53)

0.430 (10,92)

MAX

0.010 (0,25)

M

0.015 (0,38)

4040082/D 05/98

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001

For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to

discontinue any product or service without notice. Customers should obtain the latest relevant information

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subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent

TI deems necessary to support this warranty. Except where mandated by government requirements, testing

of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible

for their products and applications using TI components. To minimize the risks associated with customer

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Applications

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amplifier.ti.com

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Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

型号:	7L-16.368MCG-T
是否Rohs认证：	符合
生命周期：	Active
包装说明：	SMD, 4 PIN
Reach Compliance Code：	unknown
风险等级：	1.58
安装特点：	SURFACE MOUNT
端子数量：	4
最大工作频率：	52 MHz
最小工作频率：	13 MHz
标称工作频率：	16.368 MHz
最高工作温度：	85 °C
最低工作温度：	-30 °C
振荡器类型：	CLIPPED SINE
封装主体材料：	CERAMIC
封装等效代码：	LCC4,.08X.1,86/53
电源：	2.5 V
认证状态：	Not Qualified
子类别：	Other Oscillators
最大压摆率：	2 mA
标称供电电压：	2.5 V
表面贴装：	YES
Base Number Matches：	1

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