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产品型号8403606JA的Datasheet PDF文件预览

TM  
HM-65162  
2K x 8 Asynchronous  
CMOS Static RAM  
March 1997  
Features  
Description  
• Fast Access Time . . . . . . . . . . . . . . . . . . . 70/90ns Max  
• Low Standby Current. . . . . . . . . . . . . . . . . . . .50µA Max  
• Low Operating Current . . . . . . . . . . . . . . . . . 70mA Max  
• Data Retention at 2.0V. . . . . . . . . . . . . . . . . . .20µA Max  
• TTL Compatible Inputs and Outputs  
• JEDEC Approved Pinout (2716, 6116 Type)  
• No Clocks or Strobes Required  
The HM-65162 is a CMOS 2048 x 8 Static Random Access  
Memory manufactured using the Intersil Advanced SAJI V  
process. The device utilizes asynchronous circuit design for  
fast cycle time and ease of use. The pinout is the JEDEC 24  
pin DIP, and 32 pad 8-bit wide standard which allows easy  
memory board layouts flexible to accommodate a variety of  
industry standard PROMs, RAMs, ROMs and EPROMs. The  
HM-65162 is ideally suited for use in microprocessor based  
systems with its 8-bit word length organization. The conve-  
nient output enable also simplifies the bus interface by allow-  
ing the data outputs to be controlled independent of the chip  
enable. Gated inputs lower operating current and also elimi-  
nate the need for pull-up or pull-down resistors.  
• Equal Cycle and Access Time  
• Single 5V Supply  
• Gated Inputs  
• No Pull-Up or Pull-Down Resistors Required  
Ordering Information  
PACKAGE  
CERDIP  
JAN#  
TEMP. RANGE  
70ns/20µA (NOTE 1)  
HM1-65162B-9  
29110BJA  
90ns/40µA (NOTE 1)  
HM1-65162-9  
29104BJA  
90ns/300µA (NOTE 1)  
HM1-65162C-9  
-
PKG. NO.  
F24.6  
o
o
-40 C to +85 C  
o
o
-55 C to +125 C  
F24.6  
o
o
SMD#  
-55 C to +125 C  
8403606JA  
8403602JA  
8403603JA  
F24.6  
o
o
CLCC  
-40 C to +85 C  
HM4-65162B-9  
8403606ZA  
HM4-65162-9  
8403602ZA  
HM4-65162C-9  
8403603ZA  
J32.A  
o
o
SMD#  
-55 C to 125 C  
J32.A  
NOTE:  
1. Access time/data retention supply current.  
Pinouts  
HM-65162  
(CERDIP)  
TOP VIEW  
HM-65162  
(CLCC)  
TOP VIEW  
PIN  
NC  
DESCRIPTION  
No Connect  
A7  
A6  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
V
CC  
1
4
3
2
32 31 30  
A8  
29  
28  
27  
26  
25  
24  
23  
22  
21  
5
6
A8  
A9  
NC  
A6  
A5  
A0 - A10  
E
Address Input  
A5  
A9  
Chip Enable/Power Down  
Ground  
A4  
W
7
8
A4  
A3  
A3  
G
V
/GND  
SS  
W
G
A2  
A10  
E
DQ0 - DQ7 Data In/Data Out  
9
A2  
A1  
10  
11  
12  
13  
A1  
A10  
E
A0  
V
Power (+5V)  
Write Enable  
Output Enable  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
CC  
DQ0  
A0  
W
G
DQ1 10  
DQ2 11  
NC  
DQ0  
DQ7  
DQ6  
GND  
12  
14  
15 16 17 18 19 20  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.  
FN3000.1  
Copyright © Intersil Americas Inc. 2002. All Rights Reserved  
1
HM-65162  
Functional Diagram  
A1  
A
A
A2  
A3  
A4  
A5  
A6  
A7  
7
7
ROW  
ADDRESS  
BUFFER  
128 X 128  
MEMORY ARRAY  
ROW  
DECODER  
128  
1 OF 8  
DQ0  
128  
THRU  
DQ7  
8
COLUMN DECODER  
AND DATA  
E
INPUT / OUTPUT (X8)  
4
4
A
A
G
COLUMN  
ADDRESS BUFFER  
W
A0  
A8 A9 A10  
2
HM-65162  
Absolute Maximum Ratings  
Thermal Information  
o
o
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V  
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to V +0.3V  
Typical Derating Factor . . . . . . . . . . 05mA/MHz Increase in ICCOP  
Thermal Resistance  
CERDIP Package . . . . . . . . . . . . . . . .  
CLCC Package . . . . . . . . . . . . . . . . . .  
θ
( C/W)  
θ
( C/W)  
JA  
JC  
48  
66  
8
CC  
12  
o
o
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1  
Maximum Storage Temperature Range . . . . . . . . .-65 C to +150 C  
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175 C  
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300 C  
o
o
Operating Conditions  
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V  
Operating Temperature Range  
Die Characteristics  
HM-65162S-9, HM-65162B-9,  
HM-65162-9, HM65162C-9. . . . . . . . . . . . . . . . . . -40 C to +85 C  
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26000 Gates  
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating  
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
o
o
DC Electrical Specifications V = 5V ±10%; T = -40 C to +85 C (HM-65162S-9, HM-65162B-9, HM-65162-9, HM-65162C-9)  
CC  
A
LIMITS  
SYMBOL  
PARAMETER  
MIN  
MAX  
UNITS  
TEST CONDITIONS  
ICCSB1  
Standby Supply Current  
-
50  
µA  
HM-65162B-9, IO = 0mA,  
E = V  
- 0.3V, V  
= 5.5V  
CC  
CC  
-
-
100  
900  
µA  
µA  
HM-65162S-9, HM65162-9,  
IO = 0mA, E = V - 0.3V,  
CC  
V
= 5.5V  
CC  
HM-65162C-9, IO = 0mA,  
E = V - 0.3V, V = 5.5V  
CC  
CC  
ICCSB  
ICCEN  
ICCOP  
Standby Supply Current  
-
-
-
8
mA  
mA  
mA  
E = 2.2V, IO = 0mA, V  
E = 0.8V, IO = 0mA, V  
= 5.5V  
= 5.5V  
CC  
CC  
Enabled Supply Current  
70  
70  
Operating Supply Current (Note 1)  
E = 0.8V, IO = 0mA, f = 1MHz,  
= 5.5V  
V
CC  
HM-65162B-9, IO = 0mA,  
= 2.0V, E = VCC - 0.3V  
ICCDR  
Data Retention Supply Current  
-
-
20  
40  
µA  
µA  
V
CC  
HM-65162S-9, HM-65162-9,  
IO = 0mA, V = 2.0V,  
CC  
- 0.3V  
E = V  
CC  
-
300  
µA  
HM-65162C-9, IO = 0mA,  
= 2.0V, E = V - 0.3V  
V
CC  
CC  
VCCDR  
II  
Data Retention Supply Voltage  
Input Leakage Current  
Input/Output Leakage Current  
Input Low Voltage  
2.0  
-1.0  
-1.0  
-0.3  
2.2  
-
-
V
µA  
µA  
V
+1.0  
+1.0  
0.8  
VI = V  
CC  
or GND, V  
= 5.5V  
CC  
IIOZ  
VIO = V  
CC  
or GND, V  
= 5.5V  
CC  
V
V
= 4.5V  
= 5.5V  
IL  
CC  
CC  
V
Input High Voltage  
V
+0.3  
V
V
IH  
CC  
VOL  
Output Low Voltage  
0.4  
V
IO = 4.0mA, V  
CC  
= 4.5V  
= 4.5V  
VOH1  
VOH2  
Output High Voltage  
2.4  
-
-
V
IO = -1.0mA, V  
CC  
CC  
Output High Voltage (Note 2)  
V
-0.4  
V
IO = -100µA, V  
= 4.5V  
CC  
o
Capacitance T = +25 C  
A
SYMBOL  
PARAMETER  
MAX  
10  
UNITS  
TEST CONDITIONS  
CI  
Input Capacitance (Note 2)  
pF  
pF  
f = 1MHz, All measurements are  
referenced to device GND  
CIO  
Input/Output Capacitance (Note 2)  
12  
NOTES:  
1. Typical derating 5mA/MHz increase in ICCOP.  
2. Tested at initial design and after major design changes.  
3
HM-65162  
o
o
AC Electrical Specifications V = 5V ±10%, T = -40 C to +85 C (HM-65162S-9, HM-65162B-9, HM65162-9, HM-65162C-9)  
CC  
A
LIMITS  
HM-65162S-9 HM-65162B-9 HM-65162-9  
HM-65162C-9  
SYMBOL  
READ CYCLE  
(1) TAVAX  
(2) TAVQV  
(3) TELQV  
PARAMETER  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
CONDITIONS  
Read Cycle Time  
55  
-
-
70  
-
-
90  
-
-
90  
-
-
ns  
ns  
ns  
(Notes 1, 3)  
(Notes 1, 3, 4)  
(Notes 1, 3)  
Address Access Time  
55  
55  
70  
70  
90  
90  
90  
90  
Chip Enable Access  
Time  
-
-
-
-
(4) TELQX  
(5) TGLQV  
(6) TGLQX  
(7) TEHQZ  
(8) TGHQZ  
(9) TAVQX  
Chip Enable Output  
Enable Time  
5
-
-
35  
-
5
-
-
50  
-
5
-
-
65  
-
5
-
-
65  
-
ns  
ns  
ns  
ns  
ns  
ns  
(Notes 2, 3)  
(Notes 1, 3)  
(Notes 2, 3)  
(Notes 2, 3)  
(Notes 2, 3)  
(Notes 1, 3)  
Output Enable Access  
Time  
Output Enable Output  
Enable Time  
5
-
5
-
5
-
5
-
Chip Enable Output  
Disable Time  
35  
30  
-
35  
35  
-
50  
40  
-
50  
40  
-
Output Enable Output  
Disable Time  
-
-
-
-
Output Hold From  
Address Change  
5
5
5
5
WRITE CYCLE  
(10) TAVAX  
(11) TELWH  
Write Cycle Time  
55  
45  
-
-
70  
45  
-
-
90  
55  
-
-
90  
55  
-
-
ns  
ns  
(Notes 1, 3)  
(Notes 1, 3)  
Chip Selection to End of  
Write  
(12) TAVWL  
(13) TWLWH  
Address Setup Time  
5
-
-
10  
40  
-
-
10  
55  
-
-
10  
55  
-
-
ns  
ns  
(Notes 1, 3)  
(Notes 1, 3)  
Write Enable Pulse  
Width  
40  
(14) TWHAX  
(15) TGHQZ  
(16) TWLQZ  
Write Enable Read  
Setup Time  
10  
-
-
10  
-
-
10  
-
-
10  
-
-
ns  
ns  
ns  
(Notes 1, 3)  
(Notes 2, 3)  
(Notes 2, 3)  
Output Enable Output  
Disable Time  
30  
30  
35  
40  
40  
50  
40  
50  
Write Enable Output  
Disable Time  
-
-
-
-
(17) TDVWH  
(18) TWHDX  
(19) TWHQX  
Data Setup Time  
Data Hold Time  
25  
10  
0
-
-
-
30  
10  
0
-
-
-
30  
15  
0
-
-
-
30  
15  
0
-
-
-
ns  
ns  
ns  
(Notes 1, 3)  
(Notes 1, 3)  
(Notes 1, 3)  
Write Enable Output  
Enable Time  
(20) TWLEH  
(21) TDVEH  
(22) TAVWH  
NOTES:  
Write Enable Pulse  
Setup Time  
45  
25  
45  
-
-
-
40  
30  
50  
-
-
-
55  
30  
65  
-
-
-
55  
30  
65  
-
-
-
ns  
ns  
ns  
(Notes 1, 3)  
(Notes 1, 3)  
(Notes 1, 3)  
Chip Enable Data  
Setup Time  
Address Valid to End of  
Write  
1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate  
equivalent and C = 50pF (min) - for C greater than 50pF, access time is derated by 0.15ns per pF.  
L
L
2. Tested at initial design and after major design changes.  
3. V = 4.5 and 5.5V.  
CC  
4. TAVQV = TELQV + TAVEL.  
4
HM-65162  
Timing Waveforms  
(1) TAVAX  
(2) TAVQV  
ADDRESS  
G
(8) TGHQZ  
(5) TGLQV  
(7) TEHQZ  
(6) TGLQX  
E
(3) TELQV  
(9) TAVQX  
Q
(4) TELQX  
NOTE:  
1. W is high for a Read Cycle.  
FIGURE 1. READ CYCLE  
Addresses must remain stable for the duration of the read is low. To execute consecutive read cycles, E may be tied  
cycle. To read, G and E must be V and W V . The  
IL IH  
output buffers can be controlled independently by G while E  
low continuously until all desired locations are accessed.  
(10) TAVAX  
ADDRESS  
(14) TWHAX  
(11) TELWH  
E
W
Q
D
(12) TAVWL  
(16) TWLQZ  
(13) TWLWH  
(20) TWLEH  
(19) TWHQX  
(21)  
TDVEH  
(17) TDVWH  
(22) TAVWH  
(18) TWHDX  
NOTE:  
1. G is low throughout Write Cycle.  
FIGURE 2. WRITE CYCLE I  
To write, addresses must be stable, E low and W falling low and input data of the opposite phase to the outputs must not  
for a period no shorter than TWLWH. Data in is referenced be applied, (Bus contention). If transitions low  
E
with the rising edge of W, (TDVWH and TWHDX). While simultaneously with the W line transitioning low, or after the  
addresses are changing, W must be high. When W falls low, W transition, the output will remain in a high impedance  
the I/O pins are still in the output state for a period of TWLQZ state. G is held continuously low.  
5
HM-65162  
Timing Waveforms (Continued)  
(10) TAVAX  
ADDRESS  
G
(22) TAVWH  
(11) TELWH  
(14)  
TWHAX  
E
(12) TAVWL  
(13) TWLWH  
W
TGHQZ  
(15)  
Q
D
(21) TDVEH  
(17) TDVWH  
(18) TWHDX  
FIGURE 3. WRITE CYCLE II  
In this write cycle G has control of the output after a period, allows data in to be applied without bus contention after  
TGHQZ. G switching the output to a high impedance state  
Low Voltage Data Retention  
Intersil CMOS RAMs are designed with battery backup in  
mind. Data retention voltage and supply current are guaran-  
teed over temperature. The following rules ensure data  
retention:  
2. On RAMs which have selects or output enables (e.g., S,  
G), one of the selects or output enables should be held in  
the deselected state to keep the RAM outputs high im-  
pedance, minimizing power dissipation.  
3. Inputs which are to be held high (e.g., E) must be kept be-  
1. Chip Enable (E) must be held high during data retention;  
tween V  
+0.3V and 70% of V during the power up  
CC  
CC  
and down transitions.  
within V  
-0.3V to V  
+0.3V.  
CC  
CC  
4. The RAM can begin operation > 55ns after V  
the minimum operating voltage (4.5V).  
reaches  
CC  
DATA  
RETENTION  
TIMING  
V
02.0V  
CC  
V
CC  
4.5V  
4.5V  
>55ns  
V
-0.3V TO V  
+0.3V  
CC  
CC  
E
FIGURE 4. DATA RETENTION TIMING  
6
HM-65162  
Typical Performance Curve  
-3  
V
= 2.0V  
CC  
-4  
-5  
-6  
-7  
-8  
-9  
-10  
-11  
-12  
-55  
-35  
-15  
5
25  
T
45  
65  
85  
105  
125  
o
( C)  
A
FIGURE 5. TYPICAL ICCDR vs T  
A
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.  
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
Sales Office Headquarters  
NORTH AMERICA  
Intersil Corporation  
7585 Irvine Center Drive  
Suite 100  
Irvine, CA 92618  
TEL: (949) 341-7000  
FAX: (949) 341-7123  
EUROPE  
ASIA  
Intersil Corporation  
Intersil Corporation  
2401 Palm Bay Rd.  
Palm Bay, FL 32905  
TEL: (321) 724-7000  
FAX: (321) 724-7946  
Intersil Europe Sarl  
Ave. William Graisse, 3  
1006 Lausanne  
Switzerland  
TEL: +41 21 6140560  
FAX: +41 21 6140579  
Unit 1804 18/F Guangdong Water Building  
83 Austin Road  
TST, Kowloon Hong Kong  
TEL: +852 2723 6339  
FAX: +852 2730 1433  
7
配单直通车
8403606JA产品参数
型号:8403606JA
生命周期:Active
IHS 制造商:DEFENSE LOGISTICS AGENCY
零件包装代码:DIP
包装说明:DIP,
针数:24
Reach Compliance Code:unknown
ECCN代码:3A001.A.2.C
HTS代码:8542.32.00.41
风险等级:5.26
最长访问时间:70 ns
JESD-30 代码:R-GDIP-T24
内存密度:16384 bit
内存集成电路类型:STANDARD SRAM
内存宽度:8
功能数量:1
端子数量:24
字数:2048 words
字数代码:2000
工作模式:ASYNCHRONOUS
最高工作温度:125 °C
最低工作温度:-55 °C
组织:2KX8
封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP
封装形状:RECTANGULAR
封装形式:IN-LINE
并行/串行:PARALLEL
认证状态:Qualified
筛选级别:MIL-STD-883
最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V
表面贴装:NO
技术:CMOS
温度等级:MILITARY
端子形式:THROUGH-HOLE
端子位置:DUAL
Base Number Matches:1
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