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88E1111 Product Brief

Integrated 10/100/1000 Ultra

Gigabit Ethernet Transceiver

Doc. No. MV-S105540-00, Rev. --

March 4, 2009

Document Classification: Proprietary Information

Marvell. Moving Forward Faster

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

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Advance

Information

This document contains design specifications for initial product development. Specifications may

change without notice. Contact Marvell Field Application Engineers for more information.

Preliminary

Information

This document contains preliminary data, and a revision of this document will be published at a later

date. Specifications may change without notice. Contact Marvell Field Application Engineers for

more information.

Final

Information

This document contains specifications on a product that is in final release. Specifications may

change without notice. Contact Marvell Field Application Engineers for more information.

Doc Status: Advance

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Doc. No. MV-S105540-00 Rev. --

Page 2

March 4, 2009, Advance

Document Classification: Proprietary Information

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

OVERVIEW

FEATURES

The Alaska^®Ultra 88E1111 Gigabit Ethernet Trans-

ceiver is a physical layer device for Ethernet

1000BASE-T, 100BASE-TX, and 10BASE-T applica-

tions. It is manufactured using standard digital CMOS

process and contains all the active circuitry required to

implement the physical layer functions to transmit and

receive data on standard CAT 5 unshielded twisted pair.

•

10/100/1000BASE-T IEEE 802.3 compliant

Supports GMII, TBI, reduced pin count GMII

(RGMII), reduced pin count TBI (RTBI), and serial

GMII (SGMII) interfaces

•

Integrated 1.25 GHz SERDES for 1000BASE-X

fiber applications

•

Four RGMII timing modes

The 88E1111 device incorporates the Marvell Virtual

Cable Tester^®(VCT™) feature, which uses Time

Domain Reflectometry (TDR) technology for the remote

identification of potential cable malfunctions, thus

reducing equipment returns and service calls. Using

VCT, the Alaska 88E1111 device detects and reports

potential cabling issues such as pair swaps, pair polar-

ity and excessive pair skew. The device will also detect

cable opens, shorts or any impedance mismatch in the

cable and report accurately within one meter the dis-

tance to the fault.

Energy Detect and Energy Detect+ low power

modes

•

Three loopback modes for diagnostics

“Downshift” mode for two-pair cable installations

Fully integrated digital adaptive equalizers, echo

cancellers, and crosstalk cancellers

•

Advanced digital baseline wander correction

Automatic MDI/MDIX crossover at all speeds of

operation

•

Automatic polarity correction

The 88E1111 device supports the Gigabit Media Inde-

pendent Interface (GMII), Reduced GMII (RGMII),

Serial Gigabit Media Independent Interface (SGMII),

the Ten-Bit Interface (TBI), and Reduced TBI (RTBI) for

direct connection to a MAC/Switch port.

IEEE 802.3u compliant Auto-Negotiation

Software programmable LED modes including LED

testing

•

Automatic detection of fiber or copper operation

Supports IEEE 1149.1 JTAG

The 88E1111 device incorporates an optional 1.25 GHz

SERDES (Serializer/Deserializer). The serial interface

may be connected directly to a fiber-optic transceiver

for 1000BASE-T/1000BASE-X media conversion appli-

cations. Additionally, the 88E1111 device may be used

to implement 1000BASE-T Gigabit Interface Converter

(GBIC) or Small Form Factor Pluggable (SFP) modules.

Two-Wire Serial Interface (TWSI) and MDC/MDIO

CRC checker, packet counter

Packet generation

Virtual Cable Tester (VCT)

Auto-Calibration for MAC Interface outputs

The 88E1111 device uses advanced mixed-signal pro-

cessing to perform equalization, echo and crosstalk

cancellation, data recovery, and error correction at a

gigabit per second data rate. The device achieves

robust performance in noisy environments with very low

power dissipation.

Requires only two supplies: 2.5V and 1.0V (with

1.2V option for the 1.0V supply)

•

I/Os are 3.3V tolerant

Low power dissipation Pave = 0.75W

117-Pin TFBGA, 96-Pin BCC, and 128 PQFP

package options

The 88E1111 device is offered in three different pack-

age options including a 117-Pin TFBGA, a 96-pin BCC

featuring a body size of only 9 x 9 mm, and a 128 PQFP

package.

•

117-Pin TFBGA and 96-Pin BCC packages avail-

able in Commercial or Industrial grade

RoHS 6/6 compliant packages available

Doc. No. MV-S105540-00, Rev. --

Page 3

March 4, 2009, Advance

Document Classification: Proprietary Information

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

M

a

g

n

e

t

i

Media Types:

- 10BASE-T

- 100BASE-TX

- 1000BASE-T

88E1111

Device

10/100/1000 Mbps

Ethernet MAC

RJ-45

MAC Interface Options

- GMII/MII

- TBI

c

s

- RGMII

- RTBI

- SGMII

- Serial Interface

88E1111 Device used in Copper Application

88E1111

Device

10/100/1000 Mbps

Ethernet MAC

Fiber

Optics

Media Types:

- 1000BASE-X

Serial

MAC Interface Options

Interface

- GMII/MII

- RGMII

88E1111 Device used in Fiber Application

(Effective SGMII MAC)

88E1111

Device

Gigabit Ethernet

MAC

3-Speed

SFP

Serial Interface

- 4-pin SGMIII

MAC Interface Options

- GMII

- RGMII

88E1111 RGMII/GMII MAC to SGMII MAC Conversion

Doc. No. MV-S105540-00, Rev. --

Page 4

March 4, 2009, Advance

Document Classification: Proprietary Information

Table of Contents

1.1 117-Pin TFBGA Package................................................................................................6

1.2 96-Pin BCC Package .....................................................................................................7

1.3 128-Pin PQFP Package ..................................................................................................8

1.4 Pin Description...............................................................................................................9

1.4.1 Pin Type Definitions............................................................................................................ 9

1.5 I/O State at Various Test or Reset Modes ..................................................................33

1.6 117-Pin TFBGA Pin Assignment List - Alphabetical by Signal Name .....................34

1.7 96-Pin BCC Pin Assignment List - Alphabetical by Signal Name............................36

1.8 128-Pin PQFP Pin Assignment List - Alphabetical by Signal Name........................38

2.1 117-pin TFBGA Package..............................................................................................40

2.2 96-pin BCC Package - Top View .................................................................................42

2.3 96-Pin BCC Package - Bottom View ...........................................................................43

2.4 128-Pin PQFP Package ................................................................................................44

3.1 Ordering Part Numbers and Package Markings........................................................45

3.1.1 RoHS 5/6 Compliant Marking Examples .......................................................................... 46

3.1.2 RoHS 6/6 Compliant Marking Examples .......................................................................... 49

March 4, 2009, Advance

Doc. No. MV-S105540-00, Rev. --

Page 5

Document Classification: Proprietary Information

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

Section 1. Signal Description

The 88E1111 device is a 10/100/1000BASE-T/1000BASE-X Gigabit Ethernet transceiver.

1.1 117-Pin TFBGA Package

Figure 1: 88E1111 Device 117-Pin TFBGA Package (Top View)

1

2

3

4

5

S_CLK+

CRS

RXD7

VSS

6

S_CLK-

COL

7

S_OUT+

AVDD

DVDD

VDDOH

CONFIG[3]

VSSC

DVDD

NC

8

9

LED_

A

B

C

D

E

F

RXD5

RX_DV

RX_CLK

TX_CLK

TX_EN

TXD0

NC

RXD6

RXD0

VDDO

RX_ER

GTX_CLK

TX_ER

TXD1

S_IN+

RXD3

RXD2

RXD1

DVDD

TXD2

TXD5

DVDD

RESETn

MDC

S_IN-

VDDO

RXD4

VSS

S_OUT-

A

B

C

D

E

F

LINK1000

LED_

VDDOH

LED_RX

LED_TX

CONFIG[1]

CONFIG[4]

CONFIG[5]

XTAL1

LINK100

LED_

DVDD

VSS

LINK10

CONFIG[0]

LED_

VSS

DUPLEX

VSS

CONFIG[2]

CONFIG[6]

G

H

J

VSS

G

H

J

SEL_

TXD4

TXD6

VDDO

INTn

TXD3

VSS

FREQ

TXD7

VSS

VDDOH

TDO

XTAL2

K

L

125CLK

VDDOX

RSET

MDI[0]-

2

VSS

VDDOX

TCK

K

L

COMA

AVDD

MDI[1]-

4

VSS

TDI

TMS

M

N

MDIO

MDI[0]+

1

AVDD

MDI[1]+

3

HSDAC+

AVDD

5

HSDAC-

MDI[2]+

6

AVDD

MDI[2]-

7

AVDD

MDI[3]+

8

TRSTn

M

N

MDI[3]-

9

Figure 2: Pin A1 Location

Pin A1 location

Doc. No. MV-S105540-00, Rev. --

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March 4, 2009, Advance

Document Classification: Proprietary Information

Signal Description

96-Pin BCC Package

1.2 96-Pin BCC Package

Figure 3: 88E1111 Device 96-Pin BCC Package (Top View)

LED_LINK

100

TCK

49

74

VDDOX

48

46

44

42

40

S_OUT-

TRSTn

AVDD

75

47

45

43

41

39

37

35

33

31

29

27

25

LED_LINK

10

TMS

TDI

76

VSS

0

S_OUT+

77

79

81

83

85

87

89

91

93

AVDD

78

S_CLK+

MDI[3]-

MDI[2]-

S_CLK-

S_IN+

CRS

MDI[3]+

AVDD

80

S_IN-

COL

82

84

86

88

90

92

94

MDI[2]+

HSDAC-

AVDD

38

DVDD

RXD6

RXD5

RXD3

RXD2

HSDAC+

RXD7

VDDO

RXD4

RXD1

RX_DV

36

88E1111 - CAA

AVDD

MDI[1]-

AVDD

34

MDI[1]+

32

MDI[0]-

RSET

30

MDI[0]+

RESETn

VDDOX

28

RXD0

VDDO

COMA

MDC

95

96

26

March 4, 2009, Advance

Doc. No. MV-S105540-00, Rev. --

Page 7

Document Classification: Proprietary Information

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

1.3 128-Pin PQFP Package

Figure 4: 88E1111 Device 128-Pin PQFP Package (Top View)

VSS

AVDD

S_OUT-

VSS

S_OUT+

VSS

S_CLK-

S_CLK+

VSS

S_IN-

S_IN+

COL

CRS

VSS

DVDD

VSS

RXD7

RXD6

VDDO

RXD5

RXD4

RXD3

RXD2

VSS

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

AVDD

VSS

MDI[3]-

MDI[3]+

VSS

AVDD

VSS

MDI[2]-

MDI[2]+

VSS

HSDAC-

HSDAC+

AVDD

VSS

NC

AVDD

VSS

MDI[1]-

MDI[1]+

VSS

AVDD

VSS

MDI[0]-

MDI[0]+

VSS

88E1111 - RCJ

Top View

RXD1

RSET

Doc. No. MV-S105540-00, Rev. --

Page 8

March 4, 2009, Advance

Document Classification: Proprietary Information

Signal Description

Pin Description

1.4 Pin Description

1.4.1 Pin Type Definitions

Pin Type

Definition

H

Input with hysteresis

Input and output

Input only

I/O

I

O

Output only

PU

PD

D

Internal pull up

Internal pull down

Open drain output

Tri-state output

DC sink capability

Z

mA

March 4, 2009, Advance

Doc. No. MV-S105540-00, Rev. --

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Document Classification: Proprietary Information

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

Table 1:

Media Dependent Interface

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

N1

N2

29

31

41

42

MDI[0]+

MDI[0]-

I/O, D

Media Dependent Interface[0].

In 1000BASE-T mode in MDI configuration,

MDI[0]± correspond to BI_DA±.

In MDIX configuration, MDI[0]± correspond

to BI_DB±.

In 100BASE-TX and 10BASE-T modes in

MDI configuration, MDI[0]± are used for the

transmit pair. In MDIX configuration,

MDI[0]± are used for the receive pair.

MDI[0]± should be tied to ground if not used.

Media Dependent Interface[1].

N3

N4

33

34

46

47

MDI[1]+

MDI[1]-

I/O, D

In 1000BASE-T mode in MDI configuration,

MDI[1]± correspond to BI_DB±.

In MDIX configuration, MDI[1]± correspond

to BI_DA±.

In 100BASE-TX and 10BASE-T modes in

MDI configuration, MDI[1]± are used for the

receive pair. In MDIX configuration, MDI[1]±

are used for the transmit pair.

MDI[1]± should be tied to ground if not used.

Doc. No. MV-S105540-00, Rev. --

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March 4, 2009, Advance

Document Classification: Proprietary Information

Signal Description

Pin Description

Table 1:

Media Dependent Interface (Continued)

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

N6

N7

39

41

56

57

MDI[2]+

MDI[2]-

I/O, D

Media Dependent Interface[2].

In 1000BASE-T mode in MDI configuration,

MDI[2]± correspond to BI_DC±.

In MDIX configuration, MDI[2]± corresponds

to BI_DD±.

In 100BASE-TX and 10BASE-T modes,

MDI[2]± are not used.

MDI[2]± should be tied to ground if not used.

Media Dependent Interface[3].

N8

N9

42

43

61

62

MDI[3]+

MDI[3]-

I/O, D

In 1000BASE-T mode in MDI configuration,

MDI[3]± correspond to BI_DD±.

In MDIX configuration, MDI[3]± correspond

to BI_DC±.

In 100BASE-TX and 10BASE-T modes,

MDI[3]± are not used.

MDI[3]± should be tied to ground if not used.

March 4, 2009, Advance

Doc. No. MV-S105540-00, Rev. --

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Document Classification: Proprietary Information

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

The GMII interface supports both 1000BASE-T and 1000BASE-X modes of operation. The GMII interface pins are

also used for the TBI interface. See Table 3 for TBI pin definitions. The MAC interface pins are 3.3V tolerant.

Table 2:

GMII/MII Interfaces

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

E2

8

14

GTX_CLK

TX_CLK

I

GMII Transmit Clock. GTX_CLK provides a

125 MHz clock reference for TX_EN,

TX_ER, and TXD[7:0]. This clock can be

stopped when the device is in 10/100BASE-

T modes, and also during Auto-Negotiation.

D1

4

10

O, Z

MII Transmit Clock. TX_CLK provides a 25

MHz clock reference for TX_EN, TX_ER,

and TXD[3:0] in 100BASE-TX mode, and a

2.5 MHz clock reference in 10BASE-T

mode.

TX_CLK provides a 25 MHz, 2.5 MHz, or 0

MHz clock during 1000 Mbps Good Link,

Auto-Negotiation, and Link Lost states

depending on the setting of register 20.6:4.

The 2.5 MHz clock is the default rate, which

may be programmed to another frequency

by writing to register 20.6:4.

E1

9

16

TX_EN

I

GMII and MII Transmit Enable. In GMII/MII

mode when TX_EN is asserted, data on

TXD[7:0] along with TX_ER is encoded and

transmitted onto the cable.

TX_EN is synchronous to GTX_CLK, and

synchronous to TX_CLK in 100BASE-TX

and 10BASE-T modes.

F2

7

13

TX_ER

I

GMII and MII Transmit Error. In GMII/MII

mode when TX_ER and TX_EN are both

asserted, the transmit error symbol is trans-

mitted onto the cable. When TX_ER is

asserted with TX_EN de-asserted, carrier

extension symbol is transmitted onto the

cable.

TX_ER is synchronous to GTX_CLK, and

synchronous to TX_CLK in 100BASE-TX

and 10BASE-T modes.

Doc. No. MV-S105540-00, Rev. --

Page 12

Document Classification: Proprietary Information

March 4, 2009, Advance

Signal Description

Pin Description

Table 2:

GMII/MII Interfaces (Continued)

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

J2

J1

20

19

18

17

16

14

12

11

29

28

26

25

24

20

19

18

TXD[7]

TXD[6]

TXD[5]

TXD[4]

TXD[3]/TXD[3]

TXD[2]/TXD[2]

TXD[1]/TXD[1]

TXD[0]/TXD[0]

I

GMII and MII Transmit Data. In GMII mode,

TXD[7:0] present the data byte to be trans-

mitted onto the cable in 1000BASE-T mode.

H3

H1

H2

G3

G2

F1

In MII mode, TXD[3:0] present the data nib-

ble to be transmitted onto the cable in

100BASE-TX and 10BASE-T modes.

TXD[7:4] are ignored in these modes, but

should be driven either high or low. These

pins must not float.

TXD[7:0] are synchronous to GTX_CLK, and

synchronous to TX_CLK in 100BASE-TX

and 10BASE-T modes.

Inputs TXD[7:4] should be tied low if not

used (e.g., RGMII mode).

C1

2

7

RX_CLK

O, Z

GMII and MII Receive Clock. RX_CLK pro-

vides a 125 MHz clock reference for RX_DV,

RX_ER, and RXD[7:0] in 1000BASE-T

mode, a 25 MHz clock reference in

100BASE-TX mode, and a 2.5 MHz clock

reference in 10BASE-T mode.

TX_TCLK comes from the RX_CLK pins

used in jitter testing. Refer to Register 9 for

jitter test modes.

B1

D2

94

4

8

RX_DV

RX_ER

O, Z

GMII and MII Receive Data Valid. When

RX_DV is asserted, data received on the

cable is decoded and presented on

RXD[7:0] and RX_ER.

RX_DV is synchronous to RX_CLK.

3

GMII and MII Receive Error. When RX_ER

and RX_DV are both asserted, the signals

indicate an error symbol is detected on the

cable.

When RX_ER is asserted with RX_DV de-

asserted, a false carrier or carrier extension

symbol is detected on the cable.

RX_ER is synchronous to RX_CLK.

March 4, 2009, Advance

Doc. No. MV-S105540-00, Rev. --

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Document Classification: Proprietary Information

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

Table 2:

GMII/MII Interfaces (Continued)

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

C5

A2

A1

C4

B3

C3

D3

B2

86

87

89

90

91

93

92

95

120

121

123

124

125

126

128

3

RXD[7]

RXD[6]

RXD[5]

RXD[4]

RXD[3]/RXD[3]

RXD[2]/RXD[2]

RXD[1]/RXD[1]

RXD[0]/RXD[0]

O, Z

GMII and MII Receive Data. Symbols

received on the cable are decoded and pre-

sented on RXD[7:0] in 1000BASE-T mode.

In MII mode, RXD[3:0] are used in

100BASE-TX and 10BASE-T modes. In MII

mode, RXD[7:4] are driven low.

RXD[7:0] is synchronous to RX_CLK.

B5

84

115

CRS

GMII and MII Carrier Sense. CRS asserts

when the receive medium is non-idle. In half-

duplex mode, CRS is also asserted during

transmission. CRS assertion during half-

duplex transmit can be disabled by program-

ming register 16.11 to 0.

CRS is asynchronous to RX_CLK,

GTX_CLK, and TX_CLK.

B6

83

114

COL

GMII and MII Collision. In 10/100/

1000BASE-T full-duplex modes, COL is

always low. In 10/100/1000BASE-T half-

duplex modes, COL asserts only when both

the transmit and receive media are non-idle.

In 10BASE-T half-duplex mode, COL is

asserted to indicate signal quality error

(SQE). SQE can be disabled by clearing reg-

ister 16.2 to zero.

COL is asynchronous to RX_CLK,

GTX_CLK, and TX_CLK.

Doc. No. MV-S105540-00, Rev. --

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Document Classification: Proprietary Information

March 4, 2009, Advance

Signal Description

Pin Description

The TBI interface supports 1000BASE-T mode of operation. The TBI interface uses the same pins as the GMII

interface. The MAC interface pins are 3.3V tolerant.

Table 3:

TBI Interface

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

E2

8

14

GTX_CLK/

TBI_TXCLK

I

TBI Transmit Clock. In TBI mode, GTX_CLK

is used as TBI_TXCLK. TBI_TXCLK is a 125

MHz transmit clock.

TBI_TXCLK provides a 125 MHz clock refer-

ence for TX_EN, TX_ER, and TXD[7:0].

D1

4

10

TX_CLK/RCLK1 O, Z

TBI 62.5 MHz Receive Clock- even code

group. In TBI mode, TX_CLK is used as

RCLK1.

J2

J1

20

19

18

17

16

14

12

11

29

28

26

25

24

20

19

18

TXD[7]

TXD[6]

TXD[5]

TXD[4]

TXD[3]

TXD[2]

TXD[1]

TXD[0]

I

TBI Transmit Data. TXD[7:0] presents the

data byte to be transmitted onto the cable.

H3

H1

H2

G3

G2

F1

TXD[9:0] are synchronous to GTX_CLK.

Inputs TXD[7:4] should be tied low if not

used (e.g., RTBI mode).

E1

9

16

TX_EN/

TXD8

I

TBI Transmit Data. In TBI mode, TX_EN is

used as TXD8.

TXD[9:0] are synchronous to GTX_CLK.

F2

7

13

TX_ER/

TXD9

TBI Transmit Data. In TBI mode, TX_ER is

used as TXD9.

TXD[9:0] are synchronous to GTX_CLK.

TX_ER should be tied low if not used (e.g.,

RTBI mode).

C1

2

7

RX_CLK/

RCLK0

O, Z

TBI 62.5 MHz Receive Clock- odd code

group. In the TBI mode, RX_CLK is used

as RCLK0.

C5

A2

A1

C4

B3

C3

D3

B2

86

87

89

90

91

93

92

95

120

121

123

124

125

126

128

3

RXD[7]

RXD[6]

RXD[5]

RXD[4]

RXD[3]

RXD[2]

RXD[1]

RXD[0]

TBI Receive Data code group [7:0]. In the

TBI mode, RXD[7:0] present the data byte to

be transmitted to the MAC. Symbols

received on the cable are decoded and pre-

sented on RXD[7:0].

RXD[7:0] are synchronous to RCLK0 and

RCLK1.

B1

94

4

RX_DV/

RXD8

O, Z

TBI Receive Data code group bit 8. In the

TBI mode, RX_DV is used as RXD8.

RXD[9:0] are synchronous to RCLK0 and

RCLK1.

March 4, 2009, Advance

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Page 15

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

Table 3:

TBI Interface (Continued)

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

D2

3

8

RX_ER/

RXD9

O, Z

TBI Receive Data code group bit 9. In the

TBI mode, RX_ER is used as RXD9.

RXD[9:0] are synchronous to RCLK0 and

RCLK1.

B5

B6

84

83

115

114

CRS/

COMMA

O, Z

I

TBI Valid Comma Detect. In the TBI mode,

CRS is used as COMMA.

COL/LPBK

TBI Mode Loopback. In the TBI mode, COL

is used to indicate loopback on the TBI.

When a “0 - 1" transition is sampled on this

pin, bit 0.14 is set to 1.

When a “1 - 0" is sampled on this pin, bit

0.14 is reset to 0.

If this feature is not used, the COL pin

should be driven low on the board. This pin

should not be left floating in TBI mode.

Doc. No. MV-S105540-00, Rev. --

Page 16

Document Classification: Proprietary Information

March 4, 2009, Advance

Signal Description

Pin Description

The RGMII interface supports 10/100/1000BASE-T and 1000BASE-X modes of operation.The RGMII interface

pins are also used for the RTBI interface. See Table 5 for RTBI pin definitions. The MAC interface pins are 3.3V

tolerant.

Table 4:

RGMII Interface

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

E2

8

14

GTX_CLK/

TXC

I

RGMII Transmit Clock provides a 125 MHz,

25 MHz, or 2.5 MHz reference clock with ±

50 ppm tolerance depending on speed. In

RGMII mode, GTX_CLK is used as TXC.

H2

G3

G2

F1

16

14

12

11

24

20

19

18

TXD[3]/TD[3]

TXD[2]/TD[2]

TXD[1]/TD[1]

TXD[0]/TD[0]

I

RGMII Transmit Data. In RGMII mode,

TXD[3:0] are used as TD[3:0].

In RGMII mode, TXD[3:0] run at double data

rate with bits [3:0] presented on the rising

edge of GTX_CLK, and bits [7:4] presented

on the falling edge of GTX_CLK. In this

mode, TXD[7:4] are ignored.

In RGMII 10/100BASE-T modes, the trans-

mit data nibble is presented on TXD[3:0] on

the rising edge of GTX_CLK.

E1

9

16

TX_EN/

TX_CTL

I

RGMII Transmit Control. In RGMII mode,

TX_EN is used as TX_CTL. TX_EN is pre-

sented on the rising edge of GTX_CLK.

A logical derivative of TX_EN and TX_ER is

presented on the falling edge of GTX_CLK.

C1

B1

2

7

4

RX_CLK/

RXC

O, Z

RGMII Receive Clock provides a 125 MHz,

25 MHz, or 2.5 MHz reference clock with ±

50 ppm tolerance derived from the received

data stream depending on speed. In RGMII

mode, RX_CLK is used as RXC.

94

RX_DV/

RX_CTL

RGMII Receive Control. In RGMII mode,

RX_DV is used as RX_CTL. RX_DV is pre-

sented on the rising edge of RX_CLK.

A logical derivative of RX_DV and RX_ER is

presented on the falling edge of RX_CLK.

B3

C3

D3

B2

91

93

92

95

125

126

128

3

RXD[3]/RD[3]

RXD[2]/RD[2]

RXD[1]/RD[1]

RXD[0]/RD[0]

O, Z

RGMII Receive Data. In RGMII mode,

RXD[3:0] are used as RD[3:0]. In RGMII

mode, RXD[3:0] run at double data rate with

bits [3:0] presented on the rising edge of

RX_CLK, and bits [7:4] presented on the fall-

ing edge of RX_CLK. In this mode, RXD[7:4]

are ignored.

In RGMII 10/100BASE-T modes, the receive

data nibble is presented on RXD[3:0] on the

rising edge of RX_CLK.

RXD[3:0] are synchronous to RX_CLK.

March 4, 2009, Advance

Doc. No. MV-S105540-00, Rev. --

Document Classification: Proprietary Information

Page 17

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

The RTBI interface supports 1000BASE-T mode of operation. The RTBI interface uses the same pins as the

RGMII interface. The MAC interface pins are 3.3V tolerant.

Table 5:

RTBI Interface

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

E2

8

14

GTX_CLK/

TXC

I

RGMII Transmit Clock provides a 125 MHz

reference clock with ± 50 ppm tolerance. In

RTBI mode, GTX_CLK is used as TXC.

H2

G3

G2

F1

16

14

12

11

24

20

19

18

TXD[3]/TD[3]

TXD[2]/TD[2]

TXD[1]/TD[1]

TXD[0]/TD[0]

I

RTBI Transmit Data.

In RTBI mode, TXD[3:0] are used as

TD[3:0]. TD[3:0] run at double data rate with

bits [3:0] presented on the rising edge of

GTX_CLK, and bits [8:5] presented on the

falling edge of GTX_CLK. In this mode,

TXD[7:4] are ignored.

E1

C1

9

2

16

TX_EN/

TD4_TD9

I

RTBI Transmit Data.

In RTBI mode, TX_EN is used as TD4_TD9.

TD4_TD9 runs at a double data rate with bit

4 presented on the rising edge of GTX_CLK,

and bit 9 presented on the falling edge of

GTX_CLK.

7

RX_CLK/

RXC

O, Z

RTBI Receive Clock provides a 125 MHz ref-

erence clock with ± 50 ppm tolerance

derived from the received data stream. In

RTBI mode, RX_CLK is used as RXC.

B3

C3

D3

B2

91

93

92

95

125

126

128

3

RXD[3]/RD[3]

RXD[2]/RD[2]

RXD[1]/RD[1]

RXD[0]/RD[0]

RTBI Receive Data.

In RTBI mode, RXD[3:0] are used as

RD[3:0]. RD[3:0] runs at double data rate

with bits [3:0] presented on the rising edge of

RX_CLK, and bits [8:5] presented on the fall-

ing edge of RX_CLK. In this mode, RXD[7:4]

are ignored.

B1

94

4

RX_DV/

O, Z

RTBI Receive Data.

RD4_RD9

In RTBI mode, RX_DV is used as

RD4_RD9. RD4_RD9 runs at a double data

rate with bit 4 presented on the rising edge

of RX_CLK, and bit 9 presented on the fall-

ing edge of RX_CLK.

Doc. No. MV-S105540-00, Rev. --

Page 18

Document Classification: Proprietary Information

March 4, 2009, Advance

Signal Description

Pin Description

Table 6:

SGMII Interface

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

A3

A4

82

81

113

112

S_IN+

S_IN-

I

SGMII Transmit Data. 1.25 GBaud input -

Positive and Negative.

Input impedance on the S_IN± pins may be

programmed for 50 ohm or 75 ohm imped-

ance by setting register 26.6. The input

impedance default setting is determined by

the 75/50 OHM configuration pin.

A5

A6

79

80

110

109

S_CLK+

S_CLK-

I/O

SGMII 625 MHz Receive Clock.

For Serial Interface modes

(HWCFG_MODE[3:0] = 1x00) the S_CLK±

pins become Signal Detect± (SD±) inputs.

A7

A8

77

75

107

105

S_OUT+

S_OUT-

O, Z

SGMII Receive Data. 1.25 GBaud output -

Positive and Negative.

Output impedance on the S_OUT± pins may

be programmed for 50 ohm or 75 ohm

impedance by setting register 26.5. Output

amplitude can be adjusted via register

26.2:0. The output impedance default setting

is determined by the 75/50 OHM configura-

tion pin.

March 4, 2009, Advance

Doc. No. MV-S105540-00, Rev. --

Document Classification: Proprietary Information

Page 19

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

Table 7:

1.25 GHz Serial High Speed Interface

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

A3

A4

82

81

113

112

S_IN+

S_IN-

I

1.25 GHz input - Positive and Negative.

When this interface is used as a MAC inter-

face, the MAC transmitter’s positive output

connects to the S_IN+. The MAC transmit-

ter’s negative output connects to the S_IN-.

When this interface is used as a fiber inter-

face, the fiber-optic transceiver’s positive

output connects to the S_IN+. The fiber-optic

transceiver’s negative output connects to the

S_IN-.

Input impedance on the S_IN± pins may be

programmed for 50 ohm or 75 ohm imped-

ance by setting register 26.6. The input

impedance default setting is determined by

the 75/50 OHM configuration pin.

A5

A6

79

80

110

109

S_CLK+/SD+

S_CLK-/SD-

I

Signal Detect input.

For Serial Interface modes the S_CLK± pins

become Signal Detect± (SD±) inputs.

A7

A8

77

75

107

105

S_OUT+

S_OUT-

O, Z

1.25 GHz output − Positive and Negative.

When this interface is used as a MAC inter-

face, S_OUT+ connects to the MAC

receiver’s positive input. S_OUT- connects

to the MAC receiver’s negative input.

When this interface is used as a fiber inter-

face, S_OUT+ connects to the fiber-optic

transceiver’s positive input. S_OUT- con-

nects to the fiber-optic transceiver’s negative

input.

Output impedance on the S_OUT± pins may

be programmed for 50 ohm or 75 ohm

impedance by setting register 26.5. Output

amplitude can be adjusted via register

26.2:0. The output impedance default setting

is determined by the 75/50 OHM configura-

tion pin.

B3

91

125

RXD[3]

O, Z

Serial MAC interface Copper Link Status[1]

connection.

1 = Copper link up

0 = Copper link down

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Document Classification: Proprietary Information

March 4, 2009, Advance

Signal Description

Pin Description

Table 7:

1.25 GHz Serial High Speed Interface (Continued)

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

C3

93

126

RXD[2]

RXD[1]

O, Z

Serial MAC interface Copper Link Status[0]

connection.

1 = Copper link down

0 = Copper link up

D3

B2

92

95

128

Serial MAC interface PHY_SIGDET[1] con-

nection.

1 = S_OUT± valid code groups according to

clause 36.

0 = S_OUT± invalid

3

RXD[0]

O, Z

Serial MAC interface PHY_SIGDET[0] con-

nection.

1 = S_OUT± invalid

0 = S_OUT± valid code groups according to

clause 36

March 4, 2009, Advance

Doc. No. MV-S105540-00, Rev. --

Document Classification: Proprietary Information

Page 21

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

Table 8:

Management Interface and Interrupt

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

L3

25

35

MDC

MDIO

INTn

I

MDC is the management data clock refer-

ence for the serial management interface. A

3.3V

Tolerant continuous clock stream is not expected.

The maximum frequency supported is 8.3

MHz.

M1

L1

24

23

33

32

I/O

3.3V

MDIO is the management data. MDIO

transfers management data in and out of the

Tolerant device synchronously to MDC. This pin

requires a pull-up resistor in a range from

1.5 kohm to 10 kohm.

D

The polarity of the INTn pin may be pro-

grammed at hardware reset by setting the

INT_POL bit.

Polarity:

0 = Active High

1 = Active Low

Table 9:

Two-Wire Serial Interface

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

L3

25

35

MDC/SCL

I

Two-Wire Serial Interface (TWSI) serial

clock line. When the 88E1111 device is con-

nected to the bus, MDC connects to the

serial clock line (SCL).

Data is input on the rising edge of SCL, and

output on the falling edge.

M1

24

33

MDIO/SDA

I/O

TWSI serial data line. When the 88E1111

device is connected to the bus, MDIO con-

nects to the serial data line (SDA). This pin is

open-drain and may be wire-ORed with any

number of open-drain devices.

Doc. No. MV-S105540-00, Rev. --

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Document Classification: Proprietary Information

March 4, 2009, Advance

Signal Description

Pin Description

Table 10: LED Interface

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

C8

76

100

LED_LINK10

O, mA

Parallel LED output for 10BASE-T link or

speed. This active low LED pin may be pro-

grammed in direct drive or combined LED

modes by programming register LED_LINK

Control register 24.4:3.

In direct drive LED mode, this pin indicates

10 Mbps link up or down.

In combined LED mode, the output from

LED_LINK10, LED_LINK100, and

LED_LINK1000 must be read together to

determine link and speed status.

LED_LINK10 is a multi-function pin used to

configure the 88E1111 device at the de-

assertion of hardware reset.

B8

74

99

LED_LINK100

O, mA

Parallel LED output for 100BASE-TX link or

speed. This active low LED pin may be pro-

grammed in direct drive or combined LED

modes by programming register LED_LINK

Control register 24.4:3.

In direct drive LED mode, this pin indicates

100 Mbps link up or down.

In combined LED mode, the output from

LED_LINK10, LED_LINK100, and

LED_LINK1000 must be read together to

determine link and speed status.

LED_LINK100 is a multi-function pin used to

configure the 88E1111 device at the de-

assertion of hardware reset.

A9

73

98

LED_LINK1000 O, mA

Parallel LED output for 1000BASE-T link/

speed or link indicator. This active low LED

pin may be programmed in direct drive or

combined LED modes by programming reg-

ister LED_LINK Control register 24.4:3.

In direct drive LED mode, this pin indicates

1000 Mbps link up or down.

In combined LED mode, the output from

LED_LINK1000 indicates link status.

LED_LINK1000 is a multi-function pin used

to configure the 88E1111 device at the de-

assertion of hardware reset.

March 4, 2009, Advance

Doc. No. MV-S105540-00, Rev. --

Document Classification: Proprietary Information

Page 23

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

Table 10: LED Interface (Continued)

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

E8

70

95

LED_DUPLEX

O, mA

Parallel LED duplex or duplex/collision

modes. The LED_DUPLEX pin may be pro-

grammed to Mode 1 or Mode 2 by setting

register bit 24.2.

Mode 1

Low = Full-duplex

High = Half-duplex

Blink = Collision

Mode 2

Low = Full-duplex

High = Half-duplex

Mode 3

Low = Fiber Link up

High = Fiber Link down

LED_DUPLEX is a multi-function pin used to

configure the 88E1111 device at the de-

assertion of hardware reset.

Doc. No. MV-S105540-00, Rev. --

Page 24

Document Classification: Proprietary Information

March 4, 2009, Advance

Signal Description

Pin Description

Table 10: LED Interface (Continued)

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

C9

69

92

LED_RX

O, mA

Parallel LED Receive Activity or Receive

Activity/Link modes. LED_RX may be pro-

grammed to Mode 1 or Mode 2 by setting

register bit 24.1.

Mode 1

Low = Receiving

High = Not receiving

Mode 2

Low = Link up

High = Link down

Blink = Receiving

LED_RX is a multi-function pin used to con-

figure the 88E1111 device at the de-asser-

tion of hardware reset.

D9

68

91

LED_TX

O, mA

Parallel LED Transmit Activity or RX/TX

Activity/Link modes. LED_TX may be pro-

grammed to Mode 1 or Mode 2 by setting

register bit 24.0.

Mode 1

Low = Transmitting

High = Not transmitting

Mode 2

Low = Link up

High = Link down

Blink = Transmitting or receiving

LED_TX is a multi-function pin used to con-

figure the 88E1111 device at the de-asser-

tion of hardware reset.

March 4, 2009, Advance

Doc. No. MV-S105540-00, Rev. --

Document Classification: Proprietary Information

Page 25

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

Table 11: JTAG Interface

117-TFBGA 96-BCC 128-PQFP Pin Type

Description

Pin #

Name

L7

44

67

TDI

I, PU

Boundary scan test data input.

TDI contains an internal 150 kohm pull-up

resistor.

L8

L9

M9

46

49

47

69

70

68

TMS

TCK

Boundary scan test mode select input.

TMS contains an internal 150 kohm pull-up

resistor.

Boundary scan test clock input.

TCK contains an internal 150 kohm pull-up

resistor.

TRSTn

Boundary scan test reset input. Active low.

TRSTn contains an internal 150 kohm pull-

up resistor as per the 1149.1 specification.

After power up, the JTAG state machine

should be reset by applying a low signal on

this pin, or by keeping TMS high and apply-

ing 5 TCK pulses, or by pulling this pin low

by a 4.7 kohm resistor.

K8

50

72

TDO

O, Z

Boundary scan test data output.

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Page 26

March 4, 2009, Advance

Document Classification: Proprietary Information

Signal Description

Pin Description

Table 12: Clock/Configuration/Reset/I/O

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

K2

22

31

125CLK

O

Clock 125. A generic 125 MHz clock refer-

ence generated for use on the MAC device.

This output can be disabled via DIS_125

through the CONFIG[3] pin.

D8

65

88

CONFIG[0]

I

CONFIG[0] pin configures PHY_ADR[2:0]

bits of the physical address.

Each LED pin is hardwired to a constant

value. The values associated to the CON-

FIG[0] pin are latched at the de-assertion of

hardware reset.

CONFIG[0] pin must be tied to one of the

pins based on the configuration options

selected. They should not be left floating.

For the Two-Wire Serial Interface (TWSI)

device address, the lower 5 bits, which are

PHYADR[4:0], are latched during hardware

reset, and the device address bits [6:5] are

fixed at ‘10’.

E9

64

87

CONFIG[1]

I

CONFIG[1] pin configures PHY_ADR[4:3]

and ENA_PAUSE options.

Each LED pin is hardwired to a constant

value. The values associated to the CON-

FIG[1] pin are latched at the de-assertion of

hardware reset.

CONFIG[1] pin must be tied to one of the

pins based on the configuration options

selected. They should not be left floating.

For the TWSI device address, the lower 5

bits, which are PHYADR[4:0], are latched

during hardware reset, and the device

address bits [6:5] are fixed at ‘10’.

F8

63

86

CONFIG[2]

I

CONFIG[2] pin configures ANEG[3:1] bits.

Each LED pin is hardwired to a constant

value. The values associated to the CON-

FIG[2] pin are latched at the de-assertion of

hardware reset.

CONFIG[2] pin must be tied to one of the

pins based on the configuration options

selected. They should not be left floating.

March 4, 2009, Advance

Doc. No. MV-S105540-00, Rev. --

Document Classification: Proprietary Information

Page 27

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

Table 12: Clock/Configuration/Reset/I/O (Continued)

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

G7

61

82

CONFIG[3]

I

CONFIG[3] pin configures ANEG[0],

ENA_XC, and DIS_125 options.

Each LED pin is hardwired to a constant

value. The values associated to the CON-

FIG[3] pin are latched at the de-assertion of

hardware reset.

CONFIG[3] pin must be tied to one of the

pins based on the configuration options

selected. They should not be left floating.

F9

60

59

81

80

CONFIG[4]

CONFIG[5]

I

CONFIG[4] pin configures

HWCFG_MODE[2:0] options.

G9

CONFIG[5] pin configures DIS_FC,

DIS_SLEEP, and HWCFG_MODE[3]

options.

G8

H8

58

56

79

77

CONFIG[6]

SEL_FREQ

I

CONFIG[6] pin configures SEL_TWSI,

INT_POL, and 75/50 OHM options.

Frequency Selection for XTAL1 input

NC = Selects 25 MHz clock input.

Tied low = Selects 125 MHz clock input.

Internally divided to 25 MHz. SEL_FREQ is

internally pulled up.

H9

J9

55

54

76

75

XTAL1

XTAL2

I

Reference Clock. 25 MHz ± 50 ppm or 125

MHz ± 50 ppm oscillator input. PLL clocks

are not recommended.

0

Reference Clock. 25 MHz ± 50 ppm toler-

ance crystal reference. When the XTAL2 pin

is not connected, it should be left floating.

There is no option for a 125 MHz crystal.

See “Crystal Oscillator” Application Note for

details.

Doc. No. MV-S105540-00, Rev. --

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March 4, 2009, Advance

Signal Description

Pin Description

Table 12: Clock/Configuration/Reset/I/O (Continued)

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

K3

28

36

RESETn

I

Hardware reset. Active low. XTAL1 must be

active for a minimum of 10 clock cycles

before the rising edge of RESETn. RESETn

must be pulled high for normal operation.

L4

27

37

COMA

I

COMA disables all active circuitry to draw

absolute minimum power. The COMA power

mode can be activated by asserting high on

the COMA pin. To deactivate the COMA

power mode, tie the COMA pin low. Upon

deactivating COMA mode, the 88E1111

device will continue normal operation.

The COMA power mode cannot be enabled

as long as hardware reset is enabled.

In COMA mode, the PHY cannot wake up on

its own by detecting activity on the CAT 5

cable.

March 4, 2009, Advance

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Page 29

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

Table 13: Test

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

M5

M6

37

38

53

54

HSDAC+

HSDAC-

Analog

PD

Test pins. These pins should be left floating

but brought out for probing.

Table 14: Control and Reference

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

M2

30

39

RSET

Analog

I

Constant voltage reference. External 5.0

kohm 1% resistor connection to VSS

required for each pin.

Doc. No. MV-S105540-00, Rev. --

Page 30

Document Classification: Proprietary Information

March 4, 2009, Advance

Signal Description

Pin Description

Table 15: Power & Ground

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

B7

32

35

36

40

45

78

44

49

52

59

64

104

AVDD

Power

Analog Power. 2.5V.

M3

M4

M7

M8

N5

C6

C7

D7

E3

E7

F3

J3

1

6

2

6

DVDD

Power

Digital Power. 1.0V (Instead of 1.0V, 1.2V

can be used).

10

15

57

62

67

71

85

12

17

23

27

78

85

90

96

117

118

J7

B9

F7

J8

52

66

72

73

89

97

VDDOH

Power

2.5V Power Supply for LED and CONFIG

pins.

K9

L2

26

48

34

71

VDDOX

VDDO

Power

2.5V Supply for the MDC/MDIO, INTn,

125CLK, RESETn, JTAG pin Power.

B4

C2

K1

5

2.5V I/O supply for the MAC interface pins.

21

88

96

11

30

122

March 4, 2009, Advance

Doc. No. MV-S105540-00, Rev. --

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Document Classification: Proprietary Information

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

Table 15: Power & Ground (Continued)

117-TFBGA 96-BCC 128-PQFP Pin Name

Description

Pin #

Type

D4

D5

D6

E4

E5

E6

F4

F5

F6

G4

G5

G6

H4

H5

H6

J4

0

1

9

15

21

22

38

40

43

45

48

51

55

58

60

63

65

VSS

GND

Global ground

J5

66

J6

83

K4

K5

K6

L5

L6

84

93

94

101

102

103

106

108

111

116

119

127

H7

53

74

VSSC

NC

GND

NC

Ground reference for XTAL1 and XTAL2

pins. This pin must be connected to the

ground.

G1

K7

13

51

50

No connect. Do not connect these pins to

anything

Doc. No. MV-S105540-00, Rev. --

Page 32

Document Classification: Proprietary Information

March 4, 2009, Advance

Signal Description

I/O State at Various Test or Reset Modes

1.5 I/O State at Various Test or Reset Modes

Pin(s)

Isolate

Loopback

or Normal

operation

Software

Reset

Hardware

Reset

Power Down

Coma

Power

Down and

Isolate

MDI[3:0]±

TX_CLK

Active

Tri-state

Low

Tri-state

Reg. 16.3

state

Reg. 16.3 state

0 = Low

Reg. 16.3

state

0 = Low

1 = Active

0 = Low

0 = Static but

can be either

high or low

RXD[0],

RXD[2]

Tri-state

Active

High

Low

High

Low

High

Low

High

Tri-state

RXD[7:3,1],

RX_DV,

RX_ER,

CRS

Low

COL

Tri-state

TBI mode -

input

else -active

Tri-state

Low

TBI mode -

input

else - low

TBI mode -

input

else - low

Tri-state

RX_CLK

Active

Reg. 16.3

state

Reg. 16.3 state

0 = Low

Reg. 16.3

state

0 = Low

1 = Active

0 = Low

0 = Static but

can be either

high or low

S_CLK±

S_OUT±

Active

Tri-state

Reg. 16.3 state

0 = Tri-state

1 = Active

Tri-state

Active

MDIO

INT

Active

Tri-state

Active

Tri-state

Active

Tri-state

High

Tri-state

High

Active

Tri-state

High

Tri-state

High

Active

Tri-state

High

LED_***

TDO

Tri-state

Toggle

Tri-state

Active

Tri-state

125CLK

Reg. 16.4

state

0 = Toggle 0 = Toggle

1 = Low 1 = Low

Reg. 16.4

state

Reg. 16.4

state

0 = Toggle

1 = Low

Reg. 16.4 state

0 = Toggle

1 = Low

Reg. 16.3

state

0 = Static but

can be either

high or low

0 = Low

Reg. 16.4

state

0 = Toggle

1 = Low

March 4, 2009, Advance

Doc. No. MV-S105540-00, Rev. --

Page 33

Document Classification: Proprietary Information

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

1.6 117-Pin TFBGA Pin Assignment List - Alphabetical by

Signal Name

Pin #

K2

B7

M3

M4

M7

M8

N5

B6

L4

Pin Name

125CLK

AVDD

Pin #

A9

C9

D9

L3

Pin Name

LED_LINK1000

LED_RX

LED_TX

MDC

AVDD

N2

N1

N4

N3

N7

N6

N9

N8

M1

G1

K7

K3

M2

B2

D3

C3

B3

C4

A1

A2

C5

C1

B1

D2

A6

A5

A4

A3

MDI[0]-

MDI[0]+

MDI[1]-

MDI[1]+

MDI[2]-

MDI[2]+

MDI[3]-

MDI[3]+

MDIO

AVDD

COL

COMA

D8

E9

F8

CONFIG[0]

CONFIG[1]

CONFIG[2]

CONFIG[3]

CONFIG[4]

CONFIG[5]

CONFIG[6]

CRS

G7

F9

NC

G9

G8

B5

C6

C7

D7

E3

E7

F3

NC

RESETn

RSET

DVDD

RXD0

DVDD

RXD1

DVDD

RXD2

DVDD

RXD3

DVDD

RXD4

DVDD

RXD5

J3

DVDD

RXD6

J7

DVDD

RXD7

E2

M6

M5

L1

GTX_CLK

HSDAC-

HSDAC+

INTn

RX_CLK

RX_DV

RX_ER

S_CLK-

S_CLK+

S_IN-

E8

C8

B8

LED_DUPLEX

LED_LINK10

LED_LINK100

S_IN+

Doc. No. MV-S105540-00, Rev. --

Page 34

March 4, 2009, Advance

Document Classification: Proprietary Information

Signal Description

117-Pin TFBGA Pin Assignment List - Alphabetical by Signal Name

1.6 117-Pin TFBGA Pin Assignment List - Alphabetical by

Signal Name (Continued)

Pin #

A8

A7

H8

L9

Pin Name

S_OUT-

S_OUT+

SEL_FREQ

TCK

Pin #

D4

D5

D6

E4

E5

E6

F4

F5

F6

G4

G5

G6

H4

H5

H6

J4

Pin Name

VSS

L7

TDI

VSS

K8

L8

TDO

VSS

TMS

VSS

M9

F1

G2

G3

H2

H1

H3

J1

TRSTn

TXD0

VSS

TXD1

VSS

TXD2

VSS

TXD3

VSS

TXD4

VSS

TXD5

VSS

TXD6

VSS

J2

TXD7

VSS

D1

E1

F2

B4

C2

K1

B9

F7

J8

TX_CLK

TX_EN

TX_ER

VDDO

VDDOH

VDDOX

J5

VSS

J6

VSS

K4

K5

K6

L5

VSS

L6

VSS

H7

H9

J9

VSSC

XTAL1

XTAL2

K9

L2

March 4, 2009, Advance

Doc. No. MV-S105540-00, Rev. --

Page 35

Document Classification: Proprietary Information

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

1.7 96-Pin BCC Pin Assignment List - Alphabetical by

Signal Name

Pin #

22

32

35

36

40

45

78

83

27

65

64

63

61

60

59

58

84

1

Pin Name

125CLK

AVDD

Pin #

74

73

69

68

25

31

29

34

33

41

39

43

42

24

13

51

28

30

95

92

93

91

90

89

87

86

2

Pin Name

LED_LINK100

LED_LINK1000

LED_RX

LED_TX

MDC

AVDD

MDI[0]-

MDI[0]+

MDI[1]-

MDI[1]+

MDI[2]-

MDI[2]+

MDI[3]-

MDI[3]+

MDIO

AVDD

COL

COMA

CONFIG[0]

CONFIG[1]

CONFIG[2]

CONFIG[3]

CONFIG[4]

CONFIG[5]

CONFIG[6]

CRS

NC

RESETn

RSET

DVDD

6

DVDD

RXD0

10

15

57

62

67

71

85

8

DVDD

RXD1

DVDD

RXD2

DVDD

RXD3

DVDD

RXD4

DVDD

RXD5

DVDD

RXD6

DVDD

RXD7

GTX_CLK

HSDAC-

HSDAC+

INTn

RX_CLK

RX_DV

RX_ER

S_CLK-

S_CLK+

S_IN-

38

37

23

70

76

94

3

80

79

81

LED_DUPLEX

LED_LINK10

Doc. No. MV-S105540-00, Rev. --

Page 36

March 4, 2009, Advance

Document Classification: Proprietary Information

Signal Description

96-Pin BCC Pin Assignment List - Alphabetical by Signal Name

1.7 96-Pin BCC Pin Assignment List - Alphabetical by

Signal Name (Continued)

Pin #

82

75

77

56

49

44

50

46

47

11

Pin Name

S_IN+

S_OUT-

S_OUT+

SEL_FREQ

TCK

Pin #

4

Pin Name

TX_CLK

TX_EN

TX_ER

VDDO

9

7

5

21

88

96

52

66

72

26

48

0

VDDO

TDI

VDDO

TDO

VDDO

TMS

VDDOH

VDDOX

VSS

TRSTn

TXD0

12

14

16

17

18

19

20

TXD1

TXD2

TXD3

TXD4

53

55

54

VSSC

TXD5

XTAL1

TXD6

XTAL2

TXD7

March 4, 2009, Advance

Doc. No. MV-S105540-00, Rev. --

Page 37

Document Classification: Proprietary Information

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

1.8 128-Pin PQFP Pin Assignment List - Alphabetical by

Signal Name

Pin #

31

44

49

52

59

64

104

114

37

88

87

86

82

81

80

79

115

2

Pin Name

125CLK

AVDD

Pin #

32

Pin Name

INTn

95

LED_DUPLEX

LED_LINK10

LED_LINK100

LED_LINK1000

LED_RX

LED_TX

MDC

AVDD

100

99

AVDD

98

AVDD

92

AVDD

91

COL

35

COMA

41

MDI[0]+

MDI[0]-

MDI[1]+

MDI[1]-

MDI[2]+

MDI[2]-

MDI[3]+

MDI[3]-

MDIO

CONFIG[0]

CONFIG[1]

CONFIG[2]

CONFIG[3]

CONFIG[4]

CONFIG[5]

CONFIG[6]

CRS

42

46

47

56

57

61

62

33

DVDD

50

NC

6

DVDD

36

RESETn

RSET

12

17

23

27

78

85

90

96

117

118

14

53

54

DVDD

39

DVDD

7

RX_CLK

RX_DV

RX_ER

RXD0

DVDD

4

DVDD

8

DVDD

3

DVDD

128

126

125

124

123

121

120

110

RXD1

DVDD

RXD2

DVDD

RXD3

DVDD

RXD4

DVDD

RXD5

GTX_CLK

HSDAC+

HSDAC-

RXD6

RXD7

S_CLK+

Doc. No. MV-S105540-00, Rev. --

Page 38

March 4, 2009, Advance

Document Classification: Proprietary Information

Signal Description

128-Pin PQFP Pin Assignment List - Alphabetical by Signal Name

1.8 128-Pin PQFP Pin Assignment List - Alphabetical by

Signal Name (Continued)

Pin #

109

113

112

107

105

77

Pin Name

S_CLK-

S_IN+

S_IN-

Pin #

9

Pin Name

VSS

VSSC

XTAL1

XTAL2

15

21

S_OUT+

S_OUT-

SEL_FREQ

TCK

22

38

40

70

43

67

TDI

45

72

TDO

48

69

TMS

51

68

TRSTn

TX_CLK

TX_EN

TX_ER

TXD0

55

10

58

16

60

13

63

18

65

19

TXD1

66

20

TXD2

83

24

TXD3

84

25

TXD4

93

26

TXD5

94

28

TXD6

101

102

103

106

108

111

116

119

127

74

29

TXD7

5

VDDO

VDDOH

VDDOX

VSS

11

30

122

73

89

97

34

71

76

1

75

March 4, 2009, Advance

Doc. No. MV-S105540-00, Rev. --

Page 39

Document Classification: Proprietary Information

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

Section 2. Package Mechanical Dimensions

2.1 117-pin TFBGA Package

(All dimensions in mm.)

Doc. No. MV-S105540-00, Rev. --

Page 40

March 4, 2009, Advance

Document Classification: Proprietary Information

Package Mechanical Dimensions

117-pin TFBGA Package

Table 16: 117-Pin TFBGA Package Dimensions

Dimensions in mm

Symbol

MIN

--

NOM

--

MAX

1.54

0.60

0.94

0.40

10.10

14.10

--

A

A1

A2

c

0.40

0.84

0.32

9.90

13.90

--

0.50

0.89

0.36

10.00

14.00

8.00

12.00

1.00

0.60

0.20

0.25

0.35

0.15

D

E

D1

E1

e

--

b

0.50

0.70

aaa

bbb

ccc

ddd

MD/ME

NOTE:

1. CONTROLLING DIMENSION: MILLIMETER.

2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE

SPHERICAL CROWNS OF THE SOLDER BALLS.

3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL

DIAMETER, PARALLEL TO PRIMARY DATUM C.

March 4, 2009, Advance

Doc. No. MV-S105540-00, Rev. --

Page 41

Document Classification: Proprietary Information

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

2.2 96-pin BCC Package - Top View

PIN 1 CORNER

9.00±0.10

X

1

3

73

71

C0.2

0.400±0.05

0.08

M

Z X Y

DETAIL "A" (1X)

51

50

23

24

0.15

Y

TOP VIEW

0.20

Z

0.05

Z

Doc. No. MV-S105540-00, Rev. --

Page 42

March 4, 2009, Advance

Document Classification: Proprietary Information

Package Mechanical Dimensions

96-Pin BCC Package - Bottom View

2.3 96-Pin BCC Package - Bottom View

4.100

3.50

''A''

0.60±0.10

(PIN 1 CORNER)

0.600 TYP.

4.800

CL.(PKG.)

0.2

"B"

0.30±0.05

7.00

7.200

8.20

M

0.08

Z X Y

DETAIL "B" (95X)

9.00

BOTTOM VIEW

March 4, 2009, Advance

Doc. No. MV-S105540-00, Rev. --

Page 43

Document Classification: Proprietary Information

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

2.4 128-Pin PQFP Package

23.20

0.20

±

20.00

0.10

102

65

103

64

14.00

0.10

±

17.20

0.20

±

PIN1

INDICATOR

128

39

1

38

1.6 Nominal

3.40 Max

0.25

min

0.22

0.05

0.88

0.15

±

0.5 Basic

Doc. No. MV-S105540-00, Rev. --

Page 44

March 4, 2009, Advance

Document Classification: Proprietary Information

Order Information

Ordering Part Numbers and Package Markings

Section 3. Order Information

3.1 Ordering Part Numbers and Package Markings

Figure 5 shows the ordering part numbering scheme for the 88E1111 devices. Contact Marvell^®FAEs or sales

representatives for complete ordering information.

Figure 5: Sample Part Number

88E1111 – xx – xxx – Cxxx - xxxx

Custom Code (optional)

Part Number

88E1111

Custom Code

Temperature Range

Custom Code

C = Commercial

I = Industrial

Package Code

Environmental

BAB = 117-pin TFBGA

CAA = 96-pin BCC

RCJ - 128-pin PQFP

“-” = RoHS 5/6 compliant package

1 = RoHS 6/6 compliant package

Table 17: 88E1111 Part Order Options - RoHS 5/6 Compliant Package

Package Type

Part Order Number

88E1111-XX-BAB-C000

88E1111 117-pin TFBGA - Commercial

88E1111 117-pin TFBGA - Industrial

88E1111 96-pin BCC - Commercial

88E1111 96-pin BCC - Industrial

88E1111 128-pin PQFP - Commercial

88E1111-XX-BAB-I000

88E1111-XX-CAA-C000

88E1111-XX-CAA-I000

88E1111-XX-RCJ-C000

Table 18: 88E1111 Part Order Options - RoHS 6/6 Compliant Package

Package Type

Part Order Number

88E1111 117-pin TFBGA - Commercial

88E1111 117-pin TFBGA - Industrial

88E1111 96-pin BCC - Commercial

88E1111 96-pin BCC - Industrial

88E1111 128-pin PQFP - Commercial

88E1111-XX-BAB1C000

88E1111-XX-BAB1I000

88E1111-XX-CAA1C000

88E1111-XX-CAA1I000

88E1111-XX-RCJ1C000

Doc. No. MV-S105540-00, Rev. --

Page 45

March 4, 2009, Advance

Document Classification: Proprietary Information

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

3.1.1 RoHS 5/6 Compliant Marking Examples

Figure 6 is an example of the package marking and pin 1 location for the 88E1111 117-pin TFBGA commercial

RoHS 5/6 compliant package.

Figure 6: 88E1111 117-pin TFBGA Commercial RoHS 5/6 Compliant Package Marking and Pin

1 Location

Logo

Part number, package code, environmental code

Environmental Code - No code = RoHS 5/6

1 = RoHS 6/6

88E1111-BAB

Lot Number

YYWW xx@

Country

Country of origin

Date code, custom code, assembly plant code

(Contained in the mold ID or

marked as the last line on

the package.)

YYWW

= Date code

xx

= Custom code

@ = Assembly location code

Pin 1 location

Note: The above example is not drawn to scale. Location of markings is approximate.

Figure 7 is an example of the package marking and pin 1 location for the 88E1111 117-pin TFBGA Industrial RoHS

5/6 compliant package.

Figure 7: 88E1111 117-pin TFBGA Industrial RoHS 5/6 Compliant Package Marking and Pin 1

Location

Logo

Part number, package code, environmental code

Environmental Code - No code = RoHS 5/6

1 = RoHS 6/6

88E1111-BAB

Lot Number

YYWW xx@

Country

Country of origin

Date code, custom code, assembly plant code

(Contained in the mold ID or

marked as the last line on

the package.)

I

YYWW

= Date code

xx

= Custom code

@ = Assembly location code

Industrial Grade Package Marking

Pin 1 location

Note: The above example is not drawn to scale. Location of markings is approximate.

Doc. No. MV-S105540-00, Rev. --

March 4, 2009, Advance

Page 46

Document Classification: Proprietary Information

Order Information

Ordering Part Numbers and Package Markings

Figure 8 is an example of the package marking and pin 1 location for the 88E1111 96-pin BCC Commercial RoHS

5/6 compliant package.

Figure 8: 88E1111 96-pin BCC Commercial RoHS 5/6 Compliant Package Marking and Pin 1

Location

Logo

88E1111-CAA

Part number, package code, environmental code

Environmental Code - No code = RoHS 5/6

1 = RoHS 6/6

Lot Number

YYWW xx@

Country

Country of origin

Date code, custom code, assembly plant code

(Contained in the mold ID or

marked as the last line on

the package.)

YYWW

= Date code

xx

= Custom code

@ = Assembly location code

Pin 1 location

Note: The above example is not drawn to scale. Location of markings is approximate.

Figure 9 is an example of the package marking and pin 1 location for the 88E1111 96-pin BCC Industrial RoHS 5/

6 compliant package.

Figure 9: 88E1111 96-pin BCC Industrial RoHS 5/6 Compliant Package Marking and Pin 1 Loca-

tion

Logo

88E1111-CAA

Part number, package code, environmental code

Environmental Code - No code = RoHS 5/6

1 = RoHS 6/6

Lot Number

YYWW xx@

Country

Country of origin

Date code, custom code, assembly plant code

(Contained in the mold ID or

marked as the last line on

the package.)

I

YYWW

= Date code

xx

= Custom code

@ = Assembly location code

Industrial Grade Package Marking

Pin 1 location

Note: The above example is not drawn to scale. Location of markings is approximate.

Doc. No. MV-S105540-00, Rev. --

Page 47

March 4, 2009, Advance

Document Classification: Proprietary Information

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

Figure 10 is an example of the package marking and pin 1 location for the 88E1111 128-pin PQFP Commercial

RoHS 5/6 compliant package.

Figure 10: 88E1111 128-pin PQFP Commercial RoHS 5/6 Compliant Package Marking and Pin 1

Location

Logo

Part number, package code, environmental code

Environmental Code - No code = RoHS 5/6

1 = RoHS 6/6

88E1111-RCJ

Lot Number

YYWW xx@

Country

Country of origin

Date code, custom code, assembly plant code

(Contained in the mold ID or

marked as the last line on

the package.)

YYWW

= Date code

xx

= Custom code

@ = Assembly location code

Pin 1 location

Note: The above example is not drawn to scale. Location of markings is approximate.

Doc. No. MV-S105540-00, Rev. --

March 4, 2009, Advance

Page 48

Document Classification: Proprietary Information

Order Information

Ordering Part Numbers and Package Markings

3.1.2 RoHS 6/6 Compliant Marking Examples

Figure 11 is an example of the package marking and pin 1 location for the 88E1111 117-pin TFBGA commercial

RoHS 6/6 compliant package.

Figure 11: 88E1111 117-pin TFBGA Commercial RoHS 6/6 Compliant Package Marking and Pin

1 Location

Logo

88E1111-BAB1

Part number, package code, environmental code

Environmental Code - No code = RoHS 5/6

1 = RoHS 6/6

Lot Number

YYWW xx@

Country

Country of origin

Date code, custom code, assembly plant code

(Contained in the mold ID or

marked as the last line on

the package.)

YYWW

= Date code

xx

= Custom code

@ = Assembly location code

Pin 1 location

Note: The above example is not drawn to scale. Location of markings is approximate.

Figure 12 is an example of the package marking and pin 1 location for the 88E1111 117-pin TFBGA industrial

RoHS 6/6 compliant package.

Figure 12: 88E1111 117-pin TFBGA Industrial RoHS 6/6 Compliant Package Marking and Pin 1

Location

Logo

88E1111-BAB1

Part number, package code, environmental code

Environmental Code - No code = RoHS 5/6

1 = RoHS 6/6

Lot Number

YYWW xx@

Country

Country of origin

Date code, custom code, assembly plant code

(Contained in the mold ID or

marked as the last line on

the package.)

I

YYWW

= Date code

xx

= Custom code

@ = Assembly location code

Industrial Grade Package Marking

Pin 1 location

Note: The above example is not drawn to scale. Location of markings is approximate.

Doc. No. MV-S105540-00, Rev. --

Page 49

March 4, 2009, Advance

Document Classification: Proprietary Information

88E1111 Product Brief

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

Figure 13 is an example of the package marking and pin 1 location for the 88E1111 96-pin BCC Commercial

RoHS 6/6 compliant package.

Figure 13: 88E1111 96-pin BCC Commercial RoHS 6/6 Compliant Package Marking and Pin 1

Location

Logo

88E1111-CAA1

Part number, package code, environmental code

Environmental Code - No code = RoHS 5/6

1 = RoHS 6/6

Lot Number

YYWW xx@

Country

Country of origin

Date code, custom code, assembly plant code

(Contained in the mold ID or

marked as the last line on

the package.)

YYWW

= Date code

xx

= Custom code

@ = Assembly location code

Pin 1 location

Note: The above example is not drawn to scale. Location of markings is approximate.

Figure 14 is an example of the package marking and pin 1 location for the 88E1111 96-pin BCC Industrial RoHS 6/

6 compliant package.

Figure 14: 88E1111 96-pin BCC Industrial RoHS 6/6 Compliant Package Marking and Pin 1 Loca-

tion

Logo

88E1111-CAA1

Part number, package code, environmental code

Environmental Code - No code = RoHS 5/6

1 = RoHS 6/6

Lot Number

YYWW xx@

Country

Country of origin

Date code, custom code, assembly plant code

(Contained in the mold ID or

marked as the last line on

the package.)

I

YYWW

= Date code

xx

= Custom code

@ = Assembly location code

Industrial Grade Package Marking

Pin 1 location

Note: The above example is not drawn to scale. Location of markings is approximate.

Doc. No. MV-S105540-00, Rev. --

March 4, 2009, Advance

Page 50

Document Classification: Proprietary Information

Order Information

Ordering Part Numbers and Package Markings

Figure 15 is an example of the package marking and pin 1 location for the 88E1111 128-pin PQFP Commercial

RoHS 6/6 compliant package.

Figure 15: 88E1111 128-pin PQFP Commercial RoHS 6/6 Compliant Package Marking and Pin 1

Location

Logo

88E1111-RCJ1

Part number, package code, environmental code

Environmental Code - No code = RoHS 5/6

1 = RoHS 6/6

Lot Number

YYWW xx@

Country

Country of origin

Date code, custom code, assembly plant code

(Contained in the mold ID or

marked as the last line on

the package.)

YYWW

= Date code

xx

= Custom code

@ = Assembly location code

Pin 1 location

Note: The above example is not drawn to scale. Location of markings is approximate.

Doc. No. MV-S105540-00, Rev. --

Page 51

March 4, 2009, Advance

Document Classification: Proprietary Information

Back Cover

Marvell Semiconductor, Inc.

5488 Marvell Lane

Santa Clara, CA 95054, USA

Tel: 1.408.222.2500

Fax: 1.408.752.9028

www.marvell.com

Marvell. Moving Forward Faster

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