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89HP0604SB

Data Sheet

4 Channel 6Gbps SAS/SATA

Signal Repeater

®

Device Overview

Features

Compensates for cable and PCB trace attenuation and ISI

jitter

The IDT 89HP0604SB (P0604SB) is a 6Gbps SAS/SATA® Repeater

device featuring IDT EyeBoost™ technology that compensates for cable

and board trace attenuations and ISI jitter, thereby extending connection

reach. The device is optimized for SAS/SATA high speed serial data

streams and contains four data channels, each able to process 6Gbps

transmission rates. Each channel consists of an input equalizer and

amplifier, signal detection with glitch filter, as well as programmable

output swing and de-emphasis. Allowing for application specific

optimization, the P0604SB, with its configurable receiver and transmitter

features, is ideal for SAS/SATA applications using a wide combination of

cables and board trace materials.

Programmable receiver equalization up to 24db

Programmable transmitter swing and de-emphasis

Recovers data stream even when the differential signal eye

is completely closed due to trace attenuation and ISI jitter

Full SAS/SATA protocol support

Configurable via external pins

Leading edge power minimization in active and shutdown

modes

No external bias resistors or reference clocks required

All modes of active data transfer are designed with minimized power

consumption. In full shutdown mode, the part consumes less than

40mW in worst case environmental conditions.

Channel mux mode, demux mode, 1 to 2 channels multicast,

and Z-switch function mode

Available in a 36-pin QFN package (4.0 x 7.5mm with 0.5mm

pitch)

Applications

Blade servers, rack servers

Benefits

SAS/SATA instrumentation

Extends maximum cable length to over 8 meters and trace

Storage systems

length over 48 inches in SAS/SATA applications

Cabled SAS/SATA devices

Minimizes BER

Typical Application

Figure 1 IDT Repeaters in Blade Servers

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

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February 8, 2011

IDT 89HP0604SB Data Sheet

SAS/SATA Compliance

The device was designed to provide end users with features needed to comply with SAS/SATA system application requirements:

–

SAS/SATA Out-of-Band (OOB) Support

Jitter, eye opening, and all other AC and DC specifications.

Block Diagram

The P0604SB contains four high speed channels as shown in Figure 2. Each channel can be routed to different outputs. Depending on user

configuration via mode selections, input traffic can be muxed or demuxed. Powerdown (PDB) is provided for state and channel control.

Figure 2 Block Diagram

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February 8, 2011

Table of Contents

Device Overview................................................................................................................................ 1

Applications........................................................................................................................................ 1

Features............................................................................................................................................. 1

Benefits.............................................................................................................................................. 1

Typical Application............................................................................................................................. 1

SAS/SATA Compliance ..................................................................................................................... 2

Block Diagram.................................................................................................................................... 2

Functional Description ....................................................................................................................... 5

Power-Up................................................................................................................................... 6

Power Sequencing..................................................................................................................... 6

IDT EyeBoost™ Technology ..................................................................................................... 6

Eye Diagram Parameters .......................................................................................................... 7

Modes of Operation ................................................................................................................... 7

Electrical Specifications ................................................................................................................... 11

Absolute Maximum Ratings..................................................................................................... 11

Recommended Operating Conditions...................................................................................... 11

Power Consumption ................................................................................................................ 12

Package Thermal Considerations............................................................................................ 12

DC Specifications .................................................................................................................... 13

AC Specifications..................................................................................................................... 13

Pin Description................................................................................................................................. 17

Package Pinout — 36-QFN Signal Pinout ....................................................................................... 19

Pin Diagram ..................................................................................................................................... 19

QFN Package Dimension ................................................................................................................ 20

Revision History............................................................................................................................... 21

Ordering Information........................................................................................................................ 22

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February 8, 2011

IDT 89HP0604SB Data Sheet

PAGE INTENTIONALLY LEFT BLANK

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February 8, 2011

IDT 89HP0604SB Data Sheet

Functional Description

The P0604SB has 4 channels, each with the individually programmable features listed below. Figure 3 diagrams the channel and Table 1

summarizes key configuration options.

OOB/LOS detection with

glitch filter

Channel power-down

Programmable equalizer

Programmable Transmitter

Input

termination

100 ohm

+

_

+

_

Output

termination

100 ohm

ٛ

De-emphasis: 0 to -6.5dB

Voltage swing: 500mV to

950mV

Up to 10dB

0 to 14dB

ٛ

Auto-boost

ٛ

Figure 3 Channel Block Diagram with Channel Features

Per-channel programmable features used at the Receive side.

–

Input equalization with 3 levels: 2 to 14dB compensation for high frequency signal attenuation due to cables and board traces. Additionally,

up to 10dB boost is added automatically by the equalizer for applications using long cables. The total equalization range is between 2dB and

24dB.

–

Input high impedance control via channel enable: disabled (active mode) and hi-Z (power-down).

Per-channel programmable features used at the Transmit side.

–

Output de-emphasis with 8 levels: 0 to -6.5dB. The de-emphasis boosts the magnitude of higher frequencies sent by the transmitter to

compensate for high frequency losses travelling through output side cable or output side board traces. This ensures that the final received

signal has a wider eye opening.

–

Output differential swing with 3 levels: 0.5V to 0.95V (peak-to-peak).

–

Loss of signal detection: When the incoming differential peak-peak amplitude falls below 110mV, the device enters loss of signal mode and

the corresponding transmitter stops toggling, maintains its common mode voltage level, and meets all loss of signal specifications described

in the AC Specifications section of this data sheet.

In addition, the device contains global configuration of the data path:

Transfer modes: direct connect, cross-connect, multicast.

–

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February 8, 2011

IDT 89HP0604SB Data Sheet

Power-Up

After the power supplies reach their minimum required levels, the P0604SB powers up by setting all input and output pins to known states:

All the device's input configuration pins are set internally to VSS or VDD for 2-level pins and to VDD/2 for 3-level pins.

High speed differential input and output pins depend on various conditions described below:

–

High speed differential input and output pins are in high impedance if any of the following conditions is true:

• Powerdown is set (PDB pin = 0V) or

• No receiver termination was detected at TX outputs

In all other cases, high speed differential input and output pins are set to 50 ohms per pin, with 100 ohms differential impedance. Also refer to

Table 2, Power Reducing Modes.

The power ramp up time for the P0604SB should be less than 1ms.

Power Sequencing

There are no power sequencing constraints for the P0604SB.

IDT EyeBoost™ Technology

IDT EyeBoost™ technology is a method of data stream recovery even when the differential signal eye is completely closed due to cable or trace

attenuation and ISI jitter. With IDT EyeBoost™, the system designer can both recover the incoming data and retransmit it to target device with a

maximized eye width and amplitude. An example of IDT EyeBoost™ usage in a system application and eye diagram results are shown in Figure 4. In

this figure, the (a) diagram shows incoming differential signal (closed eye) after 62 inch FR4 connection from signal source and the (b) diagram shows

differential signal at the output of repeater maximized eye opening with IDT EyeBoost™.

(a)

(b)

Figure 4 Eye Diagram

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February 8, 2011

IDT 89HP0604SB Data Sheet

Eye Diagram Parameters

Parameter Names for

Programming via Pins

Feature

Input equalization

Feature Type

Main eye optimization

A0RXEQ, A1RXEQ, B0RXEQ, B1RXEQ

Range: 0dB to 14dB (plus additional auto-

boost up to 10dB for long connections)

Output differential signal Main eye optimization

swing (peak-to-peak) and

A0TXSW, A1TXSW, B0TXSW, B1TXSW

Range: 0.5V to 0.95V for swing

output de-emphasis

Range: 0 to -6.5dB for de-emphasis

Table 1 Quick Reference: Parameters Used for Eye Optimization

Modes of Operation

The device supports several data transfer modes, loss of signal mode, and one power reducing mode.

Loss of Signal Mode

When the input signal is lost, the transmitter stops toggling and maintains its common-mode voltage level. The device detects loss-of-signal (LOS)

when the envelope of the incoming signal on a given channel has fallen below a programmable threshold level.

Power Reducing Modes

The Repeater supports five power-down states and one active state as shown in Table 2. The user can choose between full chip power-down or

channel based power-down. Power reducing modes are selected via PDB and channel enable pins (A0EN, A1EN, etc.).

Required

Power

Reducing

Mode

Signal

Values

State Description

PDB

Full IC power-

down

0

All channels are powered-down

Rx termination is set to Hi-Z

Tx termination is set to 1kΩ

Tx common-mode is at VDD

Channel enabled

and active. No

power-down

1

Tx output is active

Receiver terminations set to 50Ω

Transmitter terminations set to 50Ω

Table 2 Power Reducing Modes

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February 8, 2011

IDT 89HP0604SB Data Sheet

Channel Muxing

The P0604SB repeater permits a variety of muxing, demuxing, and switching configurations, and it can mux/de-mux 1 or 2 bi-directional SAS/

SATA lanes (4 SAS/SATA channels) into 2 target devices. These configurations require the selection of specific pins for input and output ports. In the

following sections, each configuration is described in terms of pin connectivity to external upstream and downstream devices. The configurations

shown are those often used in system designs:

–

Uni-directional 2:1 Mux (1 or 2 instances)

Uni-directional 1:2 De-Mux (1 or 2 instances)

Bi-directional 2:1 Mux/De-Mux

Bi-directional Z-function (also called Partial Cross Function)

The P0604SB supports channel muxing in both upstream and downstream channel directions via the CHSEL pin, as shown below. Figure 5 shows

the channel/reference muxing modes and Table 3 shows how CHSEL (Channel transfer selection) pin allows for various modes of data transfers:

Multicast mode, Direct-connect, and Cross-connect. Both Direct-connect, and Cross-connect modes are used to build uni-directional and bi-directional

2:1 mux and Z-switch functions.

Figure 5 Diagram of Channel/Reference Muxing Modes

Input Pins

Output Pins

CHSEL

A0RX[P,M]

A1RX[P,M]

B0RX[P,M]

B1RX[P,M]

A0TX[P,M]

A1TX[P,M]

B0TX[P,M]

B1TX[P,M]

CHSEL=VSS

(Multicast Mode)

A0 DATA

X

B0 DATA

X

A0 DATA

A1 DATA

B0 DATA

CHSEL=Open

(Direct-Connect

Mode)

A0 DATA

A1 DATA

X

B0 DATA

B1 DATA

X

A0 DATA

B0 DATA

B1 DATA

B0 DATA

CHSEL=VDD

(Cross-Connect

Mode)

Squelched

A0 DATA

Squelched

Table 3 Description of Channel Muxing/De-Muxing Functionality

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February 8, 2011

IDT 89HP0604SB Data Sheet

Uni-directional 2:1 Mux or Two Instances of Unidirectional 2:1 Mux

This function can be achieved by using the CHSEL pin as a mux control signal. CHSEL should be set to either VDD or OPEN. The ports should be

configured as shown in Figure 6.

A0RX(P,N)

A

B

Device #1

Device #2

A1TX(P,N)

OUT

Device #3

A1RX(P,N)

CHSEL

CHSEL = VDD: OUT = A

CHSEL = OPEN: OUT = B

Figure 6 Implementation of Unidirectional 2:1 Mux

As an alternative, different chip channels can also be selected as shown in Figure 7. This solution can be combined with the previous one to obtain

two instances of Uni-directional 2:1 Mux.

B0RX(P,N)

A

B

Device #1 or #4

Device #2 or #5

OUT

B1TX(P,N)

Device #3 or #6

B1RX(P,N)

CHSEL

CHSEL = VDD: OUT = A

CHSEL = OPEN: OUT = B

Figure 7 Implementation of Second Instance of Unidirectional 2:1 Mux

Uni-directional 1:2 De-Mux or Two Instances of Unidirectional 1:2 De-Mux

This function can be achieved by using CHSEL pin as a de-mux control signal. CHSEL should be set to either VDD or OPEN. The ports should be

configured as shown in Figure 8.

A0TX(P,N)

A

B

Device #2

Device #3

A0RX(P,N)

IN

Device #1

A1TX(P,N)

CHSEL

CHSEL = OPEN: A = IN

CHSEL = VDD: B = IN

Figure 8 Implementation of Unidirectional 1:2 De-Mux

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February 8, 2011

IDT 89HP0604SB Data Sheet

As an alternative, different chip channels can also be selected as shown in Figure 9. This solution can be combined with the previous one to obtain

two instances of Uni-directional 1:2 De-Mux.

B0TX(P,N)

Device #2 or #5

Device #3 or #6

A

B

IN

B0RX(P,N)

Device #1 or #4

B1TX(P,N)

CHSEL

CHSEL = OPEN: A = IN

CHSEL = VDD: B = IN

Figure 9 Implementation of Second Instance of Unidirectional 1:2 De-Mux

Bi-directional 2:1 Mux/De-Mux

The bi-directional Mux and De-Mux function can also be achieved by using the CHSEL pin as a mux control signal. CHSEL should be set to either

VDD or OPEN. The ports should be configured as shown in Figure 10.

A0RX(P,N)

B1TX(P,N)

A

B

Device #1

Device #2

I/O

A1TX(P,N)

B0RX(P,N)

Device #3

A1RX(P,N)

B0TX(P,N)

CHSEL

CHSEL = VDD: I/O = A

CHSEL = OPEN: I/O = B

Figure 10 Implementation of Bi--directional 2:1 Mux/De-Mux

Bi-directional Z-function (also called Partial Cross Function)

This function can also be achieved by using the CHSEL pin as a flow control signal. CHSEL should be set to either VDD or OPEN. The ports

should be configured as shown in Figure 11.

CHSEL=OPEN

A0TX(P,N)

B1RX(P,N)

A0RX(P,N)

B1TX(P,N)

Device #1

Device #2

Device #3

Device #4

A1TX(P,N)

B0RX(P,N)

A1RX(P,N)

B0TX(P,N)

Figure 11 Implementation of Z-function

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February 8, 2011

IDT 89HP0604SB Data Sheet

Electrical Specifications

Absolute Maximum Ratings

Note: All voltage values, except differential voltages, are measured with respect to ground pins.

Parameter

Supply voltage range VDD

Value

Unit

–0.5 to 1.35

–0.5 to VDD +0.5

–0.5 to VDD + 0.5

±2000

V

Voltage range Differential I/O

Control I/O

ESD requirements: Electrostatic discharge

Human body model

ESD requirements: Charged-Device Model (CDM)

ESD requirements: Machine model

Storage ambient temperature

±500

±125

V

-55 to 150

°C

Table 4 Absolute Maximum Ratings

Warning: Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating Conditions is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

Parameter

Notes

Min

Typical

Max

Unit

Power Supply Pin Requirements

VDD

1.2V DC analog supply voltage (specified at bump pins)

1.14

1.2

1.26

V

Temperature Requirements

TA

Ambient operating temperature - Commercial

0

-40

0

—

70

85

°C

Ambient operating temperature - Industrial

Junction operating temperature

TJUNCTION

125

Table 5 P0604SB Operating Conditions

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February 8, 2011

IDT 89HP0604SB Data Sheet

Power Consumption

Table 6 below lists power consumption values under typical and maximum operating conditions.

Parameter

Notes

Min

Typical

Max

Unit

Active Mode

I_VDD

Current into VDD supply

—

330

400

100

30

500

600

150

40

mA

mW

P_D

Full chip power¹

Power per channel¹

Full chip standby

P_D-ch

Standby Mode

Table 6 Power Consumption

^1.Maximum power under all conditions. Power is reduced by selecting smaller de-emphasis settings (closer or equal to 0dB).

Package Thermal Considerations

The data in Table 7 below contains information that is relevant to the thermal performance of the 36-pin QFN package.

Symbol

Parameter

Value

Conditions

Units

49.8

44.8

42.2

39.3

34.5

Zero air flow

1 m/S air flow

2 m/S air flow

NA

^oC/W

θ

Effective Thermal Resistance, Junction-to-Ambient

JA(effective)

θ

Thermal Resistance, Junction-to-Board

Thermal Resistance, Junction-to-Case

JB

θ

NA

JC

Table 7 Thermal Specifications for 36-QFN Package

Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the T

value

J(max)

specified in Table 7. Consequently, the effective junction to ambient thermal resistance (θ_JA) for the worst case scenario must be maintained

below the value determined by the formula:

θ_JA= (T

- T

)/P

J(max) A(max)

Given that the values of T

, T

, and P are known, the value of desired θ_JAbecomes a known entity to the system designer. How to

J(max) A(max)

achieve the desired θ_JAis left up to the board or system designer, but in general, it can be achieved by adding the effects of θ (value

JC

provided in Table 7), thermal resistance of the chosen adhesive (θ_CS), that of the heat sink (θ_SA), amount of airflow, and properties of the

circuit board (number of layers and size of the board).

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February 8, 2011

IDT 89HP0604SB Data Sheet

DC Specifications

Parameter

Description

Min

Typ

Max

Unit

V_IL

Digital Input Signal Voltage Low Level¹

Digital Input Signal Voltage Mid Level²

Digital Input Signal Voltage High Level¹

Hysteresis of Schmitt Trigger Input

Input Current³

Input Current⁴

Input Current²

Internal weak pull-down resistor at 2-level input pads⁴

Internal weak pull-up resistor at 2-level input pads³

Internal weak pull-down resistor at all 3-level input pads

Internal weak pull-up resistor at all 3-level input pads

-0.3

—

0.25*VDD-0.1

V

V_IM

0.25*VDD+ 0.1

0.75*VDD-0.1

V_IH

0.75*VDD+ 0.1

VDD+ 0.3

—

V

V_HYS

0.1

—

V

I_IL

100

180

—

µA

I_IH

—

µA

I_IL1

—

µA

I_IH1

—

µA

R_{WEAK_PD_2L}

R_{WEAK_PU_2L}

R_{WEAK_PD_3L}

R_{WEAK_PU_3L}

11

6.3

K ohm

—

Table 8 DC Specification

^1.Applies to all input pins.

^2.Applies to all 3-level input pins.

^3.Applies only to 2-level input pins with default values set to VDD in the Pin Description table (Table 12).

^4.Applies only to 2-level input pins with default values set to VSS in the Pin Description table (Table 12).

AC Specifications

Latency Specification

Parameter

Description

Min

Typical

Max

Unit

T_PD

Input to output signal propagation device

—

300

—

15

5

ps

ns

T_{SIGDET-ATTACK}

T_SIGDET-DECAY

T_{SIGDET-ATT-DECAY-MIS}

Signal Detect Valid Signal Attack Time (Turn-on time)

Signal Detect Valid Signal Decay Time (Turn-off time)

Signal Detect Attack / Decay Time Mismatch

—

Table 9 P0604SB Latency Specification

Receiver Specifications

Parameter

Description

Min

Typical

Max

Unit

Receiver Input Jitter Specification

T_RX-DJ

Receive input, Data Dependant Jitter (Inter-Symbol-

Interference)

—

>1

UI

T_RX-TJ

Receive input, Total Jitter

—

0

—

>1

—

UI

T_RX-EYE

Receiver eye time opening (can recover from closed

eye due to trace/cable jitter)

Table 10 P0604SB Receiver Electrical Specifications (Part 1 of 2)

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February 8, 2011

IDT 89HP0604SB Data Sheet

Parameter

Description

Min

Typical

Max

Unit

Receiver Input Eye Specification

V_DIFF-RX

Receiver Differential Peak-Peak Voltage¹

0

—

2000

30

mV

ps

t_skew-RX

RX Differential Skew

—

50

V_CM-AC-RX

Receiver AC Common Mode Voltage

OOB Signal Detection Threshold

—

100

160

mVp-p

mVppd

V_thresh

110

Receiver Return Loss

RL_DD11,RX

RX Differential Mode Return Loss

0 MHz - 150 MHz

18

14

10

8

—

-13

—

dB

150 MHz - 300 MHz

300 MHz - 600 MHz

600 MHz - 1.2 GHz

1.2 GHz - 2.4 GHz

2.4 GHz - 3.0 GHz

3

3.0 GHz - 5.0 GHz

1

RL_RXslope

Slope of RX Differential Mode Return Loss (From

300MHz)

—

dB/dec

GHz

RL_RX-freq-max

RL_CC11,RX

RX Differential Mode Return Loss Max Frequency

RX Common Mode Return Loss

0 MHz - 300 MHz

—

6

—

5

—

dB

300 MHz - 600 MHz

600 MHz - 1.2 GHz

2

1.2 GHz - 2.4 GHz

1

2.4 GHz - 3.0 GHz

1

3.0 GHz - 5.0 GHz

—

Receiver DC Impedance

Z_DIFF-RXDifferential impedance , RX pair

Z_CM-RXCommon-Mode Receive Impedance

85

20

—

115

40

Ohm

Table 10 P0604SB Receiver Electrical Specifications (Part 2 of 2)

^1.The minimum value of 0 mV represents the case when Eye is completely closed.

Transmitter Specifications

Parameter

Description

Min

Typical

Max

Unit

Output Eye and Common Voltage Specification

V_TX-DIFF-PP

Differential Transmitter swing

[A:B]xTXSW=1

800

700

950

800

1100

950

mV

[A:B]xTXSW=open

V_{TX-DIFF-PP-LOW}

Low power differential p-p Transmitter swing

[A:B]xTXSW=0

400

500

650

Table 11 P0604SB Transmitter Electrical Requirements (Part 1 of 2)

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February 8, 2011

IDT 89HP0604SB Data Sheet

Parameter

Description

Tx de-emphasis level ratio

Min

Typical

Max

Unit

V_TX-DE-RATIO

-6.5

0

dB

V_{TX-DE-RATIO-3.5dB}

Tx de-emphasis level ratio

[A:B]xTXSW=open

-4.0

—

-3.0

dB

V_{TX-DE-RATIO-6dB}

T_{RES-DJ-6.25GBPS-1}

T_{RES-DJ-6.25GBPS-2}

Tx de-emphasis level

[A:B]xTXSW=1

-6.5

—

-5.5

dB

UI

Residual Deterministic Jitter at output pins (1 inch FR4

trace before receiver input pins, 6.25Gbps)¹

<0.1

Residual Deterministic Jitter at output pins (40 inch FR4

trace before receiver input pins, 6.25Gbps)¹

—

0.18

0.25

UI

T_20-80TX

T_skewTX

TX Rise/Fall Time (20-80%)

TX Differential Skew

33

—

12

—

90

20

ps

R/F_bal

TX Rise/Fall Imbalance

20

%

AMP_bal

TX Amplitude Balance

10

%

V_CM,AC-TX-PP

V_TX-CM-RMS-AC

C_TX

Tx AC Common Mode Voltage (Peak to peak)

RMS AC Common Mode Voltage Variation

AC Coupling Capacitor

50

mVp-p

mV

nF

20

200

Transmitter DC Impedance

Z_TX-DIFF-DCTransmitter Output Differential DC Impedance

I_TX-SHORTTransmitter short-circuit current limit

Transmitter Return Loss

85

—

100

—

115

90

Ohm

mA

RL_DD11,TX

DC TX Differential Mode Return Loss

DC TX Differential Mode Return Loss (F_BAUD/2

14

6

—

dB

)

RL_TXslope

RL_CC11,TX

Slope of TX Differential Mode Return Loss (From

300MHz)

—

-13

dB/dec

TX Common Mode Return Loss (measured at 3.0 Gbps)

0 MHz - 300 MHz

8

5

2

1

—

dB

300 MHz - 600 MHz

600 MHz - 1.2 GHz

1.2 GHz - 2.4 GHz

2.4 GHz - 3.0 GHz

3.0 GHz - 5.0 GHz

Lane Skew

L_TX-SKEW

Lane-to-Lane Output Skew

—

5

10

ps

Table 11 P0604SB Transmitter Electrical Requirements (Part 2 of 2)

^1.Refer to Figure 12.

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February 8, 2011

IDT 89HP0604SB Data Sheet

C — Measurement Point

A — FR4 Trace

Note: FR4 test channel is bypassed for 1-inch input trace case.

B — SMA Connector

Figure 12 Residual Jitter Characterization Test Setup

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February 8, 2011

IDT 89HP0604SB Data Sheet

Pin Description

Note: Unused pins can be left floating.

Input/

Output/

Power

2 or 3

Level

Pin Name

Pin #

Description

Power

VDD

5, 8, 11, 21, 24, 27

1.2V (typ) Power supply for Repeater high speed channels

and internal logic. Each VDD pin should be connected to the

VDD plane through a low inductance path, with a via located

as close as possible to the landing pad of VDD pins. It is rec-

ommended to have a 0.01 µF or 0.1 µF, X7R, size-0402

bypass capacitor from each VDD pin to ground plane.

Power

VSS

Center Pad

VSS reference. VSS should be connected to the ground

plane through a low inductance path, with a via located as

close as possible to the landing pad.

Power

Data Signals

A0RXN

A0RXP

4

3

Channel A0 Receive Data Ports

Channel A0 Transmit Data Ports

Channel B0 Receive Data Ports

Channel B0 Transmit Data Ports

Channel A1 Receive Data Ports

Channel A1 Transmit Data Ports

Channel B1 Receive Data Ports

Channel B1 Transmit Data Ports

Input

Output

Input

A0TXN

A0TXP

28

29

B0RXN

B0RXP

25

26

B0TXN

B0TXP

7

6

Output

Input

A1RXN

A1RXP

10

9

A1TXN

A1TXP

22

23

Output

Input

B1RXN

B1RXP

19

20

B1TXN

B1TXP

13

12

Output

Channel Control and Status

A0RXEQ (Channel A0)

B0RXEQ (Channel B0)

A1RXEQ (Channel A1)

B1RXEQ (Channel B1)

15

17

36

33

Receiver Equalization at F=3GHz (6Gbps).

Programming of channel A0 via pins is shown below. To pro-

gram other channels, use pins for those channels.

Input - 3

level

A0RXEQ

VSS

Setting

2dB (3GHz)

Open

VDD

6dB (3GHz) (Default)

14dB (3GHz)

Table 12 Pin Description (Part 1 of 2)

17

February 8, 2011

IDT 89HP0604SB Data Sheet

Input/

Output/

Power

2 or 3

Level

Pin Name

Pin #

Description

A0TXSW (Channel A0)

B0TXSW (Channel B0)

A1TXSW (Channel A1)

B1TXSW (Channel B1)

1

Transmitter Voltage Swing (pk-pk).

Programming of channel A0 via pins is shown below. To pro-

gram other channels, use pins for those channels.

Input - 3

level

32

14

18

A0TXSW

VSS

Swing

0.5Vdiff-pkpk

De-Emphasis

0dB

Open

VDD

0.8Vdiff-pkpk (Default) -3.5dB

0.95Vdiff-pkpk

-6.5dB

Other Control Signals

PDB

35

Power-down Enable.

Input - 2

level

PDB

VSS

Setting

Powerdown IC. RX terminations are in Hi-Z,

TX is disabled

VDD

Normal operation (internal 11K ohm mini-

mum pull-up applied)

CHSEL

RSVD

30

Channel Transfer Mode.

Input - 3

level

CHSEL

VSS

Setting

Multi-cast mode

Open

VDD

Direct-connect mode (default)

Cross-connect mode

2,16,31,34

Reserved. Do not connect.

Table 12 Pin Description (Part 2 of 2)

18

February 8, 2011

IDT 89HP0604SB Data Sheet

Package Pinout — 36-QFN Signal Pinout

Table 13 lists the pin numbers and signal names for the P0604SB device.

Function

A0RXEQ

Function

A1TXP

Function

B1RXP

15

4

23

14

17

25

26

7

20

A0RXN

A0RXP

A0TXN

A0TXP

A0TXSW

A1RXEQ

A1RXN

A1RXP

A1TXN

A1TXSW

B0RXEQ

B0RXN

B0RXP

B1TXN

B1TXP

B1TXSW

CHSEL

PDB

13

3

12

28

29

1

18

30

B0TXN

35

36

10

9

B0TXP

6

RSVD

VDD

2,16,31,34

5,8,11,21,24,27

B0TXSW

B1RXEQ

B1RXN

32

33

19

22

Table 13 Alphabetical Pin List

Pin Diagram

The following figure lists the pin numbers and the signal names for the 36-QFN package.

Figure 13 Pin Diagram — Top View

19

February 8, 2011

IDT 89HP0604SB Data Sheet

QFN Package Dimension

20

February 8, 2011

IDT 89HP0604SB Data Sheet

Revision History

November 2, 2010: Initial publication of final datasheet.

February 8, 2011: Removed black packaging options from Order page.

21

February 8, 2011

IDT 89HP0604SB Data Sheet

Ordering Information

Legend

A = Alpha Character

N = Numeric Character

NN

A

AA

A

AAA

Pkg

N

NN

Product

Family

Operating

Voltage

Temp Tape &

Reel

Device

Revision

Speed Chnls

Product

Detail

Protocol

Range

Tape & Reel

8

Commercial Temperature

(0°C to +70°C Ambient)

Industrial Temperature

Blank

I

(-40° C to +85° C Ambient)

NRG36 36-pin QFN, Green

ZB revision

NRG

ZB

SAS/SATA Interface, “B” version

4 Channels

SB

04

6Gbps

06

P

rePeater

H

1.2V +/- 5%

Signal Integrity Product

89

Valid Combinations

89HP0604SBZBNRG8

89HP0604SBZBNRGI8

36-pin Green QFN package, Commercial Temperature

36-pin Green QFN package, Industrial Temperature

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

800-345-7015 or 408-284-8200

fax: 408-284-2775

for Tech Support:

email: siphelp@idt.com

phone: 408-284-8208

®

www.idt.com

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of

product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when

installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied

warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a

manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners.

22

February 8, 2011

型号:	89HPEB383ZBEMG8
Brand Name：	Integrated Device Technology
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Transferred
IHS 制造商：	INTEGRATED DEVICE TECHNOLOGY INC
零件包装代码：	TQFP
包装说明：	TFQFP,
针数：	128
制造商包装代码：	EMG128
Reach Compliance Code：	compliant
风险等级：	5.8
Samacsys Description：	TQFP 14.0 X 14.0 X 1.0 MM
地址总线宽度：	32
总线兼容性：	ISA; PCI; SBUS; VGA; USB
最大数据传输速率：	2500 MBps
外部数据总线宽度：	32
JESD-30 代码：	S-PQFP-G128
JESD-609代码：	e3
长度：	14 mm
湿度敏感等级：	3
端子数量：	128
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	TFQFP
封装形状：	SQUARE
封装形式：	FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260
座面最大高度：	1.2 mm
最大供电电压：	1.155 V
最小供电电压：	0.945 V
标称供电电压：	1.05 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn)
端子形式：	GULL WING
端子节距：	0.4 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	30
宽度：	14 mm
uPs/uCs/外围集成电路类型：	BUS CONTROLLER, PCI

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