9179BF芯片引脚定义引脚图及功能IC贸易商引脚图技术参数-中国IC网-芯三七

ICS9179B-01

Integrated

Circuit

Systems, Inc.

Low Skew Buffers

General Description

Features

•

High speed, low noise non-inverting (0:17) buffer for

SDRAM clock buffer applications.

Supports up to four SDRAM DIMMS

Synchronous clocks skew matched to 250ps

window on SDRAM.

The ICS9179B-01 generates SDRAM clock buffers

required for high speed RISC or CISC microprocessor

systems such as Intel PentiumPro or Pentium II. An

output enable is provided for testability.

•

The device is a buffer with low output to output skew.This

is a Fanout buffer device, not using an internal PLL.This

buffer can also be a feedback to an external PLL stage for

phase synchronization to a master clock.

•

I²C Serial Configuration interface to allow individual

clocks to be stopped.

•

Multiple VDD, VSS pins for noise reduction

Tri-state pin for testing

Custom configurations available

3.0V – 3.7V supply range

The individual clock outputs are addressable through I²C

to be enabled, or stopped in a low state for reduced EMI

when the lines are not needed.

48-pin SSOP package

Block Diagram

Pin Configuration

48-Pin SSOP

PentiumPro is a trademark of Intel Corporation

I²C is a trademark of Philips Corporation

0256E—12/15/08

ICS9179B-01

Pin Descriptions

PIN NUMBER

PIN NAME

TYPE DESCRIPTION

4, 5, 8, 9

13, 14, 17, 18

SDRAM (0:3)

SDRAM (4:7)

OUT SDRAM Byte 0 clock outputs¹

OUT SDRAM Byte 1 clock outputs¹

31, 32, 35, 36 SDRAM (8:11) OUT SDRAM Byte 2 clock outputs¹

40, 41, 44, 45 SDRAM (12:15) OUT SDRAM Byte 3 clock outputs¹

21, 28

11

SDRAM (16:17) OUT SDRAM clock outputs useable for feedback.¹

BUF_IN

IN Input for buffers

Tri-states all outputs when held LOW. Has internal

38

OE

IN

pull-up.²

24

25

SDATA

SCLK

I/O Data pin for I²C circuitry³

I/O Clock pin for I²C circuitry³

3, 7, 12, 16,

20, 29, 33, 37,

42, 46

6, 10, 15, 19,

22, 27, 30, 34,

39, 43

VDD

GND

PWR 3.3V Power supply for SDRAM buffer

PWR Ground for SDRAM buffer

23

26

VDDS

GNDS

N/C

PWR 3.3V Power supply for I²C circuitry

PWR Ground for I²C circuitry

1, 2, 47, 48

-

Pins are not internally connected

Notes:

1.

2.

3.

At power up all eighteen SDRAM outputs are enabled and active.

OE has a 100K Ohm internal pull-up resistor to keep all outputs active.

The SDATA and SCLK inputs both also have internal pull-up resistors with values above 100K Ohms as well

for complete platform flexibility.

Power Groups

VDD = Power supply for SDRAM buffer

VDDS = Power supply for I²C circuitry

Ground Groups

GND = Ground for SDRAM buffer

GNDS = Ground for I²C circuitry

2

ICS9179B-01

Technical Pin Function Descriptions

VDD

This is the power supply to the internal core logic of the

device as well as the clock output buffers for

SDRAM(0:17).

This pin operates at 3.3V volts. Clocks from the listed

buffers that it supplies will have a voltage swing from

Ground to this level. For the actual guaranteed high and

low voltage levels for the Clocks, please consult the DC

parameter table in this data sheet.

GND

This is the power supply ground (common or negative)

return pin for the internal core logic and all the output

buffers.

SDRAM(0:17)

These Output Clocks are use to drive Dynamic RAM’s

and are low skew copies of the CPU Clocks. The voltage

swing of the SDRAM’s output is controlled by the supply

voltage that is applied toVDD of the device, operates at

3.3 volts.

I²C

The SDATA and SCLOCK Inputs are use to program the

device. The clock generator is a slave-receiver device in

the I²C protocol. It will allow read-back of the registers.

See configuration map for register functions. The I²C

specification in Philips I²C Peripherals Data Handbook

(1996) should be followed.

BUF_IN

Input for Fanout buffers (SDRAM 0:17).

OE

OE tristates all outputs when held low.

VDDS

This is the power supply to I²C circuitry.

GNDS

This is the ground to I²C circuitry.

3

ICS9179B-01

General I²C serial interface information

A.

For the clock generator to be addressed by an I²C controller, the following address must be sent as a start

sequence, with an acknowledge bit between each byte.

Clock Generator

Address (7 bits)

+ 8 bits

dummy

command

code

+ 8 bits

dummy Byte ACK

count

Then Byte 0, 1, 2, etc in

sequence until STOP.

ACK

A(6:0) & R/W#

D2(H)

B.

Theclockgeneratorisaslave/receiverI²Ccomponent. Itcan"readback"(inPhilipsI²Cprotocol) thedatastored

in the latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet

the Intel SMB PIIX4 protocol.

Clock Generator

Address (7 bits)

A(6:0) & R/W#

D3^(H)

Byte 0, 1, 2, etc in sequence until STOP.

Byte 0

ACK

Byte 1

ACK

C.

D.

E.

F.

The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)

The input is operating at 3.3V logic levels.

The data byte format is 8 bit bytes.

To simplify the clock generator I²C interface, the protocol is set to use only block writes from the controller.The

bytesmustbeaccessedinsequentialorderfromlowesttohighestbytewiththeabilitytostopafteranycomplete

bytehasbeentransferred. TheCommandcodeandBytecountshownabovemustbesent, butthedataisignored

for those two bytes. The data is loaded until a Stop sequence is issued.

G.

H.

Inthepowerdownmode(PWR_DWN#Low), theSDATAandSCLKpinsaretristatedandtheinternaldatalatches

maintain all prior programming information.

At power-on, all registers are set to a default condition. Bytes 0 through 2 default to a 1 (Enabled output state).

Serial Configuration Command Bitmaps

Byte0:SDRAMClockRegister

BIT

PIN# PWD

DESCRIPTION

Bit7

18

17

14

13

9

1

SDRAM7

(Act/Inact)

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SDRAM6

(Act/Inact)

SDRAM5

(Act/Inact)

SDRAM4

(Act/Inact)

SDRAM3

(Act/Inact)

SDRAM2

(Act/Inact)

SDRAM1

(Act/Inact)

SDRAM0

(Act/Inact)

8

5

4

Notes: 1 = Enabled; 0 = Disabled, outputs held low

Note: PWD = Power-Up Default

4

ICS9179B-01

Functionality

SDRAM

(12:15)

SDRAM

(16:17)

OE#

SDRAM (0:3)

SDRAM (4:7) SDRAM (8:11)

0

1

Hi-Z

1 X BUF_IN

Byte1:SDRAMClockRegister

Byte2:PCICLKClockRegister

BIT PIN# PWD DESCRIPTION

BIT PIN# PWD

DESCRIPTION

SDRAM15

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

45

44

41

40

36

35

32

31

1

(Act/Inact)

SDRAM17

(Act/Inact)

SDRAM16

(Act/Inact)

Bit 7 28

Bit 6 21

1

SDRAM14

(Act/Inact)

SDRAM13

(Act/Inact)

SDRAM12

(Act/Inact)

SDRAM11

(Act/Inact))

SDRAM10

(Act/Inact)

SDRAM9

(Act/Inact)

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

-

1

Reserved

SDRAM8

(Act/Inact))

Notes: 1 = Enabled; 0 = Disabled, outputs held low

Note: PWD = Power-Up Default

Notes: 1 = Enabled; 0 = Disabled, outputs held low

ICS9179B-01 Power Management

The values below are estimates of target specifications.

Max 3.3V supply consumption

Max discrete cap loads

Condition

VDD = 3.465V

All static inputs = VDD or GND

No Clock Mode

(BUF_IN - VDD1 or

GND)

3mA

I²C Circuitry Active

Active 66MHz

115mA

180mA

(BUF_IN = 66.66MHz)

Active 100MHz

(BUF_IN = 100.00MHz)

5

ICS9179B-01

Absolute Maximum Ratings

SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V_DD+0.5 V

Ambient OperatingTemperature . . . . . . . . . . 0°C to +70°C

StorageTemperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These

ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose

listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect product reliability.

Electrical Characteristics - Input & Supply

T_A= 0 - 70C; Supply Voltage V_DD= 3.3 V +/-5% (unless otherwise stated)

PARAMETER

Input High Voltage

Input Low Voltage

Input High Current

SYMBOL

V_IH

CONDITIONS

MIN

2

TYP

MAX UNITS

V_DD+0.3

V

V_IL

V_SS-0.3

0.8

5

I_IH

V_IN= V_DD

V_IN= 0 V; Inputs with no pull-up resistors

uA

I_IL

-5

uA

Input Low Current

I_IL

V_IN= 0 V; Inputs with 100K pull-up resisto -60

C_L= 0 pF; F_IN@ 66M

-33

80

uA

I_DD1

I_DD2

I_DD3

I_DD4

I_DD5

F_i¹

120

180

260

360

500

150

5

mA

µA

C_L= 0 pF; F_IN@ 100M

120

180

240

Operating Supply

Current

C_L= 30 pF; RS=33W; F_IN@ 66M

C_L= 30 pF; RS=33W; F_IN@ 100M

Stopped, input at 0 or VDD

Input frequency

V_DD= 3.3 V; All Outputs Loaded

Logic Inputs

10

MHz

pF

1

Input Capacitance

C_IN

¹Guaranteed by design, not 100% tested in production.

6

ICS9179B-01

Electrical Characteristics - SDRAM

T_A= 0 - 70C; V_DD= V_DDL= 3.3 V +/-5%; C_L= 20 - 30 pF (unless otherwise stated)

PARAMETER

Output Impedance

Output High Voltage

Output Low Voltage

Output High Current

Output Low Current

Rise Time¹

SYMBOL

R_DSP

R_DSN

V_OH

V_OL

I_OH

CONDITIONS

V_O= V_DD*(0.5)

MIN

10

TYP

MAX UNITS

24

W

V_O= V_DD*(0.5)

I_OH= -36 mA

10

2.4

3

V

I_OL= 23 mA

0.27

-115

57

0.4

-54

V

V_OH= 2.0 V

mA

ns

%

I_OL

V_OL= 0.8 V

40

0.5

45

T_r

V_OL= 0.4 V, V_OH= 2.4 V

V_OH= 2.4 V, V_OL= 0.4 V

V_T= 1.5 V

0.95

51

1.33

55

250

6

Fall Time¹

Duty Cycle¹

T_f

D_t

Skew¹

T_sk

V_T= 1.5 V

110

5

ps

ns

T_PROP

V_T= 1.5 V

1

Propagation¹

T_PROPENV_T= 1.5 V

T_PROPDISV_T= 1.5 V

8

¹Guarenteed by design, not 100% tested in production.

7

ICS9179B-01

GeneralLayoutPrecautions:

1) Use a ground plane on the top

layer of the PCB in all areas not

used by traces.

2)Makeallpowertracesandviasas

wide as possible to lower

inductance.

Notes:

1

All clock outputs should have

series terminating resistor. Not

shown in all places to improve

readibility of diagram

2 Optional EMI capacitor should be

usedonallCPU, SDRAM, andPCI

outputs.

CapacitorValues:

All unmarked capacitors are 0.01µF ceramic

8

ICS9179B-01

SSOP Package

SYMBOL

COMMON DIMENSIONS

VARIATIONS

D

N

MIN.

.095

.008

.088

.008

.005

NOM.

.101

.012

.090

.010

-

MAX.

.110

.016

.092

.0135

.010

MIN. NOM. MAX.

.620 .625 .630

A

A1

A2

B

C

D

E

AC

48

See Variations

.296

.292

.299

e

H

h

L

0.025 BSC

.406

.013

.032

.400

.010

.024

.410

.016

.040

N

µ

See Variations

0°

5°

8°

X

.085

.093

.100

Ordering Information

9179BF-01

Example:

XXXX F - PPP

Pattern Number (2 or 3 digit number for parts with ROM code

patterns)

Package Type

F=SSOP

Device Type

9

ICS9179B-01

Revision History

Rev.

Issue Date Description

Page #

E

12/15/2008 Removed ICS prefix from ordering information

9

10

型号:	9179BF-01
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	INTEGRATED DEVICE TECHNOLOGY INC
零件包装代码：	SSOP
包装说明：	SSOP-48
针数：	48
Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01
风险等级：	5.73
系列：	9179
输入调节：	STANDARD
JESD-30 代码：	R-PDSO-G48
JESD-609代码：	e0
长度：	15.875 mm
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER
最大I（ol）：	0.023 A
湿度敏感等级：	1
功能数量：	1
反相输出次数：
端子数量：	48
实输出次数：	18
最高工作温度：	70 °C
最低工作温度：
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP
封装等效代码：	SSOP48,.4
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH
电源：	3.3 V
Prop。Delay @ Nom-Sup：	8 ns
传播延迟（tpd）：	8 ns
认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.25 ns
座面最大高度：	2.794 mm
子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.7 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING
端子节距：	0.635 mm
端子位置：	DUAL
宽度：	7.5184 mm
Base Number Matches：	1

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