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Programmable Timing Control Hub^TMfor P4^TM

ICS950201

Frequency Table

Recommended Application:

CK-408 clock for Intel^®845 chipset with P4 processor.

Output Features:

66Buff[2:0]

PCI_F

PCI

CPU

FS2 FS1 FS0

(MHz)

3V66

3V66[4:2]

(MHz)

•

3 Differential CPU Clock Pairs @ 3.3V

7 PCI (3.3V) @ 33.3MHz

3 PCI_F (3.3V) @ 33.3MHz

1 USB (3.3V) @ 48MHz

1 DOT (3.3V) @ 48MHz

1 REF (3.3V) @ 14.318MHz

5 3V66 (3.3V) @ 66.6MHz

0

1

0

1

0

1

0

1

0

1

0

1

66.66

100.00

200.00

133.33

Tristate

66.66

Tristate

66.66

33.33

0

66.66

33.33

0

66.66

33.33

Mid

Tristate

TCLK/4

Tristate

TCLK/8

TCLK/2 TCLK/4

Reserved Reserved Reserved Reserved

1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz

Features:

•

Supports spread spectrum modulation,

down spread 0 to -0.5%.

Efficient power management scheme through PD#,

CPU_STOP# and PCI_STOP#.

•

Uses external 14.318MHz crystal

Stop clocks and functional control available through

I²C interface.

Key Specifications:

•

CPU Output Jitter <150ps

3V66 Output Jitter <250ps

CPU Output Skew <100ps, programmable over 800 ps

with groups CPU0,1 and CPU2.

Pin Configuration

56-Pin SSOP & TSSOP

* These inputs have 150K internal pull-up resistor to VDD.

IDT^TMProgrammable Timing Control Hub^TMfor P4^TM

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ICS950201

Programmable Timing Control Hub^TMfor P4^TM

Block Diagram

IDT^TMProgrammable Timing Control Hub^TMfor P4^TM

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ICS950201

Programmable Timing Control Hub^TMfor P4^TM

Pin Description

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

1, 8, 14, 19, 26,

32, 37, 46, 50

VDD

PWR

3.3V power supply

X2 Crystal

Input

2

3

X1

X2

14.318MHz Crystal input

14.318MHz Crystal output

X1 Crystal

Output

Free running PCI clock not affected by PCI_STOP#

for power management.

7, 6, 5

PCICLK_F (2:0)

GND

OUT

PWR

OUT

4, 9, 15, 20, 27,

31, 36, 41, 47

Ground pins for 3.3V supply

PCI clock outputs

18, 17, 16, 13,

12,11, 10

PCICLK (6:0)

24,23, 22, 21

3V66 (5:2)

3V66_5

PD#

OUT

IN

66MHz reference clocks, from internal VCO

66MHz reference clock, from internal VCO

Invokes power-down mode. Active Low.

24

25

This 3.3V LVTTL input is a level sensitive strobe used to

determine when FS(2:0) and MULTISEL0 inputs are valid

and are ready to be sampled

28

Vtt_PWRGD#

IN

(active low)

Data pin for I²C circuitry 5V tolerant

Clock pin of I²C circuitry 5V tolerant

66MHz reference clocks, from internal VCO

29

30

33

SDATA

SCLK

I/O

IN

3V66_0

OUT

Halts PCICLK clocks at logic 0 level, when input low except

PCICLK_F which are free running

34

PCI_STOP#

IN

3.3V output selectable through I²C to be 66MHz from internal VCO

or

35

3V66_1/VCH_CLK

OUT

48MHz (non-SSC)

38

39

40

48MHz_DOT

48MHz_USB

FS2

OUT

IN

48MHz output clock for DOT

48MHz output clock for USB

Special 3.3V input for Mode selection, cannot be logic 1

This pin establishes the reference current for the CPUCLK pairs.

This pin requires a fixed precision resistor tied to ground in order to

establish the appropriate current.

, 42

I REF

OUT

43

MULTSEL0

IN

3.3V LVTTL input for selecting the current multiplier for CPU outputs

"Complementory" clocks of differential pair CPU outputs. These are

current outputs and external resistors are required for voltage bias.

44, 48, 51

CPUCLKC (2:0)

OUT

"True" clocks of differential pair CPU outputs. These are current

outputs and external resistors are required for voltage bias.

45, 49, 52

CPUCLKT (2:0)

OUT

53

55, 54

56

CPU_STOP#

FS (1:0)

REF

IN

Halts CPUCLK clocks at logic 0 level, when input low

Frequency select pins

OUT

14.318MHz reference clock.

Power Groups

(Analog)

(Digital)

VDDA = Analog Core PLL1

VDDREF = REF, Xtal

VDD48 = 48MHz, PLL

VDDPCI

VDD3V66

VDDCPU

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Truth Table

PCI_F

PCI

(MHz)

CPU

(MHz)

3V66 (5:0)

(MHz)

REF0

(MHz)

USB/DOT

(MHz)

FS2

FS1

FS0

0

1

0

1

0

1

0

1

0

1

0

1

66.66

100.00

200.00

133.33

Tristate

TCLK/2

66.66

33.33

14.318

48.00

0

66.66

33.33

14.318

48.00

0

66.66

33.33

14.318

48.00

Mid

Tristate

TCLK/4

Tristate

TCLK/8

Tristate

TCLK

Tristate

TCLK/2

Reserved

Reserved Reserved Reserved

Reserved

Maximum Allowed Current

Max 3.3V supply consumption

Max discrete cap loads,

Vdd = 3.465V

Condition

Full Active

All static inputs = Vdd or GND

360mA

Host Swing Select Functions

Reference R,

Iref =

V_DD/(3*Rr)

Board Target

MULTISEL0

Output

Current

Voh @ Z

Trace/Term Z

Rr = 475 1%,

Iref = 2.32mA

1

50 ohms

Ioh = 6* I REF 0.7V @ 50

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Programmable Timing Control Hub^TMfor P4^TM

General I²C serial interface information

The information in this section assumes familiarity with I²C programming.

For more information, contact IDT for an I²C programming application note.

How to Write:

• Controller (host) sends a start bit.

• Controller (host) sends the write address D2_(H)

• ICS clock will acknowledge

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the read address D3_(H)

• ICS clock will acknowledge

• Controller (host) sends a dummy command code

• ICS clock will acknowledge

• ICS clock will send the byte count

• Controller (host) acknowledges

• Controller (host) sends a dummy byte count

• ICS clock will acknowledge

• Controller (host) starts sending first byte (Byte 0)

through byte 5

• ICS clock sends first byte (Byte 0) through byte 6

• Controller (host) will need to acknowledge each byte

• Controller (host) will send a stop bit

• ICS clock will acknowledge each byte one at a

time.

• Controller (host) sends a Stop bit

How to Read:

How to Write:

Controller (Host)

Start Bit

ICS (Slave/Receiver)

Controller (Host)

Start Bit

ICS (Slave/Receiver)

Address

D3_{(H )}

D2_{(H )}

ACK

Byte Count

Dummy Command Code

ACK

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

Byte 6

Dummy Byte Count

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

ACK

Stop Bit

Byte 6

Stop Bit

Notes:

1.

The ICS clock generator is a slave/receiver, I²C component. It can read back the data stored in the latches for

verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.

2.

3.

4.

5.

The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

The input is operating at 3.3V logic levels.

The data byte format is 8 bit bytes.

To simplify the clock generator I²C interface, the protocol is set to use only "Block-Writes" from the controller.The bytes

must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has

been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two

bytes. The data is loaded until a Stop sequence is issued.

6.

At power-on, all registers are set to a default condition, as shown.

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Byte 0: Control Register

Bit

Pin#

Name

PWD²

Type¹

Description

Reflects the value of FS0 pin sampled on

power up

Bit 0

54

FS0

X

R

Reflects the value of FS1 pin sampled on

power up

Reflects the value of FS2 pin sampled on

power up

Hardware mode: Reflects the value of

PCI_STOP# pin sampled on PWD

Bit 1

Bit 2

55

40

FS1

FS2

X

R

Bit 3

Bit 4

34

53

PCI_STOP#³

Software mode:

1

RW

0=PCICLK stopped

1=PCICLK not stopped

Reflects the current value of the external

CPU_STOP# pin

VCH Select 66MHz/48MHz

0=66MHz, 1=48MHz

CPU_STOP#

3V66_1/VCH

X

R

Bit 5

Bit 6

Bit 7

35

-

0

RW

(Reserved)

Spread

Enabled

-

RW

0=Spread Off, 1=Spread On

Byte 1: Control Register

Bit

Pin#

Name

PWD²

Type¹

Description

CPUCLKT0

Bit 0 52, 51

Bit 1 49, 48

Bit 2 45, 44

1

RW

0=Disabled 1=Enabled ⁴

CPUCLKC0

CPUCLKT1

CPUCLKC1

CPUCLKT2

CPUCLKC2

1

RW

0=Disabled 1=Enabled ⁴

Allow control of CPUCLKT0/C0 with assertion

of CPU_STOP# 0=Not free running 1=Free

running

Allow control of CPUCLKT1/C1 with assertion

of CPU_STOP# 0=Not free running 1=Free

running

Allow control of CPUCLKT2/C2 with assertion

of CPU_STOP# 0=Not free running 1=Free

running

CPUCLKT0

CPUCLKC0

Bit 3 52, 51

Bit 4 49, 48

Bit 5 45, 44

0

RW

CPUCLKT1

CPUCLKC1

CPUCLKT2

CPUCLKC2

Bit 6

Bit 7

-

43

-

0

X

-

R

(Reserved)

Reflects the current value of MULTSEL0

MULTSEL0

Notes:

1. R= Read only RW= Read and Write

2. PWD = Power on Default

3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the

system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP

functionality via I²C Byte 0 Bit 3.

In Hardware mode it is not allowed to write to the I²C Byte 0 Bit3. In Software mode it is not allowed to pull the external

PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP conditions.

The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it is not allowed to mix these

modes.

In Hardware mode the I²C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip is in

PCI_STOP mode.

Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I²C Byte 0 Bit 3 = 0)].

4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high, CPUCLKC

off, and external resistor termination will bring CPUCLKC low.

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Byte 2: Control Register

Bit

Pin#

10

11

12

13

16

17

18

-

Name

PCICLK0

PCICLK1

PCICLK2

PCICLK3

PCICLK4

PCICLK5

PCICLK6

-

PWD

Type

RW

-

Description

0=Disabled 1=Enabled

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

1

0

0=Disabled 1=Enabled

(Reserved)

Byte 3: Control Register

Bit

Pin#

Name

PWD

Type

RW

Description

Bit 0

Bit 1

Bit 2

5

6

7

PCICLK_F0

PCICLK_F1

PCICLK_F2

1

0=Disabled 1=Enabled

Allow control of PCICLK_F0 with assertion of

PCI_STOP#. 0=Free Running, 1=Not free

running

Allow control of PCICLK_F1 with assertion of

PCI_STOP#. 0=Free Running, 1=Not free

running

Allow control of PCICLK_F2 with assertion of

PCI_STOP#. 0=Free Running, 1=Not free

running

Bit 3

Bit 4

Bit 5

5

6

7

PCICLK_F0

PCICLK_F1

PCICLK_F2

0

RW

Bit 6

Bit 7

39

38

48MHz_USB

48MHz_DOT

1

RW

0=Disabled 1=Enabled

Byte 4: Control Register

Bit

Pin#

21

22

23

24

35

33

-

Name

3V66-2

3V66-3

3V66-4

3V66_5

PWD

Type

RW

R

Description

0=Disabled 1=Enabled

(Reserved)

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

1

0

3V66_1/VCH_CLK

3V66_0

-

R

(Reserved)

Notes:

1. R= Read only RW= Read and Write

2. PWD = Power on Default

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Absolute Maximum Ratings

Supply Voltage

5.5 V

Logic Inputs

GND –0.5 V to V_DD+0.5 V

0°C to +70°C

115°C

Ambient Operating Temperature

Case Temperature

Storage Temperature

–65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are

stress specifications only and functional operation of the device at these or any other conditions above those listed in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect product reliability.

Electrical Characteristics - Input/Supply/Common Output Parameters

T_A= 0 - 70°C; Supply Voltage V_DD= 3.3 V +/-5%

PARAMETER

Input High Voltage

Input Low Voltage

Input High Current

SYMBOL

CONDITIONS

MIN

TYP

MAX

V_DD+ 0.3

0.8

UNITS

V_IH

V_IL

I_IH

2

V_SS- 0.3

-5

V

V_IN= V_DD

5

A

µ

I_IL1

V_IN= 0 V; Inputs with no pull-up resistors

-5

µA

Input Low Current

V_IN= 0 V; Inputs with pull-up resistors

I_IL2

-200

229

I_DD3.3OPC_L= Full load; Select @ 100 MHz

I_DD3.3OPC_L=Full load; Select @ 133 MHz

mA

240

360

Operating Supply

Current

mA

220

234

236

245

I_DD3.3OPC_L= Full load; Select @ 200 MHz

I_DD3.3PD

360

45

Powerdown Current

Input Frequency

Pin Inductance

mA

MHz

nH

pF

F_i

V_DD= 3.3 V

14.318

L_pin

7

5

C_IN

Logic Inputs

Input Capacitance¹

Transition time¹

C_OUT

C_INX

T_trans

T_s

6

pF

ms

ns

Output pin capacitance

27

45

3

X1 & X2 pins

To 1st crossing of target frequency

From 1st crossing to 1% target frequency

From V_DD= 3.3 V to 1% target frequency

Settling time¹

3

Clk Stabilization¹

T_STAB

3

t_PZH,t_PZL

t_PHZ,t_PLZ

1

10

Output enable delay (all outputs)

Output disable delay (all outputs)

Delay¹

ns

¹Guaranteed by design, not 100% tested in production.

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Electrical Characteristics - CPU 0.7V Current Mode Differential Pair

T_A= 0 - 70°C; V_DD= 3.3 V +/-5%; C_L=2pF

PARAMETER

SYMBOL

Zo¹

CONDITIONS

V_O= V_x

MIN

TYP

MAX

850

UNITS NOTES

Current Source Output

Impedance

3000

Ω

1

Statistical measurement on

single ended signal using

oscilloscope math function.

Voltage High

Voltage Low

VHigh

VLow

660

770

5

1

mV

-150

150

Max Voltage

Min Voltage

Crossing Voltage (abs)

Vovs

Vuds

Vcross(abs)

Measurement on single ended

signal using absolute value.

756

-7

350

1150

1

mV

-300

250

550

140

Variation of crossing over all

edges

see Tperiod min-max values

200MHz nominal

Crossing Voltage (var)

Long Accuracy

d-Vcross

ppm

12

1

-300

300

ppm

ns

ps

1,2

2

1,2

1

4.9985

5.9982

7.4978

9.9970

4.8735

5.8732

7.3728

9.8720

175

5.0015

5.0266

6.0018

6.0320

7.5023

5.4000

10.0030

10.0533

200MHz spread

166.66MHz nominal

166.66MHz spread

133.33MHz nominal

133.33MHz spread

100.00MHz nominal

100.00MHz spread

Average period

Tperiod

200MHz nominal

166.66MHz nominal/spread

133.33MHz nominal/spread

100.00MHz nominal/spread

V_OL= 0.175V, V_OH= 0.525V

Absolute min period

T_absmin

Rise Time

Fall Time

t_r

332

344

30

700

125

t_f

V_OH= 0.525V V_OL= 0.175V

175

ps

1

Rise Time Variation

Fall Time Variation

d-t_r

d-t_f

30

Measurement from differential

wavefrom

V_T= 50%

Measurement from differential

wavefrom

Duty Cycle

Skew

d_t3

t_sk3

45

49

8

55

%

ps

1

100

150

Jitter, Cycle to cycle

t_jcyc-cyc

60

¹Guaranteed by design, not 100% tested in production.

²All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at

14.31818MHz

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Programmable Timing Control Hub^TMfor P4^TM

Electrical Characteristics - PCICLK

T_A= 0 - 70°C; VDD=3.3V +/-5%; C_L= 10-30 pF (unless otherwise specified)

PARAMETER

Output Frequency

Output Impedance

Output High Voltage

Output Low Voltage

Output High Current

Output Low Current

Rise Time

SYMBOL

F_O1

CONDITIONS

MIN

TYP

33.33

33

MAX

55

UNITS

MHz

Ω

1

R_DSP1

V_O= V_DD*(0.5)

I_OH= -1 mA

I_OL= 1 mA

12

1

V_OH

2.4

V

1

V_OL

0.55

-33

38

2

V

1

V _OH@MIN= 1.0 V, V _OH@MAX= 3.135 V

V_{OL @MIN}= 1.95 V, V_{OL @MAX}= 0.4 V

V_OL= 0.4 V, V_OH= 2.4 V

-33

30

mA

ns

I_OH

1

I_OL

1

t_r1

0.5

1.29

1.45

1

Fall Time

t_f1

V_OH= 2.4 V, V_OL= 0.4 V

2

ns

1

Duty Cycle

%

d_t1

V_T= 1.5 V

45

51

55

1

Skew

t_sk1

190

124

500

250

ps

1

t_jcyc-cyc

Jitter,cycle to cyc

¹Guaranteed by design, not 100% tested in production.

Electrical Characteristics - 3V66

T_A= 0 - 70°C; VDD=3.3V +/-5%; C_L= 10-30 pF (unless otherwise specified)

PARAMETER

Output Frequency

Output Impedance

Output High Voltage

Output Low Voltage

Output High Current

Output Low Current

Rise Time

SYMBOL

F_O1

CONDITIONS

MIN

TYP MAX UNITS

66.67

33

MHz

Ω

1

R_DSP1V_O= V_DD*(0.5)

12

55

1

V_OH

I_OH= -1 mA

I_OL= 1 mA

2.4

V

1

V_OL

0.55

-33

38

2

V

1

V _OH@MIN= 1.0 V, V _OH@MAX= 3.135 V

V_{OL @MIN}= 1.95 V, V_{OL @MAX}= 0.4 V

V_OL= 0.4 V, V_OH= 2.4 V

-33

30

mA

ns

%

I_OH

1

I_OL

1

t_r1

0.5

1.28

1.36

1

Fall Time

t_f1

V_OH= 2.4 V, V_OL= 0.4 V

2

1

Duty Cycle

d_t1

V_T= 1.5 V

45

53.1

90

55

1

Skew

Jitter

t_sk1

250

ps

1

t_jcyc-cycV_T= 1.5 V 3V66

128

¹Guaranteed by design, not 100% tested in production.

IDT^TMProgrammable Timing Control Hub^TMfor P4^TM

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Programmable Timing Control Hub^TMfor P4^TM

Un-Buffered Mode 3V66 & PCI Phase Relationship

All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no

defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard

skew described below as Tpci.

3V66 (1:0)

3V66 (4:2)

3V66_5

Tpci

PCICLK_F (2:0) PCICLK (6:0)

Group Skews at Common Transition Edges: (Un-Buffered Mode)

GROUP

SYMBOL

CONDITIONS

3V66 pin to pin skew

PCI_F and PCI pin to pin skew

MIN

TYP MAX UNITS

3V66

PCI

3V66

PCI

0

1.5

500

3.5

ps

ns

3V66 to PCI

S_3V66-PCI3V66 leads 33MHz PCI

¹Guaranteed by design, not 100% tested in production.

PD# Functionality

PCICLK_F

PCICLK

USB/DOT

48MHz

CPU_STOP#

CPUT

CPUC

3V66

66MHz_OUT

PCICLK

1

0

Normal

Float

66MHz

Low

66MHz_IN

Low

66MHz_IN 66MHz_IN

Low Low

48MHz

Low

iref * Mult

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PCI_STOP# - Assertion (transition from logic "1" to logic "0")

The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low

in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising

edge.

Assertion of PCI_STOP# Waveforms

PCI_STOP#

PCI_F[2:0] 33MHz

PCI[6:0] 33MHz

tsu

CPU_STOP# - Assertion (transition from logic "1" to logic "0")

The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I²C configuration to be stoppable via

assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.

The final state of the stopped CPU signals is CPUT=High and CPUC=Low.There is to be no change to the output drive current

values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.

Assertion of CPU_STOP# Waveforms

CPU_STOP#

CPUT

CPUC

CPU_STOP# Functionality

CPU_STOP#

CPUT

CPUC

1

0

Normal

Float

iref * Mult

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In Millimeters

In Inches

c

N

SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS

MIN

2.41

0.20

0.13

MAX

2.80

0.40

0.34

0.25

MIN

.095

.008

.005

MAX

.110

.016

.0135

.010

L

A

A1

b

E1

E

INDEX

AREA

c

D

E

E1

e

SEE VARIATIONS

10.03

7.40

10.68

7.60

.395

.291

.420

.299

1

2

0.635 BASIC

0.025 BASIC

a

hh xx 4455°°

h

L

0.38

0.50

0.64

1.02

.015

.020

.025

.040

D

N

α

SEE VARIATIONS

0°

8°

0°

8°

A

VARIATIONS

D mm.

A1

D (inch)

N

- CC --

MIN

MAX

MIN

.720

MAX

.730

56

18.31

18.55

e

SEATING

PLANE

b

Reference Doc.: JEDEC Publication 95, MO-118

.10 (.004)

C

10-0034

300 mil SSOP Package

Ordering Information

950201yFLF-T

Example:

XXXX y F LF- T

Designation for tape and reel packaging

Lead Free (Optional)

Package Type

F = SSOP

Revision Designator (will not correlate with datasheet revision)

Device Type

IDT^TMProgrammable Timing Control Hub^TMfor P4^TM

460J—01/25/10

13

ICS950201

Programmable Timing Control Hub^TMfor P4^TM

c

N

In Millimeters

In Inches

L

SYMBOL

COMMON DIMENSIONS COMMON DIMENSIONS

MIN

--

0.05

0.80

0.17

0.09

MAX

1.20

0.15

1.05

0.27

0.20

MIN

--

.002

.032

.007

.0035

SEE VARIATIONS

0.319 BASIC

.236

MAX

.047

.006

.041

.011

.008

E1

E

A

A1

A2

b

c

D

E

E1

e

INDEX

AREA

1

22

SEE VARIATIONS

8.10 BASIC

6.00

a

D

6.20

.244

0.50 BASIC

0.020 BASIC

L

0.45

0.75

.018

.030

N

α

aaa

SEE VARIATIONS

A

A2

0°

--

8°

0.10

0°

--

8°

.004

A1

- CC --

VARIATIONS

D mm.

D (inch)

e

SEATING

PLANE

N

b

MIN

13.90

MAX

14.10

MIN

.547

MAX

.555

56

aaa

C

Reference Doc.: JEDEC Publication 95, MO-153

10-0039

6.10 mm. Body, 0.50 mm. pitch TSSOP

(0.020 mil)

(240 mil)

Ordering Information

950201yGLF-T

Example:

XXXX y G LF- T

Designation for tape and reel packaging

Lead Free (Optional)

Package Type

G = TSSOP

Revision Designator (will not correlate with datasheet revision)

Device Type

IDT^TMProgrammable Timing Control Hub^TMfor P4^TM

460J—01/25/10

14

ICS950201

Programmable Timing Control Hub^TMfor P4^TM

Revision History

Rev.

Issue Date Description

Page #

J

1/25/2010 Updated document template

Innovate with IDT and accelerate your future networks. Contact:

www.IDT.com

For Sales

For Tech Support

800-345-7015

408-284-6578

408-284-8200

pcclockhelp@idt.com

Fax: 408-284-2775

Corporate Headquarters

Asia Pacific and Japan

Europe

Integrated Device Technology, Inc.

6024 Silver Creek Valley Road

San Jose, CA 95138

United States

800 345 7015

Integrated Device Technology

Singapore (1997) Pte. Ltd.

Reg. No. 199707558G

435 Orchard Road

#20-03 Wisma Atria

Singapore 238877

IDT Europe, Limited

Prime House

Barnett Wood Lane

Leatherhead, Surrey

United Kingdom KT22 7DE

+44 1372 363 339

+408 284 8200 (outside U.S.)

+65 6 887 5505

TM

©

of Integrated Device Technology, Inc. Accelerated Thinking is service mark of Integrated Device Technology, Inc. All other brands, product names and marks

a

are or may be trademarks or registered trademarks used to identify products or services of their respective owners.

Printed in USA

15

型号:	9502-10000
是否Rohs认证：	符合
生命周期：	Active
Reach Compliance Code：	unknown
风险等级：	5.57
连接器支架类型：	WIRE AND CABLE
Base Number Matches：	1

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