9EX21801AKLF全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

DATASHEET

ICS9EX21801A

18 Output PCIe G2/QPI Differential Buffer with 2:1 input

mux

Description

Features/Benefits

•

Supports output clock frequencies up to 400 MHz

The ICS9EX21801 provides 18 output clocks for PCIe Gen2

(100MHz) or QPI (133MHz) applications. The 9EX21801 has 4

selectable SMBus addresses, and dedicated CKPWRGD/PD#

and VDDA pins for easy board design. A differential CPU clock

from a CK410B+ main clock generator, such as the ICS932S421,

drives the ICS9EX21801. In fanout mode, the 9EX21801 provides

outputs up to 400MHz.

4 Selectable SMBus addresses

SMBus address is independent of PLL operating mode

Dedicated CKPWRGD/PD# and VDDA pins ease board

design

Key Specifications

•

DIF output cycle-to-cycle jitter < 50ps

DIF output-to-output skew < 150 ps

PCIe Gen2 compliant phase noise

QPI 133MHz compliant phase noise

Funtional Block Diagram

OE(17:15)#

OE(14:5)#,

OE_01234#

12

CLKA_IN

CLKA_IN#

PLL

(SS Compatible)

18

DIF(17:0)

CLKB_IN

CLKB_IN#

HIBW_BYPM_LOBW#

100M_133M#

CKPWRGD/PD#

SMB_A0

Logic

SMB_A1

SEL_A_B#

SMBDAT

SMBCLK

IREF

IDT^TM18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

1463B — 01/20/10

1

ICS9EX21801A

Datasheet

18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

Pin Configuration

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55

VDD

OE10#

DIF_10

DIF_10#

OE11#

DIF_11

DIF_11#

OE12#

DIF_12

1

2

3

4

5

6

7

8

9

54 DIF_6#

53 DIF_6

52 OE6#

51 DIF_5#

50 DIF_5

49 OE5#

48 DIF_4#

47 DIF_4

46 DIF_3#

45 DIF_3

44 GND

9EX21801AKLF

DIF_12# 10

GND 11

VDD 12

43 VDD

DIF_13 13

DIF_13# 14

OE13# 15

DIF_14 16

DIF_14# 17

OE14# 18

42 DIF_2#

41 DIF_2

40 DIF_1#

39 DIF_1

38 DIF_0#

37 DIF_0

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

72-pin MLF

Frequency/Functionality Table

Byte 0,

bit 2

(100_133M#

Latch)

Power Groups

Byte 0,

bit 1

FSB

Byte 0,

bit 0

FSA

Input

MHz

DIF_x

MHz

Pin Number

VDD

29

Description

GND

28

Notes

1

0

1

100.00 100.00

133.33 133.33

166.67 166.67

200.00 200.00

266.67 266.67

333.33 333.33

400.00 400.00

Reserved

1

2

0

1

0

1

0

1

Main PLL, Analog

DIF clocks

1,12,21,35,43,55 11,32,44

Power Down Functionality

INPUTS

OUTPUTS

DIF_x

Running

Hi-Z

PLL State

CKPWRGD/PD#

Input

Running

X

1

0

ON

OFF

Notes:100M_133M#

1. Latch selects between 100 and 133 MHz.

This is equivalent to FSC in CK410B+/CK509B FS table.

2. Writing Byte 0 bits (2:0) can select other frequencies.

These frequencies are not characterized in PLL Mode

SMBus Address Selection (pins 66, 67)

SMB_A1

SMB_A0

Address

D4

0

1

0

1

0

1

HIBW_BYPM_LOBW# Selection (Pin 63)

D6

D8

DA

State

Low

Mid

Voltage

<0.8V

1.2<Vin<1.8V

Vin > 2.0V

Mode

Low BW

Bypass

High BW

High

IDT^TM18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

1463B — 01/20/10

2

ICS9EX21801A

Datasheet

18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

Pin Description

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

1

VDD

PWR

Power supply, nominal 3.3V

Active low input for enabling DIF pair 10.

1 = tri-state outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential complement clock output

Active low input for enabling DIF pair 11.

1 = tri-state outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential complement clock output

Active low input for enabling DIF pair 12.

1 = tri-state outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential complement clock output

Ground pin.

2

OE10#

IN

3

4

DIF_10

DIF_10#

OUT

5

OE11#

IN

6

7

DIF_11

DIF_11#

OUT

8

OE12#

IN

9

DIF_12

DIF_12#

GND

VDD

DIF_13

DIF_13#

OUT

PWR

OUT

10

11

12

13

14

Power supply, nominal 3.3V

0.7V differential true clock output

0.7V differential complement clock output

Active low input for enabling DIF pair 13.

1 = tri-state outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential complement clock output

Active low input for enabling DIF pair 14.

1 = tri-state outputs, 0 = enable outputs

0.7V differential true clock output

15

OE13#

IN

16

17

DIF_14

DIF_14#

OUT

18

OE14#

IN

19

20

21

DIF_15

DIF_15#

VDD

OUT

PWR

0.7V differential complement clock output

Power supply, nominal 3.3V

Active low input for enabling DIF pairs 15, 16 and 17

1 = tri-state outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential complement clock output

0.7V differential true clock output

22

OE15_17#

IN

23

24

25

26

DIF_16

DIF_16#

DIF_17

DIF_17#

OUT

0.7V differential complement clock output

This pin establishes the reference current for the differential current-mode output pairs. This pin

requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475

ohms is the standard value.

27

IREF

OUT

28

29

30

31

32

33

34

35

GNDA

VDDA

PWR

IN

PWR

IN

Ground pin for the PLL core.

3.3V power for the PLL core.

True Input for differential reference clock.

Complement Input for differential reference clock.

Ground pin.

True Input for differential reference clock.

Complement Input for differential reference clock.

Power supply, nominal 3.3V

CLKA_IN

CLKA_IN#

GND

CLKB_IN

CLKB_IN#

VDD

IN

PWR

Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.

1 = tri-state outputs, 0 = enable outputs

36

OE_01234#

IN

IDT^TM18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

1463B — 01/20/10

3

ICS9EX21801A

Datasheet

18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

Pin Description (continued)

PIN #

37

PIN NAME

PIN TYPE

OUT

DESCRIPTION

DIF_0

0.7V differential true clock output

38

39

40

41

42

43

44

45

DIF_0#

DIF_1

DIF_1#

DIF_2

DIF_2#

VDD

OUT

0.7V differential complement clock output

0.7V differential true clock output

0.7V differential complement clock output

0.7V differential true clock output

0.7V differential complement clock output

Power supply, nominal 3.3V

Ground pin.

0.7V differential true clock output

0.7V differential complement clock output

0.7V differential true clock output

0.7V differential complement clock output

Active low input for enabling DIF pair 5.

1 = tri-state outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential complement clock output

Active low input for enabling DIF pair 6.

1 = tri-state outputs, 0 = enable outputs

0.7V differential true clock output

OUT

PWR

OUT

GND

DIF_3

DIF_3#

DIF_4

DIF_4#

46

47

48

OUT

49

OE5#

IN

50

51

DIF_5

DIF_5#

OUT

52

OE6#

IN

53

54

55

DIF_6

DIF_6#

VDD

OUT

PWR

0.7V differential complement clock output

Power supply, nominal 3.3V

Active low input for enabling DIF pair 7.

1 = tri-state outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential complement clock output

Active low input for enabling DIF pair 8.

1 = tri-state outputs, 0 = enable outputs

0.7V differential true clock output

56

OE7#

IN

57

58

DIF_7

DIF_7#

OUT

59

OE8#

IN

60

61

DIF_8

DIF_8#

OUT

0.7V differential complement clock output

Input to select operating frequency

62

63

100M_133M#

IN

0 = 133MHz (QPI), 1 = 100.00MHz (PCIe Gen2)

Trilevel input to select High BW, Bypass Mode or Low BW.

0 = Low BW Mode, Mid= Bypass Mode, 1 = High Bandwidth

Clock pin of SMBUS circuitry, 5V tolerant

Data pin of SMBUS circuitry, 5V tolerant

HIBW_BYPM_LOBW#

64

65

66

67

SMBCLK

SMBDAT

SMB_A1

SMB_A0

IN

I/O

IN

SMBus address bit 1

SMBus address bit 0 (LSB)

IN

Input to select differential input clock A or differential input clock B.

0 = Input B selected, 1 = Input A selected.

Notifies the clock to sample latched inputs on the rising edge, and to power down on the falling

edge.

68

69

SEL_A_B#

IN

CKPWRGD/PD#

70

71

DIF_9

DIF_9#

OUT

0.7V differential true clock output

0.7V differential complement clock output

Active low input for enabling DIF pair 9.

1 = tri-state outputs, 0 = enable outputs

72

OE9#

IN

IDT^TM18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

1463B — 01/20/10

4

ICS9EX21801A

Datasheet

18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

Absolute Maximum Ratings

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS Notes

1

3.3V Core Supply

Voltage

VDD_A

GND - 0.5

V_DD+ 0.5

V

3.3V Logic Supply

Voltage

1

VDD

Ts

V_DD+ 0.5

V

^°C

°C

V

1

Storage Temperature

-65

0

150

70

115

Ambient Operating Temp Tambient

Case Temperature

Tcase

Input ESD protection

ESD prot

Human Body Model

2000

Electrical Characteristics - Input/Supply/Common Output Parameters

T_A= 0 - 70°C; Supply Voltage V_DD= 3.3 V +/-5%

PARAMETER

SYMBOL

CONDITIONS

3.3 V +/-5%

MIN

2

TYP

MAX UNITS NOTES

Input High Voltage

V_IH

V_DD+ 0.3

V

Input Low Voltage

Input High Current

V_IL

I_IH

3.3 V +/-5%

V_IN= V_DD

GND - 0.3

-5

0.8

5

V

uA

V_IN= 0 V; Inputs with no pull-up

resistors

I_IL1

-5

uA

Input Low Current

I_IL2

V_IN= 0 V; Inputs with pull-up resistors

Full Active, C_L= Full load;

-200

uA

mA

Digital Supply Current

Analog Supply Current

I_DD3.3D

450

40

1

I_DD3.3A

Full Active, C_L= Full load;

Digital Powerdown

Current

Analog Powerdown

Current

I_DD3.3DPD

I_DD3.3APD

all differential pairs tri-stated

15

20

F_iPLL

F_iBYPASS

L_pin

PLL Mode

80

33

150

400

7

MHz

nH

1

Input Frequency

Pin Inductance

Capacitance

Bypass Mode

C_IN

Logic Inputs

1.5

5

pF

C_OUT

Output pin capacitance

6

pF

From V_DDPower-Up and after input

clock stabilization or de-assertion of

PD# to 1st clock

Clk Stabilization

T_STAB

1

ms

1

Allowable Spread

Modulation Frequency

f_MOD

t_LATOE#

t_DRVPD

Triangular Modulation

30

4

33

12

kHz

cycles

us

1,3

1,2

DIF start after OE# assertion

DIF stop after OE# deassertion

DIF output enable after

PD de-assertion

OE# Latency

Tdrive_PD

300

1,2

1

Tfall

t_F

Fall time of OE#

5

ns

Trise

t_R

Rise time of OE#

¹Guaranteed by design and characterization, not 100% tested in production.

²Time from deassertion until outputs are >200 mV

³For which spread spectrum tracking error spec will be met.

IDT^TM18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

1463B — 01/20/10

5

ICS9EX21801A

Datasheet

18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

Electrical Characteristics - Clock Input Parameters

T_A= 0 - 70°C; Supply Voltage V_DD= 3.3 V +/-5%

PARAMETER

SYMBOL

CONDITIONS

MIN

600

TYP

800

MAX UNITS NOTES

Input High Voltage -

DIF_IN

Input Low Voltage -

DIF_IN

Input Common Mode

Voltage - DIF_IN

Differential inputs

(single-ended measurement)

Differential inputs

V_IHDIF

1150

300

mV

1

V_ILDIF

V_COM

V_SS- 300

300

0

(single-ended measurement)

Common Mode Input Voltage

Peak to Peak value

1000

1450

Input Amplitude - DIF_IN

V_SWING

300

Input Slew Rate - DIF_IN

Input Leakage Current

Input Duty Cycle

dv/dt

I_IN

Measured differentially

0.4

-5

8

5

V/ns

uA

1,2

1

V_IN= V_{DD ,}V_IN= GND

Measurement from differential

wavefrom

d_tin

45

55

%

1

Input Jitter - Cycle to

Cycle

J_DIFIn

Differential Measurement

0

125

ps

1

¹Guaranteed by design and characterization, not 100% tested in production.

Electrical Characteristics - DIF 0.7V Current Mode Differential Pairs

Ω

T_A= 0 - 70°C; V_DD= 3.3 V +/-5%; C_L=2pF, R_S=33.2 , R_P=49.9 , R_REF=475 , 10 inch transmission lines

PARAMETER

SYMBOL

Zo¹

CONDITIONS

MIN

TYP

MAX UNITS NOTES

Current Source Output

Impedance

Ω

V_O= V_x

3000

1

Statistical measurement on single

ended signal using oscilloscope math

function.

Voltage High

Voltage Low

VHigh

VLow

660

850

1,3

mV

-150

150

Max Voltage

Min Voltage

Crossing Voltage (abs)

Crossing Voltage (var)

Long Accuracy

Vovs

Vuds

Vcross(abs)

d-Vcross

ppm

Measurement on single ended signal

using absolute value.

1150

1

1,2

1

-300

250

550

140

0

mV

ppm

ps

Variation of crossing over all edges

see Tperiod min-max values

V_OL= 0.175V, V_OH= 0.525V

Rise Time

t_r

175

700

Fall Time

t_f

V_OH= 0.525V V_OL= 0.175V

700

125

ps

1

Rise Time Variation

Fall Time Variation

d-t_r

d-t_f

Measurement from differential

wavefrom

Duty Cycle

d_t3

45

55

%

1

PLL mode

BYPASS mode as additive jitter

¹Guaranteed by design and characterization, not 100% tested in production.

50

ps

1,5

1,4

Jitter, Cycle to cycle

t_jcyc-cyc

²All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with

CK410B+/CK509B accuracy requirements. The 9EX21801 itself does not contribute to ppm error.

3

Ω

I_REF= V_DD/(3xR_R). For R_R= 475 (1%), I_REF= 2.32mA. I_OH= 6 x I_REFand V_OH= 0.7V @ Z_O=50 .

⁴Applies to Bypass Mode Only

IDT^TM18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

1463B — 01/20/10

6

ICS9EX21801A

Datasheet

18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

Electrical Characteristics - Skew and Differential Jitter Parameters

T_A= 0 - 70°C; Supply Voltage V_DD= 3.3 V +/-5%

Group

Parameter

Description

Input-to-Output Skew in PLL mode (1:1 only),

nominal value @ 25°C, 3.3V, 100MHz

Input-to-Output Skew in PLL mode (1:1 only),

nominal value @ 25°C, 3.3V, 133MHz

Input-to-Output Skew in Bypass mode (1:1 only),

nominal value @ 25°C, 3.3V

Min

TYP Max Units

Notes

t_{SPO_PLL100M}

CLK_IN, DIF[x:0]

950 1000 1125

ps

ns

1,2,4,5,8

t_{SPO_PLL133M}

t_{PD_BYP}

CLK_IN, DIF[x:0]

1100 1125 1175

1,2,4,5,8

1,2,3,5

4

4.7

5.2

Input-to-Output Skew Variation in PLL mode

(over specified voltage / temperature operating ranges)

1,2,4,5,6,

10

∆t_{SPO_PLL}

∆t_{PD_BYP}

t_{SKEW_A19}

CLK_IN, DIF [x:0]

DIF[17:0]

|250| |350|

|800| |900|

100 150

ps

Input-to-Output Skew Variation in Bypass mode

(over specified voltage / temperature operating ranges)

1,2,3,4,5,

6,10

Output-to-Output Skew across all 18 outputs

(Common to Bypass and PLL mode - all outputs at same gear)

1,2,3

t_JPH

DIF[17:0]

Differential Phase Jitter (RMS Value)

2

10

80

ps

1,4,7

1,4,9

t_SSTERROR

Differential Spread Spectrum Tracking Error (peak to peak)

20

NOTES:

1. Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.

2. Measured from differential cross-point to differential cross-point

3. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.

4. This parameter is deterministic for a given device

5. Measured with scope averaging on to find mean value.

6. Long-term variation from nominal of input-to-output skew over temperature and voltage for a single device.

7. This parameter is measured at the outputs of two separate ICS9EX21801 devices driven by a single CK410B+. The ICS9EX21801's must be set to high bandwidth.

Differential phase jitter is the accumulation of the phase jitter not shared by the outputs (eg. not including the affects of spread spectrum). Target ranges of consideration are

agents with BW of 1-22Mhz and 11-33Mhz.

8. t is the period of the input clock

9. Differential spread spectrum tracking error is the difference in spread spectrum tracking between two ICS9EX21801 devices This parameter is measured at the outputs of

two separate ICS9EX21801 devices driven by a single CK410B+ in Spread Spectrum mode. The ICS9EX21801's must be set to high bandwidth. The spread spectrum

characteristics are: maximum of 0.5%, 30-33KHz modulation frequency, linear profile.

10. This parameter is an absolute value. It is not a double-sided figure.

IDT^TM18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

1463B — 01/20/10

7

ICS9EX21801A

Datasheet

18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

Electrical Characteristics - Phase Jitter (PLL Mode)

NOTES

PARAMETER

PLL Bandwidth

PLL Jitter Peaking

SYMBOL

BWH

BWL

jPKH

jPKL

CONDITIONS*

High Bandwidth Selected

Low Bandwidth Selected

High Bandwidth Selected

Low Bandwidth Selected

PCIe Gen 1

MIN

2

0.7

TYP.

3

1

2.5

2

MAX UNITS

4

2

3

MHz

dB

2.5

dB

36/42

108

3

ps

1,2

(1.5 - 22 MHz)

PCIe Gen 2

(8-16 MHz, 5-16 MHz)

Lo-band content (10kHz to 1.5MHz)

PCIe Gen 2

(8-16 MHz, 5-16 MHz)

Hi-band content (1.5MHz to Nyquist)

1.1/1.2

ps rms

tjphase_LoBW

2.0/2.1

3.1

ps rms

1,2

QPI_133MHz (4.8Gb, 12 UI)

QPI_133MHz (6.4Gb, 12 UI)

0.24/0.25

0.18/0.19

28/32

0.5

86

ps rms 2, 3

Jitter, Phase

PCIe Gen 1

(1.5 - 22 MHz)

PCIe Gen 2

ps

1,2

(8-16 MHz, 5-16 MHz)

Lo-band content (10kHz to 1.5MHz)

PCIe Gen 2

(8-16 MHz, 5-16 MHz)

Hi-band content (1.5MHz to Nyquist)

1.2/1.5

2.6/2.7

3

ps rms

tjphase_HIBW

3.1

ps rms

1,2

QPI_133MHz (4.8Gb, 12 UI)

QPI_133MHz (6.4Gb, 12 UI)

0.27/0.28

0.2/0.21

0.5

ps rms 2, 3

Notes on Phase Jitter: (Guaranteed by design and characterization, not tested in production)

¹See http://www.pcisig.com for complete specs. First number is Spread Spectrum Off, second is Spread Spectrum On.

²Device driven by IDT CK410B+ (932S421CGLF) or CK509B (932S509EKLF) or equivalent

³Calculated from Intel Supplied Clock Jitter Tool 1.5.1. First number is Spread Spectrum Off, second is Spread Spectrum On

IDT^TM18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

1463B — 01/20/10

8

ICS9EX21801A

Datasheet

18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

General SMBus serial interface information for the ICS9EX21801A

How to Write:

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the write address D4_(h)

• ICS clock will acknowledge

• Controller (host) sends a start bit.

• Controller (host) sends the write address D4_(h)

• ICS clock will acknowledge

• Controller (host) sends the begining byte location = N

• ICS clock will acknowledge

• Controller (host) sends the begining byte

location = N

• Controller (host) sends the data byte count = X

• ICS clock will acknowledge

• Controller (host) starts sending Byte N through

Byte N + X -1

• ICS clock will acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read address D5_(h)

• ICS clock will acknowledge

• ICS clock will acknowledge each byte one at a time

• ICS clock will send the data byte count = X

• ICS clock sends Byte N + X -1

• Controller (host) sends a Stop bit

• ICS clock sends Byte 0 through byte X (if X_(h)

was written to byte 8).

• Controller (host) will need to acknowledge each byte

• Controllor (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

Index Block Read Operation

Index Block Write Operation

Controller (Host)

ICS (Slave/Receiver)

Controller (Host)

ICS (Slave/Receiver)

starT bit

T

starT bit

T

Slave Address D4_(h)*

WR

WRite

WR

WRite

Beginning Byte = N

Data Byte Count = X

Beginning Byte N

ACK

Beginning Byte = N

RT

Repeat starT

Slave Address D5_(h)*

RD

ReaD

ACK

Data Byte Count = X

Beginning Byte N

ACK

Byte N + X - 1

ACK

P

stoP bit

Byte N + X - 1

N

P

Not acknowledge

stoP bit

Note: The address is selectable among 4 values (page 2).

IDT^TM18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

1463B — 01/20/10

9

ICS9EX21801A

Datasheet

18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

9EX21801 SMBus Addressing

SMB_A(2:0) = 000

SMB Adr: D0

(DB1200G/GS)

(DB1900G/GS)

SMB_A(2:0) = 001

SMB Adr: D2

(DB1200G/GS)

OR

(CK410B+/CK509B)

(DB1900G/GS)

SMB_A(1:0) = 00

SMB Adr: D4

SMB_A(2:0) = 010

SMB Adr: D4

(DB1200G/GS)

OR

9EX21801

(DB1900G/GS)

SMB_A(1:0) = 01

SMB Adr: D6

SMB_A(2:0) = 011

SMB Adr: D6

(DB1200G/GS)

`

9EX21801

(DB1900G/GS)

SMB_A(1:0) = 10

SMB Adr: D8

SMB_A(2:0) = 100

SMB Adr: D8

(DB1200G/GS)

9EX21801

(DB1900G/GS)

SMB_A(1:0) = 11

SMB Adr: DA

SMB_A(2:0) = 101

SMB Adr: DA

(DB1200G/GS)

9EX21801

(DB1900G/GS)

SMB_A(2:0) = 110

SMB Adr: DC

(DB1200G/GS)

SMB Adr: DC

9DB403/803

(DB400E/800E)

OR

(DB1900G/GS)

SMB_A(2:0) = 111

SMB Adr: DE

(DB1200G/GS)

(DB1900G/GS)

IDT^TM18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

1463B — 01/20/10

10

ICS9EX21801A

Datasheet

18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

SMBusTable: Output, and PLL BW Control Register

Byte 0

Pin #

Name

Control Function

Type

0

1

PWD

00 = Low BW (1MHz)

10 = Bypass

11 = High BW (3MHz)

PLL_BW# adjust

RW

Latch

Bit 7

4

BYPASS# test mode / PLL

RW

Latch

Bit 6

DIF_17

DIF_16

Output Control

RW

Hi-Z

Enable

1

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RESERVED

0

Latch

0

-

100M_133M#

FSB

Frequency Select Bit C

Frequency Select Bit B

Frequency Select bit A

RW

133MHz

See Frequency Select

Table

100MHz

FSA

1

SMBusTable: Output Control Register

Byte 1

Bit 7

Pin #

Name

DIF_7

DIF_6

DIF_5

DIF_4

DIF_3

DIF_2

DIF_1

DIF_0

Control Function

Output Control

Type

RW

0

1

PWD

Hi-Z

Enable

1

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBusTable: Output Control Register

Byte 2

Bit 7

Pin #

Name

DIF_15

DIF_14

DIF_13

DIF_12

DIF_11

DIF_10

Control Function

Output Control

Type

RW

0

1

PWD

Hi-Z

Enable

1

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

DIF_9

DIF_8

Output Control

RW

Hi-Z

Enable

1

Bit 1

Bit 0

SMBusTable: Output Enable Readback Register

Byte 3

Bit 7

Pin #

5

2

72

59

56

52

49

36

Name

OE11# Input

OE10# Input

OE9# Input

OE8# Input

OE7# Input

OE6# Input

OE5# Input

OE_01234# Input

Control Function

Pin Readback

Type

R

0

1

PWD

X

Pin Low

Pin Hi

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

IDT^TM18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

1463B — 01/20/10

11

ICS9EX21801A

Datasheet

18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

SMBusTable: Output Enable Readback Register

Byte 4

Bit 7

Pin #

Name

Control Function

RESERVED

Pin Readback

Type

0

1

PWD

0

X

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

62

100M_133M# Input

SEL_A_B# Input

OE15_17# Input

OE14# Input

133M

100M

Input A

Pin Hi

R

68

22

18

15

8

Input B

Pin Low

OE13# Input

OE12# Input

Note: For an output to be enabled, BOTH the Output Enable Bit and the OE# pin must be enabled.

This means that the Output Enable Bit must be '1' and the corresponding OE# pin must be '0'.

SMBusTable: Vendor & Revision ID Register

Byte 5

Bit 7

Pin #

-

Name

RID3

RID2

RID1

RID0

VID3

VID2

VID1

VID0

Control Function

Type

R

0

-

1

-

PWD

0

1

0

1

-

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

REVISION ID

VENDOR ID

SMBusTable: DEVICE ID

Byte 6 Pin #

Bit 7

Name

Control Function

Device ID 7 (MSB)

Type

R

0

1

PWD

-

0

1

0

-

Device ID 6

Device ID 5

Device ID 4

Device ID 3

Device ID 2

Device ID 1

Device ID 0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Device ID is 18 hex

SMBusTable: Byte Count Register

Byte 7

Bit 7

Pin #

-

Name

BC7

BC6

BC5

BC4

BC3

BC2

BC1

BC0

Control Function

Type

RW

0

-

1

-

PWD

0

1

-

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Writing to this register

configures how many

bytes will be read back.

IDT^TM18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

1463B — 01/20/10

12

ICS9EX21801A

Datasheet

18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

(Ref. )

Seating Plane

(N_D- 1)x

e

&

N_E

N_D

(Ref. )

Even

A1

Index Area

L

A3

E2

N

e

(Typ.)

2

If N &

N_E

D

Anvil

Singulation

are Even

1

2

1

(N - 1)x

e

E

OR

E

(Ref. )

E2

2

Sawn

Singulation

Top View

D

b

e

Thermal

Base

(Ref.)

D2

A

N &

N_E

Odd

D

2

D2

Chamfer 4x

0.6 x 0.6 max

OPTIONAL

C

0.08

THERMALLY ENHANCED, VERY THIN, FINE PITCH

QUAD FLAT / NO LEAD PLASTIC PACKAGE

DIMENSIONS

DIMENSIONS (mm)

SYMBOL

72L

72

18

SYMBOL

MIN.

0.8

0

MAX.

1.0

0.05

N

N_D

A

A1

N_E

18

A3

b

e

0.25 Reference

0.18 0.3

0.50 BASIC

10.00 x 10.00

D x E BASIC

D2 MIN. / MAX.

E2 MIN. / MAX.

L MIN. / MAX.

5.75

0.3

6.15

0.5

Ordering Information

Part / Order Number Shipping Packaging

Package

72-pin MLF

Temperature

0 to +70°C

9EX21801AKLF

9EX21801AKLFT

Tubes

Tape and Reel

“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.

“A” is the device revision designator (will not correlate to the datasheet revision).

IDT^TM18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

1463B — 01/20/10

13

ICS9EX21801A

Datasheet

18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

Revision History

Rev.

Issue Date Description

Page #

0.1

4/29/2008 Initial Release

-

1. SMBus Bytes 11-16 are now reserved

2. SMBus References to 1:1 operating set point register are removed.

5/1/2008 3. Updated readback registers to match new control pins

3. Added QPI phase noise spec

0.2

Various

4. Significant changes to pinout to improve performance

1. Updated/Corrected SMBus, filled in empty bytes

2. Updated Frequency/Functionality Table

3. Added SMBus Address decoding table and graph

4. Corrected Power hook up table.

6/3/2008 Added revision designator to orderng information

1. Updated front page text

0.3

0.4

5/30/2008

Various

12

2. Updated Functionality foot notes on Page 2.

3. Deleted duplicate table on page 6.

4. Corrected DIF 0.7V Current Mode electrical characterisitcs - removed

skew spec.

1,2,6,7,8,

10

0.5

12/8/2008

5. Updated skew and Differential Parameters Table to reflect char data,

added PLL BW and jitterpeaking data to this table.

6. Updated Phase Jitter Table - removed FBD specs and added HiBW and

Low BW sections

7. Added SMBus Addressing Table after page 9

1. Updated PLL mode input frequency range

2. Noted that Modulation frequency is the Allowable Spread Modulation

Frequency. Added foonote 3.

3. Corrected PCIe Gen1 Max phase jitter spec to be 86 ps instead of

108ps. 86ps is the derated limit when using ~160K cycles to calculate the

value. Released to final - Rev A.

A

B

12/17/2008

5,8

4

1/20/2010 1. Corrected Pin Description for Pin 62. 0 = 133M, 1 = 100M.

Innovate with IDT and accelerate your future networks. Contact:

www.IDT.com

For Sales

For Tech Support

800-345-7015

408-284-6578

408-284-8200

pcclockhelp@idt.com

Fax: 408-284-2775

Corporate Headquarters

Asia Pacific and Japan

Europe

Integrated Device Technology, Inc.

6024 Silver Creek Valley Road

San Jose, CA 95138

United States

800 345 7015

Integrated Device Technology

Singapore (1997) Pte. Ltd.

Reg. No. 199707558G

435 Orchard Road

#20-03 Wisma Atria

Singapore 238877

IDT Europe, Limited

Prime House

Barnett Wood Lane

Leatherhead, Surrey

United Kingdom KT22 7DE

+44 1372 363 339

+408 284 8200 (outside U.S.)

+65 6 887 5505

TM

Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks

or registered trademarks used to identify products or services of their respective owners.

Printed in USA

14

型号:	9EX21801AKLF
Brand Name：	Integrated Device Technology
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Obsolete
IHS 制造商：	INTEGRATED DEVICE TECHNOLOGY INC
零件包装代码：	VFQFPN
包装说明：	ROHS COMPLIANT, PLASTIC, MLF-72
针数：	72
制造商包装代码：	NLG72P1
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.81
Is Samacsys：	N
系列：	9EX
输入调节：	DIFFERENTIAL MUX
JESD-30 代码：	S-PQCC-N72
JESD-609代码：	e3
长度：	10 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER
湿度敏感等级：	3
功能数量：	1
反相输出次数：
端子数量：	72
实输出次数：	18
最高工作温度：	70 °C
最低工作温度：
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	HVQCCN
封装等效代码：	LCC72,.39SQ,20
封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260
电源：	3.3 V
认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.15 ns
座面最大高度：	1 mm
子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn) - annealed
端子形式：	NO LEAD
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10 mm
Base Number Matches：	1

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