A C T
™
2 F a m il y F P GA s
D es cr i p t i o n
The ACT™ 2 family represents Actel’s second generation of
field programmable gate arrays (FPGAs). The ACT 2 family
presents a two-module architecture, consisting of C-modules
and S-modules. These modules are optimized for both
combinatorial and sequential designs. Based on Actel’s
patented channeled array architecture, the ACT 2 family
provides significant enhancements to gate density and
performance while maintaining downward compatibility
with the ACT 1 design environment and upward
compatibility with the ACT 3 design environment. The
devices are implemented in silicon gate, 1.0-µm, two-level
metal CMOS, and employ Actel’s PLICE
®
antifuse
O r d e r i n g I nf o r m a t i o n
technology. This revolutionary architecture offers gate array
design flexibility, high performance, and fast
time-to-production with user programming. The ACT 2
family is supported by the Designer and Designer Advantage
Systems, which offers automatic pin assignment, validation
of electrical and design rules, automatic placement and
routing, timing analysis, user programming, and diagnostic
probe capabilities. The systems are supported on the
following platforms: 386/486™ PC, Sun
™
, and HP
™
workstations. The systems provide CAE interfaces to the
following design environments: Cadence, Viewlogic
®
,
Mentor Graphics
®
, and OrCAD™.
A1280
A
–
1
PG
176
C
Application (Temperature Range)
C = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
M = Military (–55 to +125°C)
B = MIL-STD-883
Package Lead Count
Package Type
PL = Plastic J-Leaded Chip Carrier
PQ = Plastic Quad Flat Pack
CQ = Ceramic Quad Flat Pack
PG = Ceramic Pin Grid Array
TQ = Thin (1.4 mm) Quad Flat Pack
VQ = Very Thin (1.0 mm) Quad Flat Pack
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% faster than Standard
–2 = Approximately 25% faster than Standard
Die Revision
A = 1.0-µm CMOS process
Part Number
A1225 = 2500 Gates
A1240 = 4000 Gates
A1280 = 8000 Gates
2
v4.0
ACTEL [ Actel Corporation ]
