Actel Fusion Mixed-Signal FPGAs
tools. Comprehensive programming file support is also included to allow for easy programming of
large numbers of parts with differing FlashROM contents.
SRAM and FIFO
Fusion devices have embedded SRAM blocks along the north and south sides of the device. Each
variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18,
512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that
can be configured with different bit widths on each port. For example, data can be written
through a 4-bit port and read as a single bitstream. The SRAM blocks can be initialized from the
flash memory blocks or via the device JTAG port (ROM emulation mode), using the UJTAG macro.
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the
SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The
FIFO width and depth are programmable. The FIFO also features programmable Almost Empty
(AEMPTY) and Almost Full (AFULL) flags in addition to the normal EMPTY and FULL flags. The
embedded FIFO control unit contains the counters necessary for the generation of the read and
write address pointers. The SRAM/FIFO blocks can be cascaded to create larger configurations.
Clock Resources
PLLs and Clock Conditioning Circuits (CCCs)
Fusion devices provide designers with very flexible clock conditioning capabilities. Each member of
the Fusion family contains six CCCs. In the two larger family members, two of these CCCs also
include a PLL; the smaller devices support one PLL.
The inputs of the CCC blocks are accessible from the FPGA core or from one of several inputs with
dedicated CCC block connections.
The CCC block has the following key features:
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Wide input frequency range (f
IN_CCC
) = 1.5 MHz to 350 MHz
Output frequency range (f
OUT_CCC
) = 0.75 MHz to 350 MHz
Clock phase adjustment via programmable and fixed delays from –6.275 ns to +8.75 ns
Clock skew minimization (PLL)
Clock frequency synthesis (PLL)
On-chip analog clocking resources usable as inputs:
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–
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100 MHz on-chip RC oscillator
Crystal oscillator
Additional CCC specifications:
Internal phase shift = 0°, 90°, 180°, and 270°
Output duty cycle = 50% ± 1.5%
Low output jitter. Samples of peak-to-peak period jitter when a single global network is
used:
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–
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70 ps at 350 MHz
90 ps at 100 MHz
180 ps at 24 MHz
Worst case < 2.5% × clock period
Maximum acquisition time = 150 µs
Low power consumption of 5 mW
Global Clocking
Fusion devices have extensive support for multiple clocking domains. In addition to the CCC and
PLL support described above, there are on-chip oscillators as well as a comprehensive global clock
distribution network.
The integrated RC oscillator generates a 100 MHz clock. It is used internally to provide a known
clock source to the flash memory read and write control. It can also be used as a source for the PLLs.
Pr e li m i n a ry v1 . 7
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ACTEL [ Actel Corporation ]
