PAC5210
Power Application Controller
7. ARCHITECTURAL BLOCK DIAGRAM
Figure 7-1. Architectural Block Diagram
PAC5210
Power Application Controller
MULTI-MODE POWER
SWDIO, SWDCL
MANAGER
VHM
MULTI-
MODE
SWITCHING
SUPPLY
DRM
VP
CSM
VSSP, VSS, VSSA
DEBUG
32kB/16kB
FLASH
REGO
VSYS
VCCIO
VCC33
VCC18
LINEAR
REGU-
LATORS
(4)
ARM
CORTEX-M0
8kB/4kB
CORE
SRAM
APPLICATION SPECIFIC
POWER DRIVERS
PWM ENGINE
CLOCK
XIN, XOUT
CONTROL
OD (3)
OMx
TIMERS (4)
PWMAx, PWMBx,
PWMCx, PWMDx
PWM /
CC (14)
RTC
GPIO (27)
SPI
ENHSx
DEAD TIME
(7)
PAx, PCx, PDx, PEx
CONFIGURABLE
ANALOG FRONT END
BRIDGE
SPICSx, SPIMISO,
SPIMOSI, SPICLK
PGA/
CMP (3)
AMPx/CMPx/PHCx
WATCHDOG
DAC (2)
I2CSDA, I2CSCL
UARTRX, UARTTX
nRESET1
I2C
DATA ACQUISITION &
SEQUENCER
DAxP/PCMPx
DAxN
DIFF-PGA/
PCMP (4)
UART
10-BIT
ADC
ADx
AUTO
SAMPLING
AIOx
BUF6
PBTN
AIO
CONTROL
(10)
SYSTEM
CONTROL
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Rev 1.11‒May 3, 2017
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
