ADDC02808PB
250
MAXIMUM PEAK
POWER LIMIT
8
200
10W ave
PEAK POWER – W
100W ave
150
V
O
– V
50W ave
100
MAXIMUM CONTINUOUS
POWER LIMIT
50
7.5
0
7.4
–200 –100
7.8
12A STEP CHANGE
7.7
7.6
24A STEP CHANGE
7.9
8.1
0
25
50
100
75
PULSEWIDTH – ms
125
150
0
100
200
300
400
500
600
700
800
Figure 17. Largest On-State Power vs. Pulsewidth that
Maintains T
JMAX
≤
110
°
C at 90
°
C Baseplate
TRANSIENT RESPONSE
TIME – s
Figure 19. Predicted Response to 12 A and 24 A Step
Change in Load Current, di/dt = 12 A/
µ
s, for C
LOAD
=
1000
µ
F and R
ESR
= 10 m
Ω
The standard ADDC02808PB is designed to deliver large
changes, or pulses, in load current with minimum output volt-
age deviation and an ultrafast return to the nominal output
voltage. The compensation of the feedback loop is optimized,
and output stability is insured, for a broad range of external load
capacitance extending from 500
µF
(R
ESR
= 20 mΩ) to 4,000
µF
(R
ESR
= 2.5 mΩ). The variables that impact pulse performance
(the maximum output voltage deviation and the settling time)
are:
1. Size of step change in the output current.
2. Amount of external load capacitance.
3. Internal compensation of the feedback loop (factory set).
4. Connection from converter output to load.
Extensive modeling of the converter with ADI proprietary soft-
ware permits analysis and prediction of the impact each of these
parameters has on the pulse response. The analyses in this data
sheet are based on the load capacitance being comprised of
100
µF,
100 mΩ tantalum load capacitors such as the CSR21
style. Figure 18 is the prediction of the standard converter’s
response to a 24 A step change in load current (from 1 A to
25 A) with a load capacitance of 1,000
µF
(R
ESR
= 10 mΩ).
This is very close to the measured pulse response under the
same conditions shown in Figure 6.
8.1
Step Change
If the step change is less than 24 A, the pulse response will
improve. For instance, with a 12 A step change, Figure 19
shows a comparison of the response for a 24 A step change and
a 12 A step change in load.
Load Capacitance
Varying the external load capacitance and associated R
ESR
be-
tween the range of C
LOAD
= 500
µF
(R
ESR
= 20 mΩ) and C
LOAD
= 4,000
µF
(R
ESR
= 2.5 mΩ) results in the predicted waveforms
shown in Figures 20, 21, and 22. As can be seen, the larger the
capacitor, the smaller the deviation, but the longer the settling
time. Table I lists the maximum output voltage deviations and
settling times for the four combinations of C
LOAD
and R
ESR
mentioned above. Note that these are based on the standard
compensation for the feedback loop.
Table I. Output Response to a 24 A (1 A–25 A) Step in Load
Current (Standard Compensation)
C
LOAD
500
µF
1,000
µF
2,000
µF
4,000
µF
8.1
R
ESR
20 mΩ
10 mΩ
5 mΩ
2.5 mΩ
Typical
Deviation
–7%
–6%
–5%
–4%
Settling Time
(Within 1%)
150
µs
175
µs
200
µs
250
µs
See
Figure
20
18
21
22
8
8
7.9
7.9
V
O
– V
7.8
7.8
7.7
7.6
7.6
7.5
7.5
7.4
–200 –100
0
100
200
300
400
500
600
700
800
7.4
–200 –100
V
O
– V
7.7
TIME – s
0
100
200
300
400
500
600
700
800
Figure 18. Predicted Response to 24 A Step Change in
Load Current, di/dt = 12 A/
µ
s, for C
LOAD
= 1,000
µ
F and
R
ESR
= 10 m
Ω
TIME – s
Figure 20. Predicted Response for 24 A Step Load
Change in Load Current, di/dt = 12 A/
µ
s, for C
LOAD
= 500
µ
F and R
ESR
= 20 m
Ω
–8–
REV. A
AD [ ANALOG DEVICES ]
