AD1881A
t
RST_LOW
RESET
t
RST2CLK
BIT_CLK
t
RISECLK
SYNC
t
FALLCLK
BIT_CLK
Figure 1. Cold Reset
t
RISESYNC
SDATA_IN
t
FALLSYNC
t
SYNC_HIGH
SYNC
BIT_CLK
t
RST2CLK
SDATA_OUT
t
RISEDIN
t
FALLDIN
t
RISEDOUT
t
FALLDOUT
Figure 2. Warm Reset
Figure 5. Signal Rise and Fall Time
t
CLK_LOW
BIT_CLK
t
CLK_HIGH
t
CLK_PERIOD
SYNC
SLOT 1
SLOT 2
BIT_CLK
t
SYNC_LOW
SYNC
SDATA_OUT
WRITE
TO 0x26
DATA
PR4
DON’T
CARE
t
SYNC_HIGH
t
SYNC_PERIOD
SDATA_IN
t
S2_PDOWN
NOTE: BIT_CLK NOT TO SCALE
Figure 3. Clock Timing
Figure 6. AC Link Low Power Mode Timing
t
SETUP
RESET
BIT_CLK
SDATA_OUT
SYNC
SDATA_OUT
t
SETUP2RST
SDATA_IN, BIT_CLK
HI-Z
t
HOLD
t
OFF
Figure 4. Data Setup and Hold
Figure 7. ATE Test Mode
–6–
REV. 0
AD [ ANALOG DEVICES ]
