AD1981B
Indexed Control Registers
Reg Name
00h
02h
04h
06h
Reset
Master Volume
Headphones
Volume
Mono Volume
D15
X
MM
HPM
MVM
PHM
MCM
LVM
CVM
AM
OM
X
IM
X
EAPD
IDC1
D14
SE4
X
X
X
X
X
X
X
X
X
X
X
X
PR6
IDC0
D13
SE3
X
X
X
X
X
X
X
X
X
X
X
X
PR5
X
X
D12
SE2
LMV4
LHV4
X
X
X
LLV4
LCV4
LAV4
LOV4
X
X
X
PR4
X
X
D11
SE1
LMV3
LHV3
X
X
X
LLV3
LCV3
LAV3
LOV3
X
LIM3
X
PR3
D10
SE0
LMV2
LHV2
X
X
X
LLV2
LCV2
LAV2
LOV2
LS2
LIM2
X
PR2
D9
ID9
D8
ID8
D7
ID7
D6
ID6
X
X
X
X
M20
X
X
X
X
X
X
D5
ID5
X
X
X
X
X
X
X
X
X
X
X
X
X
D4
ID4
D3
ID3
D2
ID2
D1
ID1
D0
ID0
Default
0090h
8000h
8000h
8000h
8008h
LMV1 LMV0 RM*
LHV1 LHV0 RM*
X
X
X
X
X
X
X
X
X
RMV4 RMV3 RMV2 RMV1 RMV0
RHV4 RHV3 RHV2 RHV1 RHV0
MV4
MV3
MV2
MV1
MV0
0Ch Phone Volume
0Eh
10h
12h
16h
18h
MIC Volume
Line-In Volume
CD Volume
AUX Volume
PCM-Out Vol
PHV4 PHV3 PHV2 PHV1 PHV0
MCV4 MCV3 MCV2 MCV1 MCV0 8008h
RLV4 RLV3 RLV2 RLV1 RLV0
RCV4 RCV3 RCV2 RCV1 RCV0
RAV4 RAV3 RAV2 RAV1 RAV0
ROV4 ROV3 ROV2 ROV1 ROV0
X
X
X
X
X
RS2
RS1
RS0
8808h
8808h
8808h
8808h
0000h
8000h
0000h
000Xh
X605h
0000h
BB80h
BB80h
2000h
8080h
0000h
LLV1 LLV0 RM*
LCV1 LCV0 RM*
LAV1 LAV0 RM*
LOV1 LOV0 RM*
LS1
LS0
X
1Ah Record Select
1Ch Record Gain
20h
26h
28h
General-Purpose
Power-Down
Ctrl/Stat
Ext’d Audio ID
LIM1 LIM0 RM*
MIX
PR1
MS
PR0
RIM3 RIM2 RIM1 RIM0
X
REF
X
ANL
X
DAC
X
ADC
VRAS
VRA
SRF0
LPBK X
X
X
X
SRF7
X
X
X
SRF6
REVC1 REVC0 AMAP X
X
SPCV
X
X
SRF8
DSA1 DSA0 X
SPSA1 SPSA0 X
SRF5
SRF4
SRF3
SPDIF X
SPDIF X
SRF2
SRF1
2Ah Ext’d Audio Stat/ VFORCE X
Ctrl
2Ch PCM Front
DAC Rate
32h
PCM L/R
ADC Rate
SRF15
SRA15
V
EQM
CFD15
MXM
X
SLOT
16
DACZ
F7
T7
SRF14 SRF13
SRA14 SRA13
X
MAD
LBEN
SPSR1
X
SRF12 SRF11 SRF10 SRF9
SRA12 SRA11 SRA10 SRA9 SRA8 SRA7 SRA6
SPSR0 L
X
X
CC6
X
CC5
X
CC4
X
CC3
SYM
CC2
CHS
SRA5 SRA4 SRA3 SRA2 SRA1 SRA0
CC1
CC0
PRE
COPY /AUD PRO
3Ah SPDIF Control
60h
62h
64h
72h
74h
76h
EQ CTRL
EQ DATA
Mixer ADC,
Volume
Jack Sense
Serial
Configuration
Misc Control
Bits
BCA5 BCA4 BCA3 BCA2 BCA1 BCA0
CFD5 CFD4 CFD3 CFD2 CFD1 CFD0
X
JS1
MD
X
X
JS0
MD
INTS
MAD
ST
S4
CFD14 CFD13
X
X
X
X
CFD12 CFD11 CFD10 CFD9 CFD8 CFD7 CFD6
X
JS
MT2
LMG3 LMG2 LMG1 LMG0 RM*
JS
MT1
JS
MT0
X
X
F2
T2
JS1
EQB
X
JS0
EQB
JS1
TMR
X
JS0
TMR
X
RMG3 RMG2 RMG1 RMG0 8000h
JS1
ST
X
JS0
ST
JS1
INT
JS0
INT
0000h
REGM REGM
2
1
X
F6
T6
M
SPLT
F5
T5
REGM X
0
LODIS DAM
F4
T4
F3
T3
CHEN X
MAD
PD
S7
SPAL SPDZ SPLNK 7001h
FMXE X
F1
T1
F0
T0
2CMIC X
S6
S5
VREF VREF MBG1 MBG0 0000h
H
D
S3
S2
S1
S0
4144h
5374h
7Ch Vendor ID1
7Eh
Vendor ID2
REV7 REV6
REV5 REV4 REV3 REV2 REV1 REV0
NOTES
All registers not shown. Bits containing an X are assumed to be reserved.
Odd register addresses are aliased to the next lower even address.
Reserved registers should not be written.
Zeros should be written to reserved bits.
*For
AC ’97 compatibility, Bit D7 (RM) is only available by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, RM bit has no effect.
REV. B
–9–
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