AD421
TIMING CHARACTERISTICS1, 2, 3
(VCC = +3 V to +5 V, TA = TMIN to TMAX unless otherwise noted)
Parameter
(B Versions)
Units
Conditions/Comments
tCK
tCL
tCH
tDW
tDS
tDH
tLD
tLL
100
50
50
30
30
0
50
50
50
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Data Clock Period
Data Clock Low Time
Data Clock High Time
Data Stable Width
Data Setup Time
Data Hold Time
Latch Delay Time
Latch Low Time
Latch High Time
tLH
NOTES
1Guaranteed by characterization at initial product release, not production tested.
2See Figures 1 and 2.
3All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC ) and timed from a voltage level of (VIN + VIL )/2; tr and tf should not exceed 1 µs on any digital
input.
Specifications subject to change without notice.
CLOCK
WORD "N"
WORD "N +1"
1
1
0
1
1
0
0
1
0
0
1
1
0
0
1
1
1
0
0
1
DATA
LATCH
Figure 1. Serial Interface Waveforms (Normal Data Load)
tCK
tCL
CLOCK
tCH
tDH
tDS
DATA
tDW
tLD
tLL
LATCH
tLH
Figure 2. Serial Interface Timing Diagram
–3–
REV. C
ADI [ ADI ]
