AD712
OP AMP SETTLING TIME -
A MATHEMATICAL MODEL
The design of the AD712 gives careful attention to optimizing
individual circuit components; in addition, a careful trade-off
was made: the gain bandwidth product (4 MHz) and slew rate
(20 V/µs) were chosen to be high enough to provide very fast
settling time but not too high to cause a significant reduction in
phase margin (and therefore stability). Thus designed, the
AD712 settles to
±
0.01%, with a 10 V output step, in under
1
µs,
while retaining the ability to drive a 250 pF load capaci-
tance when operating as a unity gain follower.
If an op amp is modeled as an ideal integrator with a unity gain
crossover frequency of
ω
ο
/2π, Equation 1 will accurately de-
scribe the small signal behavior of the circuit of Figure 26a,
consisting of an op amp connected as an I-to-V converter at the
output of a bipolar or CMOS DAC. This equation would com-
pletely describe the output of the system if not for the op amp’s
finite slew rate and other nonlinear effects.
Equation 1.
V
O
–
R
=
I
IN
R(C
f
=
C
X
)
2
G
N
s
+
+
RC
f
s
+
1
ω
ο
ω
ο
When R
O
and I
O
are replaced with their Thevenin V
IN
and R
IN
equivalents, the general purpose inverting amplifier of Figure
26b is created. Note that when using this general model, capaci-
tance C
X
is EITHER the input capacitance of the op amp if a
simple inverting op amp is being simulated OR it is the com-
bined capacitance of the DAC output and the op amp input if
the DAC buffer is being modeled.
1/2
AD712
R
L
C
F
R
IN
V
IN
C
X
R
C
L
V
OUT
Figure 26b. Simplified Model of the AD712
Used as an Inverter
where
2
=op amp’s unity gain frequency
π
G
N
= “noise” gain of circuit
1
+
R
O
This equation may then be solved for C
f
:
Equation 2.
C
f
=
2
−
G
N
2
RC
X
ω
ο
+
(1
−
G
N
)
+
Rω
ο
Rω
ο
ω
ο
R
In either case, the capacitance C
X
causes the system to go from
a one-pole to a two-pole response; this additional pole increases
settling time by introducing peaking or ringing in the op amp
output. Since the value of C
X
can be estimated with reasonable
accuracy, Equation 2 can be used to choose a small capacitor,
C
F
, to cancel the input pole and optimize amplifier response.
Figure 27 is a graphical solution of Equation 2 for the AD712
with R = 4 kΩ.
60
50
In these equations, capacitor C
X
is the total capacitor appearing
the inverting terminal of the op amp. When modeling a DAC
buffer application, the Norton equivalent circuit of Figure 26a
can be used directly; capacitance C
X
is the total capacitance of
the output of the DAC plus the input capacitance of the op amp
(since the two are in parallel).
40
G
N
= 4.0
C
X
30
G
N
= 3.0
G
N
= 2.0
20
G
N
= 1.5
10
G
N
= 1.0
0
1/2
AD712
R
L
C
F
R
I
O
R
O
C
X
C
L
0
V
OUT
10
20
30
C
F
40
50
60
Figure 27. Value of Capacitor C
F
vs. Value of C
X
Figure 26a. Simplified Model of the AD712 Used as a
Current-Out DAC Buffer
–8–
REV. B
AD [ ANALOG DEVICES ]
