AD7245A/AD7248A
CIRCUIT INFORMATION
D/A SECTION
The AD7245A/AD7248A contains a 12-bit voltage mode digi-
tal-to-analog converter. The output voltage from the converter
has the same positive polarity as the reference voltage allowing
single supply operation. The reference voltage for the DAC is
provided by an on-chip buried Zener diode.
The DAC consists of a highly stable, thin-film, R–2R ladder and
twelve high-speed NMOS single-pole, double-throw switches.
The simplified circuit diagram for this DAC is shown in Figure 1.
The small signal (200 mV p-p) bandwidth of the output buffer
amplifier is typically 1 MHz. The output noise from the ampli-
fier is low with a figure of 25 nV/√Hz at a frequency of 1 kHz.
The broadband noise from the amplifier has a typical peak-to-
peak figure of 150
µV
for a 1 MHz output bandwidth. There is
no significant difference in the output noise between single and
dual supply operation.
VOLTAGE REFERENCE
Figure 1. D/A Simplified Circuit Diagram
The input impedance of the DAC is code dependent and can
vary from 8 kΩ to infinity. The input capacitance also varies
with code, typically from 50 pF to 200 pF.
OP AMP SECTION
The AD7245A/AD7248A contains an internal low noise buried
Zener diode reference which is trimmed for absolute accuracy
and temperature coefficient. The reference is internally con-
nected to the DAC. Since the DAC has a variable input imped-
ance at its reference input the Zener diode reference is buffered.
This buffered reference is available to the user to drive the cir-
cuitry required for bipolar output ranges. It can be used as a ref-
erence for other parts in the system provided it is externally
buffered. The reference will give long-term stability comparable
with the best discrete Zener reference diodes. The performance
of the AD7245A/AD7248A is specified with internal reference,
and all the testing and trimming is done with this reference. The
reference should be decoupled at the REF OUT pin and recom-
mended decoupling components are 10
µF
and 0.1
µF
capaci-
tors in series with a 10
Ω
resistor. A simplified schematic of the
reference circuitry is shown in Figure 3.
The output of the voltage mode D/A converter is buffered by a
noninverting CMOS amplifier. The user has access to two gain
setting resistors which can be connected to allow different out-
put voltage ranges (discussed later). The buffer amplifier is ca-
pable of developing up to 10 V across a 2 kΩ load to GND.
The output amplifier can be operated from a single positive
power supply by tying V
SS
= AGND = 0 V. The amplifier can
also be operated from dual supplies to allow a bipolar output
range of –5 V to +5 V. The advantages of having dual supplies
for the unipolar output ranges are faster settling time to voltages
near 0 V, full sink capability of 2.5 mA maintained over the en-
tire output range and elimination of the effects of negative offset
on the transfer characteristic (outlined previously). Figure 2
shows the sink capability of the amplifier for single supply
operation.
Figure 3. Internal Reference
DIGITAL SECTION
The AD7245A/AD7248A digital inputs are compatible with ei-
ther TTL or 5 V CMOS levels. All data inputs are static pro-
tected MOS gates with typical input currents of less than 1 nA.
The control inputs sink higher currents (150
µA
max) as a result
of the fast digital interfacing. Internal input protection of all
logic inputs is achieved by on-chip distributed diodes.
The AD7245A/AD7248A features a very low digital feedthrough
figure of 10 nV-s in a 5 V output range. This is due to the volt-
age mode configuration of the DAC. Most of the impulse is ac-
tually as a result of feedthrough across the package.
INTERFACE LOGIC INFORMATION—AD7245A
Figure 2. Typical Single Supply Sink Current vs.
Output Voltage
Table I shows the truth table for AD7245A operation. The part
contains two 12-bit latches, an input latch and a DAC latch.
CS
and
WR
control the loading of the input latch while
LDAC
con-
trols the transfer of information from the input latch to the
DAC latch. All control signals are level triggered; and therefore,
either or both latches may be made transparent, the input latch
by keeping
CS
and
WR
“LOW”, the DAC latch by keeping
LDAC
“LOW.” Input data is latched on the rising edge of
WR.
–8–
REV. A
AD [ ANALOG DEVICES ]
