AD768
If properly implemented, ground planes can perform a host of
functions on high speed circuit boards: bypassing, shielding,
current transport, etc. In mixed signal design, the analog and
digital portions of the board should be distinct from each other,
with the analog ground plane confined to the areas covering
analog signal traces and the digital ground plane confined to
areas covering the digital interconnects.
All analog ground pins of the DAC, reference, and other analog
output components, should be tied directly to the analog ground
plane. The two ground planes should be connected by a path
1/4 to 1/2 inch wide underneath or within 1/2 inch of the DAC
as shown in Figure 28. Care should be taken to ensure that the
ground plane is uninterrupted over crucial signal paths. On the
digital side, this includes the digital input lines running to the
DAC as well as any clock signals. On the analog side, this in-
cludes the DAC output signal, reference signal, and the supply
feeders.
The use of wide runs or planes in the routing of power lines is
also recommended. This serves the dual role of providing a low
series impedance power supply to the part, as well as, providing
some “free” capacitive decoupling to the appropriate ground
plane. Figure 29 illustrates the power plane layout used in the
AD768 evaluation board. The AD768 evaluation board uses a
four layer P.C. board which illustrates good layout practices as
discussed above.
It is essential that care be taken in the layout of signal and
power ground interconnects to avoid inducing extraneous volt-
age drops in the signal ground paths. It is recommended that all
connections be short, direct and as physically close to the pack-
age as possible, in order to minimize the sharing of conduction
paths between different currents. When runs exceed an inch in
length, some type of termination resistor should be considered.
The necessity and value of this resistor will be dependent upon
the logic family used.
For maximum ac performance, the DAC should be mounted
directly to the circuit board; sockets should be avoided since
they introduce unwanted capacitive coupling between adjacent
pins of the device.
POWER SUPPLY AND DECOUPLING
A clean digital supply may be generated using the circuit shown
in Figure 30. The circuit consists of a differential LC filter with
separate power supply and return lines. Lower noise can be at-
tained using low ESR (Equivalent Series Resistance) type elec-
trolytic and tantalum capacitors.
TTL/CMOS
LOGIC
CIRCUITS
FERRITE
BEADS
V
DD
100µF
ELECT.
10–20µF
TANT.
0.1µF
CER.
DCOM
+5V
DGND
+5V
POWER SUPPLY
Figure 30. Differential LC Filter for Single +5 V
Applications
APPLICATIONS
USING THE AD768 AS A MULTIPLYING DAC
The AD768 can be easily configured as a multiplying DAC
since I
REFIN
can be modulated from 1 mA to 7 mA. The refer-
ence amplifier sets the maximum multiplying bandwidth to 15
MHz, while any external capacitor to the NR node serves to
limit the bandwidth according to Figure 7. I
REFIN
can be easily
modulated by properly scaling and summing into the IREFIN
node the modulating signal. Figure 31 demonstrates how the
modulating signal VMOD can be properly scaled and converted
to a current via R
REFMOD
such that its peak current does not ex-
ceed 3.0 mA. Figure 32 shows the AD768’s typical distortion
versus the reference channel frequency.
AD768
6
R
REF
625Ω
3
1µF
VMOD
≤ ±3.0mA
R
REFMOD
REFOUT
IREFIN
R
REFMOD
VMOD
THD – dB
One of the most important external components associated with
high speed designs are the capacitors used to bypass the power
supplies. Both selection and placement of these capacitors can
be critical and, to a large extent, dependent upon the specifics of
the system configuration. The dominant consideration in the
selection of bypass capacitors for the AD768 is the minimization
of the series resistance and inductance. Many capacitors will
begin to look inductive at 20 MHz and above. Ceramic and film
type capacitors generally feature lower series inductance than
tantalum or electrolytic types.
It is recommended that each power supply to the AD768 be de-
coupled by a 0.1
µF
capacitor located as close to the device pins
as possible. Surface-mount chip capacitors, by virtue of their
low parasitic inductance, are preferable to through-hole types.
Some series inductance between the DAC supply pins and the
power supply plane may help to provide additional filtering of
high frequency power supply noise. This inductance can be gen-
erated by using small ferrite beads.
Figure 31. Typical Multiplying DAC Application
–75
–70
–65
I
REF
= 4.0+/–2 mA
I
REF
= 5.0+/–1 mA
–60
–55
I
REF
= 4.0+/–3 mA
–50
–45
–40
250
500
750
1000 1250 1500 1750
FREQUENCY – kHz
2000
2250 2500
Figure 32. Reference Channel Distortion vs. Frequency
REV. B
–13–
AD [ ANALOG DEVICES ]
