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AD9280ARS 参数 Datasheet PDF下载

AD9280ARS图片预览
型号: AD9280ARS
PDF下载: 下载PDF文件 查看货源
内容描述: 完整的8位, 32 MSPS , 95毫瓦的CMOS A / D转换器 [Complete 8-Bit, 32 MSPS, 95 mW CMOS A/D Converter]
分类和应用: 转换器
文件页数/大小: 24 页 / 368 K
品牌: AD [ ANALOG DEVICES ]
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AD9280
0
–3
APPLYING THE AD9280
THEORY OF OPERATION
SIGNAL AMPLITUDE – dB
–6
–9
–12
–15
–18
–21
–24
1.0E+6
The AD9280 implements a pipelined multistage architecture to
achieve high sample rate with low power. The AD9280 distrib-
utes the conversion over several smaller A/D subblocks, refining
the conversion with progressively higher accuracy as it passes
the results from stage to stage. As a consequence of the distrib-
uted conversion, the AD9280 requires a small fraction of the
256 comparators used in a traditional flash type A/D. A sample-
and-hold function within each of the stages permits the first
stage to operate on a new input sample while the second, third
and fourth stages operate on the three preceding samples.
1.0E+7
1.0E+8
FREQUENCY – Hz
1.0E+9
OPERATIONAL MODES
Figure 13. Full Power Bandwidth
50
40
30
20
10
A
I
B
REFBS = 0.5V
REFTS = 2.5V
CLOCK = 32MHz
0
–10
–20
–30
The AD9280 is designed to allow optimal performance in a
wide variety of imaging, communications and instrumentation
applications, including pin compatibility with the AD876-8 A/D.
To realize this flexibility, internal switches on the AD9280 are
used to reconfigure the circuit into different modes. These modes
are selected by appropriate pin strapping. There are three parts
of the circuit affected by this modality: the voltage reference, the
reference buffer, and the analog input. The nature of the appli-
cation will determine which mode is appropriate: the descrip-
tions in the following sections, as well as Table I should assist in
selecting the desired mode.
–40
–50
0
0.5
1.5
1.0
2.0
INPUT VOLTAGE – V
2.5
3.0
Figure 14. Input Bias Current vs. Input Voltage
Table I. Mode Selection
Modes
TOP/BOTTOM
Input
Connect
AIN
AIN
CENTER SPAN AIN
AIN
Differential
AIN Is Input 1
Input
Span
1V
2V
1V
2V
1V
MODE
Pin
AVDD
AVDD
REFSENSE
Pin
REF
REFTS
REFBS
AGND
AGND
Figure
18
19
Short REFSENSE, REFTS and VREF Together
AGND
Short REFTS and VREF Together
AVDD/2
AVDD/2
AVDD/2
AVDD/2 Short VREF and REFSENSE Together
AVDD/2 AGND
No Connect
AVDD/2 20
AVDD/2
AVDD/2 29
AVDD/2 Short VREF and REFSENSE Together
REFTS and
REFBS Are
Shorted Together
for Input 2
2V
External Ref
AIN
AVDD/2 AGND
AVDD
No Connect
No Connect
AVDD/2
AVDD/2
21, 22
2 V max AVDD
AGND
Span = REFTS
– REFBS (2 V max)
Short to
VREFTF
Short to 23
VREFBF
Short to 30
VREFBF
AD876-8
AIN
2V
Float or
AVSS
AVDD
No Connect
Short to
VREFTF
–8–
REV. D