AD9643
CHANNEL/CHIP SYNCHRONIZATION
The AD9643 has a SYNC input that allows the user flexible
synchronization options for synchronizing the internal blocks.
The SYNC feature is useful for guaranteeing synchronized
operation across multiple ADCs. The input clock divider can be
synchronized using the SYNC input. The divider can be enabled
to synchronize on a single occurrence of the SYNC signal or on
every occurrence by setting the appropriate bits in Register 0x3A.
The SYNC input is internally synchronized to the sample clock.
However, to ensure that there is no timing uncertainty between
multiple parts, the SYNC input signal should be synchronized
to the input clock signal. The SYNC input should be driven
using a single-ended CMOS type signal.
Using Bit 1 in Register 0x59, the SYNC input can be set to either
level or edge sensitive mode. If the SYNC input is set to edge
sensitive mode, Bit 0 of Register 0x59 can be used to determine
whether the rising or falling edge is used.
Rev. A | Page 28 of 36
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