AD9883A
employed to write and read the control registers through the
two-line serial interface port.
2-Wire Serial Register Map
The AD9883A is initialized and controlled by a set of registers,
which determine the operating modes. An external controller is
Table VI. Control Register Map
Write and
Read or
Read Only
Hex
Address
Default
Value
Register
Name
Bits
Function
00H
RO
7:0
Chip Revision An 8-bit register that represents the silicon revision level.
Revision 0 = 0000 0000.
01H*
R/W
7:0
01101001
PLL Div MSB This register is for Bits [11:4] of the PLL divider. Greater values mean
the PLL operates at a faster rate. This register should be loaded first
whenever a change is needed. This will give the PLL more time to lock.
02H*
R/W
R/W
7:4
7:3
1101****
PLL Div LSB Bits [7:4] of this word are written to the LSBs [3:0] of the
PLL divider word.
03H
01******
**001***
Bits [7:6] VCO Range. Selects VCO frequency range.
(See PLL description.)
Bits [5:3] Charge Pump Current. Varies the current that drives the
low-pass filter. (See PLL description.)
04H
05H
06H
07H
08H
R/W
R/W
R/W
R/W
R/W
7:3
7:0
7:0
7:0
7:0
10000***
10000000
10000000
00100000
10000000
Phase Adjust
ADC Clock Phase Adjustment. Larger values mean more delay.
(1 LSB = T/32)
Clamp
Placement
Places the Clamp signal an integer number of clock periods after the trail-
ing edge of the Hsync signal.
Clamp
Duration
Number of clock periods that the Clamp signal is actively clamping.
Hsync Output Sets the number of pixel clocks that HSOUT will remain active.
Pulsewidth
Red Gain
Controls ADC input range (contrast) of each respective channel.
Greater values give less contrast.
09H
0AH
R/W
R/W
7:0
7:0
10000000
10000000
Green Gain
Blue Gain
0BH
R/W
7:1
1000000
*
Red Offset
Controls dc offset (brightness) of each respective channel. Greater
values decrease brightness.
0CH
0DH
R/W
R/W
7:1
7:1
1000000
1000000
*
*
Green Offset
Blue Offset
0EH
R/W
7:0
0*******
*1******
**0*****
***0****
Sync Control
Bit 7 – Hsync Polarity Override. (Logic 0 = Polarity determined by
chip, Logic 1 = Polarity set by Bit 6 in register 0EH.)
Bit 6 – Hsync Input Polarity. Indicates polarity of incoming Hsync
signal to the PLL. (Logic 0 = Active Low, Logic 1 = Active High.)
Bit 5 – Hsync Output Polarity. (Logic 0 = Logic High Sync,
Logic 1 = Logic Low Sync.)
Bit 4 – Active Hsync Override. If set to Logic 1, the user can select
the Hsync to be used via Bit 3. If set to Logic 0, the active interface
is selected via Bit 6 in register 14H.
****0***
Bit 3 – Active Hsync Select. Logic 0 selects Hsync as the active
sync. Logic 1 selects Sync-on-Green as the active sync. Note that the
indicated Hsync will be used only if Bit 4 is set to Logic 1 or if both
syncs are active. (Bits 1, 7 = Logic 1 in register 14H.)
*****0**
******0*
Bit 2 – Vsync Output Invert. (Logic 1 = No Invert, Logic 0 = Invert.)
Bit 1 – Active Vsync Override. If set to Logic 1, the user can select
the Vsync to be used via Bit 0. If set to Logic 0, the active interface
is selected via Bit 3 in register 14H.
*******0
Bit 0 – Active Vsync Select. Logic 0 selects Raw Vsync as the output
Vsync. Logic 1 selects Sync Separated Vsync as the output Vsync.
Note that the indicated Vsync will be used only if Bit 1 is set to Logic 1.
REV. B
–15–
ADI [ ADI ]
